Abstract: Copper bus bars are formed between adjacent die on a wafer during the process flow. The bus bars are between 50 and 100 &mgr;m wide and between 2 and 5 &mgr;m deep. A barrier layer is formed between the bus bars and the die to prevent copper diffusion. A dielectric layer is deposited over the bus bars and die and etched with contacts and features, such as vias. A seed layer is subsequently deposited over the wafer, which allows electrical conductance between the bus bars and the die during a subsequent electroplating process to fill the features and contacts. The bus bars carry electroplating current from the die edge to the die center. As a result, current does not need to be carried by a low sheet resistivity seed layer from the wafer edge to the center. This allows the seed layer to be thinner and of materials other than copper. Further, thinner seed layers allow thicker barrier layer for more reliability.

Abstract: An integrated circuit structure (8) includes a plurality of solid state electronic devices and a plurality of conductive elements (12, 14) that electrically couple the electronic devices. The integrated circuit structure (8) also includes a dielectric layer (16) positioned between two or more of the conductive elements (12, 14). A liner (18) is positioned between at least a portion of the dielectric layer (16) and a conductive element (12, 14). The liner (18) is formed from a compound that includes silicon and either carbon and nitrogen.

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: A polishing slurry for CMP of Cu, which comprises a first complexing agent containing a heterocyclic compound which is capable of forming a water-insoluble complex with Cu, and a second complexing agent containing a heterocyclic compound which is capable of forming a slightly water-soluble or water-soluble complex with Cu to thereby provide at least one extra ligand subsequent to formation of the complex.

Abstract: First of all, a breakthrough process is performed for removing the polymer and oxidized residues remained on top surface of the hard-mask layers, wherein the breakthrough process utilizes a CFx-based mixed-gas, such as Ar/O2/CF4, to slightly flush out the top surface of the hard-mask layers so as to strip the polymer and oxidized residues remained thereon. Afterward, an etching process is performed to etch through the hard-mask layers until a predetermined thickness of the dielectric layer. Finally, another etching process is performed to etch through the hard-mask layer and the dielectric layer and form the damascene structure in the dielectric layer, wherein this etching process utilizes the mixed gas having chlorine, such as O2/Cl2.

Abstract: A method of fabricating a gate structure of a field effect transistor comprising processes of forming an &agr;-carbon mask and plasma etching a gate electrode and a gate dielectric using the &agr;-carbon mask. In one embodiment, the gate dielectric comprises hafnium dioxide.

Abstract: A method of protecting an underlying diffusion barrier layer in a dual damascene trench and via etch process with a coating of negative photoresist. The dual damascene process starts with via hole etching in an intermetal dielectric (IMD) layer. Next, the thin film barrier layer is deposited and patterned to fill the bottom of the vias. The key process step is a coating of negative photoresist which is exposed and developed to partially fill the via openings. This thick layer of negative photoresist in the vias protects the thin diffusion barrier layer from subsequent dual damascene etch processing.

Abstract: A semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, a layer of undoped silicate glass disposed on the dielectric layer, a layer of borophosphorous silicate glass on the layer of undoped silicate glass, and a planar dielectric layer disposed on the layer of borophosphorous silicate glass, the layers of undoped silicate glass, borophosphorous silicate glass, and planar dielectric together forming a pre-metal dielectric stack. The planar dielectric may include plasma-enhanced tetraethyl orthosilicate.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality. An alternating process can also be arranged by selection of pulse separation and/or pulse duration to achieve reduced conformality relative to a self-saturating, self-limiting atomic layer deposition (ALD) process. In still another arrangement, layers with anisotropic pore structures can be sealed by selectively melting upper surfaces. Blocking is followed by a self-limiting, self-saturating atomic layer deposition (ALD) reactions without significantly filling the pores.

Abstract: After a plurality of grooves are formed in an insulating film and in an anti-reflection film on the insulating film, a barrier metal film and a conductive film are deposited on the anti-reflection film such that each of the wiring grooves is filled therewith. Subsequently, the portions of the conductive film outside the grooves are removed by polishing and then the portions of the barrier metal film outside the wiring are removed by polishing. Thereafter, a foreign matter adhered to a surface to be polished during polishing is removed and then a surface of the anti-reflection film is polished.

Abstract: A method for achieving a predetermined electrical resistance of a semiconductor device metal line in a CMP process including providing a semiconductor process wafer comprising at least one dielectric layer for etching an opening through a thickness of the at least one dielectric layer; measuring a thickness of the at least one dielectric layer prior to etching the opening; etching the opening through a thickness of the at least one dielectric layer; measuring at least one dimension of the opening from which at least an opening depth is determined; forming a metal layer to fill the opening; and, performing a chemical mechanical polish (CMP) process to remove at least the metal layer overlying the opening level to form a metal filled opening according to a projected metal filled opening electrical resistance.

Abstract: A method is provided for forming a copper interconnect, the method including forming a sacrificial dielectric layer above a structure layer, forming an opening in the sacrificial dielectric layer and forming a copper layer above the sacrificial dielectric layer and in the opening. The method also includes forming the copper interconnect by removing portions of the copper layer above the sacrificial dielectric layer, leaving the copper interconnect in the opening. The method further includes removing the sacrificial dielectric layer above the structure and adjacent the copper interconnect, and forming a low dielectric constant dielectric layer above the structure and adjacent the copper interconnect.

Abstract: A method for improving CMP polishing uniformity and reducing or preventing cracking in a semiconductor wafer process surface by reducing stress concentrations adjacent to dummy features including providing a semiconductor wafer process surface including active features and dummy features formed adjacently to the active features to improve a CMP polishing uniformity said dummy features each shaped to define an enclosed area in said semiconductor wafer process surface plane comprising at least 5 corner portions; and, performing a CMP process on said semiconductor wafer process surface.

Abstract: On a substrate are sequentially formed a first interconnection 203, a diffusion barrier film 205 and a second insulating film 207, and on the upper surface of the second insulating film 207 is then formed a sacrificial film 213. Next, a via hole 211 and an interconnection trench 217 are formed, and on the sacrificial film 213 are then formed a barrier metal film 219 and a copper film 221. CMP for removing the extraneous copper film 221 and barrier metal film 219 are conducted in a two-step process, i. e., the first polishing where polishing is stopped on the surface of the barrier metal film 219 and the second polishing where the remaining barrier metal film 219 and the tapered sacrificial film 213 are polished.

Abstract: A bond pad of a semiconductor device capable of restraining dishing and having improved conductivity by a damascene technique using a copper pattern, includes first and second copper patterns of irregular lattice models, first and second dielectric layer patterns to connect the first and second copper patterns in the vertical direction, a line connection structure horizontally connecting the first and second copper patterns, and a conductivity improving layer formed on the first and second copper patterns. Dishing generated in planarizing the first and second copper patterns by a damascene technique can be restrained due to the first and second copper patterns of the lattice models. Also, the conductivity property of the bond pad can be improved by connecting the first and second copper patterns horizontally and in the vertical direction and further forming the conductivity improving layer on the first and second copper patterns.

Abstract: The present invention is directed to a method of controlling chemical mechanical polishing operations to control the duration of an endpoint polishing process. The method comprises providing a wafer having a layer of copper formed thereabove, performing a first timed polishing operation for a duration (t1) on the layer of copper at a first platen to remove a majority of the layer of copper, performing an endpoint polishing operation on the layer of copper at a second platen to remove substantially all of the layer of copper, determining a duration (t2ept) of the endpoint polishing operation performed on the layer of copper at the second platen, and determining, based upon a comparison between the determined duration (t2ept) of the endpoint polishing operation and a target value for the duration of the endpoint polishing operations, a duration (t1) of the timed polishing operation to be performed on a subsequently processed layer of copper at the first platen.

Abstract: A transmission type display includes a thin film transistor for driving a pixel electrode, which transistor is provided on a substrate, and a conductive shield layer provided at a position over the thin film transistor and under the pixel electrode. A first planarization film is formed to bury an irregular contour of the thin film transistor and the shield layer is disposed on the planarized surface of the first planarization film, and a second planarization film is formed to bury steps of the shield layer, and the pixel electrode is disposed on the planarized surface of the second planarization film. Since the transmission type display has the structure in which the conductive shield layer is put between the upper second planarization film and the lower first planarization film each of which is made from an insulating material, the shielding performance and the alignment characteristic of the display can be improved.

Abstract: A tantalum-based liner for copper metallurgy is selectively removed by chemical-mechanical planarization (CMP) in an acidic slurry of an oxidizer such as hydrogen peroxide, deionized water, a corrosion inhibitor such as BTA, and a surfactant such as Duponol SP, resulting in a high removal rate of the liner without appreciable removal of the exposed copper and with minimal dishing.

Abstract: A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is deposited overlying the substrate layer. The dielectric layer patterned to form interconnect trenches. An optional titanium adhesion layer may be deposited. An aluminum barrier layer is deposited overlying the interior surfaces of the trenches. A second barrier layer, comprising for instance titanium and titanium nitride, is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, the second barrier layer, and the aluminum barrier layer are polished down to the top surface of the dielectric layer to define the copper interconnects, and complete the fabrication of the integrated circuit device.

Abstract: According to one embodiment, a method of planarizing of a surface of a semiconductor substrate is provided. A copper layer is inlaid in a dielectric layer of the substrate. The semiconductor substrate is disposed opposite to a polishing pad and relative movement provided between the pad and the substrate. An electrolytic slurry containing abrasive particles is flowed over the substrate or the pad. A voltage is applied between the polishing pad and the substrate to perform electropolishing of the substrate. The rate of chemical mechanical polishing is controlled by the down force applied to a polishing head urging the substrate against the polishing pad.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: Holes are formed in a first insulating film deposited on a substrate. After depositing a first conducting film over the first insulating film including the holes, the first conducting film is subjected to first CMP, so as to form plugs from the first conducting film. Next, the first insulating film is subjected to second CMP with a polishing rate of the first insulating film higher than a polishing rate of the first conducting film, so as to planarize the first insulating film by eliminating erosion caused in a region of the first insulating film where the plugs are densely formed. After depositing a second insulating film on the planarized first insulating film, interconnect grooves are formed in the second insulating film. After depositing a second conducting film over the second insulating film including the interconnect grooves, the second conducting film is subjected to third CMP, so as to form buried interconnects from the second conducting film.

Abstract: A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating layer (46, 363). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (51), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (56-57) on opposite sides of and immediately adjacent the gate section. A conductive layer (61, 120) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: A method of forming a copper wiring in a semiconductor device. The method can prevent an increase of a dielectric constant of a low dielectric constant film and making bad deposition of a copper anti-diffusion film, due to infiltration of an organic solvent, an etch gas, etc. into the low dielectric constant film exposed at the side of a damascene pattern during a wet cleaning process for removing polymer generating when a portion of the low dielectric constant film is etched to form the damascene pattern or during a photoresist pattern strip process. In order accomplish these purpose, a CFXHY polymer layer is changed to a SiCH film using SiH4 plasma without removing the polymer layer formed at the side of the damascene pattern. Therefore, infiltration of an organic solvent or an etch gas can be prevented due to the SiCH film having a condensed film quality and a good mechanical strength.

Abstract: A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.

Abstract: A method of manufacturing is described wherein a semiconductor device has a substrate as workpiece with an insulation film formed on the substrate, openings formed inside the insulation film, a first conductive film is formed inside the openings and on a surface of the insulation film, a second conductive film is formed on the first conductive film, and the first and the second conductive films are formed inside openings by planarizing a surface of second conductive film and a surface part of the first conductive film with a fixed abrasive tool. The method includes supplying a first processing liquid, planarizing the surface of the second conductive film with the first processing liquid and the fixed abrasive tool, switching the supply of liquid from a first processing liquid to a second processing liquid, and planarizing the surface of second conductive film and the surface of part of the first conductive film with the second processing liquid and the fixed abrasive tool.

Abstract: A first depressed portion is formed on an insulating film. A burying material is applied onto the first depressed portion and the insulating film to bury the first depressed portion. Chemical mechanical polishing of the burying material is performed until the insulating film is exposed, thereby leaving the burying material only in the first depressed portion. A resist having a pattern of a second depressed portion that overlaps the first depressed portion is formed on the insulating film in which the burying material has been buried. The burying material and the insulating film are etched to a predetermined depth using the resist as a mask to form the second depressed portion. The resist and the burying material left are removed after the step of etching. A conductive material is deposited in the first depressed portion and the second depressed portion.

Abstract: A barrier metal layer constituted of a TiN layer and a Ti layer is formed on a surface of an interlayer insulating film and on an inside surface of an interconnection recess formed in the interlayer insulating film while a substrate is maintained at a temperature of at least 200° C. and lower than 300° C. The interconnection recess is filled with a conductive layer and an extra part of the conductive layer that is deposited on the interlayer insulating film is removed through such a polishing process to form a conductive plug. In the process of forming the barrier metal layer, as the substrate is maintained at the temperature, the residual stress in the deposited barrier metal layer can be reduced. Accordingly, it is achieved to suppress peeling which occurs at the interface between the barrier metal layer and the interlayer insulating film in the polishing process.

Abstract: In a semiconductor integrated circuit wherein an interlayer insulating film is formed over a semiconductor substrate having a semiconductor device formed thereover; and an interconnection embedded in an interconnection groove in the interlayer insulating film is formed by the deposition of a metal film such as copper and polishing by the CMP method, another interlayer insulating film over the interconnection and interlayer insulating film is formed to have a blocking film, a planarizing film and an insulating film. As the planarizing film, a film having fluidity such as SOG is employed.

Abstract: A planarization method includes providing a metal-containing surface (preferably, a Group VIII metal-containing surface, and more preferably a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes a halogen and a halide salt.

Abstract: An improved and new process for fabricating dual damascene copper, in which trench/via liner removal from porous low-k dielectric, is performed using a new RIE chemistry of CF4/H2, to etch SiN and SiC liners. Prior to the new process, convention liner etching produced the following deleterious results: a) Cu re-deposition by sputtering, b) polymer deposits, and c) surface roughening of the porous low-k IMD dielectric. Process details are: CF4/H2 based with approximate gas flow ratios of greater than 10 to 1, hydrogen to carbon tetra-fluoride. A nominal flow ratio of 300 to 20, hydrogen to carbon tetra-fluoride, or 15 to 1, was developed.

Abstract: A method of forming a narrow copper line structure, embedded in an opening in an insulator layer, in which the defect count of the narrow copper line structure is minimized, has been developed. The method features a combination of processes applied to a copper layer prior to subjection of the copper layer to a chemical mechanical polishing, (CMP), procedure, used to define the narrow copper line structure. A thin compressive layer is first formed on the top surface of the copper layer, followed by a low temperature anneal. These procedures increase the number of nucleation sites, and grain size of the copper layer, resulting in less damage to the treated copper layer, as a result of a subsequent CMP procedure, when compared to counterpart copper layers, subjected to the same CMP procedure, however without experiencing the overlying, thin compressive layer, followed by the low temperature anneal.

Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate, and a wiring line groove is formed in the insulating film. Then, a conductive film is formed to fill the wiring line groove and to cover the insulating film. The conductive film is removed using a CMP polishing method until the insulating film is exposed, to complete a wiring line. Subsequently, a front side of the semiconductor substrate is rinsed on which the wiring line is formed, and then a back side of the semiconductor substrate is rinsed while supplying to the front side of the semiconductor substrate, a protection solution for forming a protection film in an exposed surface of the wiring line.

Abstract: The present invention provides a permanent protective hardmask which protects the dielectric properties of a main dielectric layer having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask further includes a single layer or dual layer sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers and the permanent hardmask layer may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants.

Abstract: A method of converting a hydrophobic surface of a dielectric layer to a hydrophilic surface is described. That method comprises forming on a substrate a dielectric layer that has a hydrophobic surface, then coupling a hydrophilic component to the surface of the dielectric layer. Also described is a method for making a semiconductor device that employs this technique after polishing a conductive layer, which may comprise copper.

Abstract: A method of forming wiring of a uniform film thickness using a damascene process is proposed. Tantalum nitride, copper, another copper, and another tantalum nitride, for example, all constituting conductive films of different polishing rates, are overlayed on the top layer of an insulating film in which one wiring groove and another wiring groove are formed. The film thickness of the tantalum nitride, the copper, the other copper, and the other tantalum nitride is set and formed so that the height of the surface of the tantalum nitride formed on a silicon oxide film excluding the one wiring groove matches the height of the surface of the other tantalum nitride formed on the top layer of the one wiring groove. Subsequently, polishing takes over to complete the forming process.

Abstract: The invention relates to a method for directly patterning a low-k dielectric layer by a high energy flow without using any photoresist layer, so that the exposed portion of the low-k dielectric layer is cured and becomes insoluble to the developing solution. The unexposed portion of the low-k dielectric layer remains soluble to the developing solution and will be removed in the developing process. The performance and reliability of the devices are improved and the fabrication processes are simplified.

Abstract: Ions are implanted into the dielectric layer and/or barrier layer over a semiconductor substrate to change the polish rates of either or both layers during formation of a shallow trench isolation (STI) structure. The ion implantation can change or affect the polish rates of the material and the polish selectivity, and reduce or minimize unwanted topography resulting from chemical mechanical polishing (CMP). After CMP, the resulting STI structure has a more uniform and smooth topography.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.

Abstract: A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.

Abstract: A method for disposing metal wiring on the surface of an insulating film formed on a semiconductor substrate. A recess is formed in the insulating film, and a metal wiring film composed of a metal wiring material is laminated on the insulating film having the recess formed therein. Further, the metal wiring film laminated on a surface area outside the recess in the insulating film is selectively removed. Thereafter, the metal wiring film laminated above the recess is polished by chemical mechanical polishing.

Abstract: A method of forming a self-aligned contact pad for use in a semiconductor device, including: forming a gate having a gate mask formed thereon on a semiconductor substrate, the semiconductor substrate including an active region and a non-active region, forming a spacer on both sidewalls of the gate and the gate mask, forming an interlayer insulating layer over the entire surface of the semiconductor substrate, the interlayer insulating layer including an opening formed on the active region of the semiconductor substrate, forming a conductive material layer over the entire surface of the semiconductor substrate to cover the interlayer insulating layer, etching-back the conductive material layer until the interlayer insulating layer is exposed, and performing a multi-step CMP process to form contact pads in the opening of the interlayer insulating layer, such that the contact pads are electrically insulated from each other.

Abstract: In the chemical mechanical polishing of copper-containing substrates, a rinse treatment is carried out with an oxidizing agent, such as hydrogen peroxide, so as to substantially completely oxidize and, thus, passivate exposed copper surface areas. Moreover, by using the oxidizing agent, organic additives required for efficient polishing performance may be effectively removed.

Abstract: Method and structure use support layers to assist in planarization processes to form conductive materials (e.g., a Group VIII metal) in an opening. Further, such method and structure may use a Group VIII metal as an etch stop or end point for the planarization process with subsequent etching to remove undesired portions of the Group VIII metal. One exemplary method of providing a conductive material in an opening includes providing a substrate assembly having at least one surface and providing an opening defined through the surface of the substrate assembly. The opening is defined by at least one surface. At least one conductive material (e.g., at least one Group VIII metal such platinum and/or rhodium) is formed within the opening on the at least one surface defining the opening and on at least a portion of the substrate assembly surface. A support film (e.g., an oxide material) is formed over the conductive material and a fill material (e.g.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.

Abstract: Peeling between a bonding pad and an insulating film which underlies the bonding pad is to be prevented. A laminate film constituted mainly by W which is higher in mechanical strength than a wiring layer using an Al alloy film as a main conductive layer and than a bonding pad, is formed within an aperture formed in silicon oxide films and is interposed between the wiring line and the bonding pad.

Abstract: A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

Abstract: A Dynamic Random Access Memory is fabricated in a semiconductor body of a first conductivity type in which there have been formed an array of memory cells which each include a trench capacitor and a vertical Insulated Gate Field Effect Transistor (IGFET). Each IGFET includes first and second output regions of a second opposite conductivity type and a gate which is separated from a surface of the semiconductor body by a gate dielectric layer. A gate electrode connected to the gate is formed using a Damascene process with insulating sidewall spacer regions being formed before the gate electrode is formed. Borderless contacts, which are self aligned, are made to the first output regions of each transistor using a Damascene process.

Abstract: A method of cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer, exposing the first metal layer. Then, a post-etching cleaning step is carried out to clean the dual damascene opening, and there are two types of cleaning methods. The first method uses a fluorine-based solvent to clean the dual damascene opening. An alternative cleaning method uses a hydrogen peroxide based solvent at a high temperature, followed by a hydrofluoric acid solvent cleaning step. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.