Simulating Electronic Device Or Electrical System Patents (Class 703/13)
  • Patent number: 9418084
    Abstract: Embodiments of the present invention utilize context subsystems to logically group resources according to context. Such context subsystems can be nested (i.e. hierarchical), and thus further simplify the complex configuration relationships encountered with complex systems. Higher level (i.e. parent) context subsystems contain at least one resource that is utilized by a lower level (i.e. child) component, subsystem, or context subsystem. Context subsystems can be hierarchically arranged in single- and multi-parent arrangements and single- and multi-child arrangements. The number of context subsystem hierarchical levels is virtually unlimited and is generally dictated by the complexity of the system and the corresponding simplification needs of the configuration technology being utilized to configure the system. Context subsystems are applicable and useful in a configuration environment for virtually any configurable system amenable to contextual groupings of resources.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: August 16, 2016
    Assignee: Versata Development Group, Inc.
    Inventor: Kevin R. Plain
  • Patent number: 9418020
    Abstract: Interaction is evaluated between a computer system cache and at least one entity that submits a stream of references corresponding to location identifiers of data storage locations. The reference stream is spatially sampled by comparing a hash value of each reference with a threshold value and selecting only those references whose hash value meets a selection criterion. Cache utility values are then compiled for those references. In some embodiments, the compiled cache values may then be corrected for accuracy as a function of statistics of those location identifiers over the entire stream of references and of the sampled references whose hash values satisfied the selection criterion. Alternatively, a plurality of caching configurations is selected and the selected references are applied as inputs to a plurality of caching simulations, each corresponding to a different caching configuration. A resulting set of cache utility values is then computed for each caching simulation.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: August 16, 2016
    Assignee: CLOUD PHYSICS, INC.
    Inventors: Carl A. Waldspurger, Irfan Ahmad, Alexander Garthwaite, Nohhyun Park
  • Patent number: 9413380
    Abstract: A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 9, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Conte, Maria Giaquinta
  • Patent number: 9411918
    Abstract: A system, method, and computer program product for extending device model parameter specification flexibility when using a subcircuit wrapper. Embodiments facilitate device modeling by allowing a modeling engineer to eliminate the explicit specification of a large set of wrapped device instance parameters as parameters to the subcircuit wrapper itself. A circuit designer may now use the subcircuit wrapper to specify an instance of the subcircuit without having to explicitly provide values for all such parameters. The simulator program's built-in device model calculates its default parameter values, which are often the result of complex expressions involving the other parameters, resulting in more accurate simulations. Subcircuit wrappers no longer need to be explicitly regenerated when a new version of the wrapped device model becomes available for the simulator (e.g., one that supports additional instance parameters that were not present on the earlier version when the subcircuit wrapper was created).
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: August 9, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: John O'Donovan, Jushan Xie, Saibal Saha
  • Patent number: 9405686
    Abstract: Cache utility curves are determined for different software entities depending on how frequently their storage access requests lead to cache hits or cache misses. Although possible, not all access requests need be tested, but rather only a sampled subset, determined by whether a hash value of each current storage location identifier (such as an address or block number) meets one or more sampling criteria. The sampling rate is adaptively changed so as to hold the number of location identifiers needed to be stored to compute the cache utility curves to within a set maximum limit.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: August 2, 2016
    Assignee: CLOUD PHYSICS, INC
    Inventors: Carl A Waldspurger, Alexander Garthwaite, Nohhyun Park, Irfan Ahmad
  • Patent number: 9383738
    Abstract: A method of high fidelity modeling an electrical power system of an aircraft, includes among other things, identifying electrical, mechanical, thermal, and EMI characteristics of the electrical power system; applying at least one circuit-based solver to model to at least one of the electrical characteristics; and applying, simultaneously with the circuit-based solver and in real-time, a field-based solver to model the remaining electrical, mechanical, thermal, and EMI characteristics.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: July 5, 2016
    Assignee: GE AVIATION SYSTEMS LLC
    Inventors: Hao Huang, Xiaochuan Jia
  • Patent number: 9378168
    Abstract: A circuit arrangement and program product for communicating data in a processing architecture comprising a plurality of interconnected IP blocks. Transmitting IP blocks may transmit messages to a shared receive queue for a first IP block. Receipt of the messages at the shared receive queue may be controlled based on receive credits allocated to each transmitting IP block. The allocation of receive credits for each transmitting IP block may dynamically managed such that the allocation of receive credits may be dynamically adjusted for each transmitting IP block based at least in part on message traffic associated with each transmitting IP block and/or a priority associated with each transmitting IP block.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey D. Brown, Robert A. Shearer
  • Patent number: 9363145
    Abstract: Systems and methods are provided for programmatically simulating one or more system conditions for a network resource using one or more services. In one implementation, a server receives a request to initiate a treatment. The request identifies a treatment definition. The server determines, based on the treatment definition, the one or more services and deploys the one or more services to the network resource. The one or more services simulate the one or more system conditions.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 7, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Luis Felipe Cabrera, Peter N. De Santis
  • Patent number: 9362837
    Abstract: The invention relates to a method for feeding electrical current into an electrical, three-phase power supply system having a first phase, a second phase and a third phase with a first voltage, a second voltage and a third voltage at a power supply system frequency, comprising the steps of: measuring the first, second and third voltages, transforming the first, second and third voltages into a positive phase-sequence voltage system and a negative phase-sequence voltage system according to the method of symmetrical components, calculating a first desired current, a second desired current and a third desired current for feeding into the first, second and third phases of the power supply system, wherein the first, second and third desired currents are calculated on the basis of at least one value of the positive phase-sequence voltage system and/or the negative phase-sequence voltage system.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: June 7, 2016
    Assignee: WOBBEN PROPERTIES GMBH
    Inventors: Volker Diedrichs, Alfred Beekmann
  • Patent number: 9350710
    Abstract: A method includes connecting to a client at a Virtual Private Network (VPN) device in a cloud system; forwarding requests from the client for the Internet or public clouds accordingly; and, for requests for an enterprise associated with the client, contacting a topology controller to fetch a topology of the enterprise, causing a tunnel to be established from the enterprise to the VPN device, and forwarding the requests for the enterprise through the tunnel. A cloud system and VPN system are also described. Advantageously, connections between the cloud and on-premises proxy are dynamic, on-demand and orchestrated by the cloud. Security is provided at the edge—there is no need to punch any holes in the existing on-premises firewalls.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: May 24, 2016
    Assignee: Zscaler, Inc.
    Inventors: Sudhindra P. Herle, Patrick Foxhoven
  • Patent number: 9342638
    Abstract: An improved approach is provided to implement performance checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis, where the two designs are checked to see if they are equivalent on the transaction-level. Thereafter, the outputs for the transactions are analyzed relative to delay time periods, which allows verification and identification of possible performance issues and differences between the two designs.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: May 17, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Antonio Celso Caldeira, Jr., Rajeev Kumar Ranjan, Marcus Vinicius da Mata Gomes
  • Patent number: 9344499
    Abstract: Techniques are described regarding providing consumers with devices on which digital content appropriate for those consumers has been loaded, such as digital media player devices or other consumer devices that are able to play or otherwise present digital media loaded on those devices. In some situations, when a consumer orders such a digital media player or other consumer device from a merchant (or other distributor of the device), the merchant preloads a copy of the device with digital media content before delivering that device to the consumer or other specified recipient, such as digital media items that are automatically selected in a personalized manner for the recipient to whom the device will be sent. This abstract is provided to comply with rules requiring an abstract, and is submitted with the intention that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 17, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Steven Kessel, William Dugald Carr, Samuel Stevens Heyworth
  • Patent number: 9336336
    Abstract: Disclosed is a method of designing a dental restoration for a patient, wherein the method includes providing one or more 2D images, where at least one 2D image includes at least one facial feature; providing a 3D virtual model of at least part of the patient's oral cavity; arranging at least one of the one or more 2D images relative to the 3D virtual model in a virtual 3D space such that the 2D image and the 3D virtual model are aligned when viewed from a viewpoint, whereby the 3D virtual model and the 2D image are both visualized in the 3D space; and modeling a restoration on the 3D virtual model, where the restoration is designed to fit the facial feature of the at least one 2D image.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: May 10, 2016
    Assignee: 3SHAPE A/S
    Inventors: Nikolaj Deichmann, Tais Clausen, Rune Fisker, Henrik Öjelund
  • Patent number: 9330424
    Abstract: A system and method for performing a hypothetical power management analysis on a distributed computer system uses chronologically consecutive snapshots of the distributed computer system. The snapshots are used to extract demands of clients running in the distributed computer system for a resource for different time intervals, which are then stitched together to produce a workload trace. The snapshots and the workload trace are used to construct modeling scenarios for the distributed computer system. The modeling scenarios are used to perform analyzes to simulate the operation of the distributed computer system during which the power management module is enabled to compute potential power savings.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 3, 2016
    Assignee: VMware, Inc.
    Inventors: Aashish Parikh, Rohit Bhoj, Pradeep Padala, Mustafa Uysal, Anne Holler
  • Patent number: 9323577
    Abstract: Operating profiles for consumers of computing resources may be automatically determined based on an analysis of actual resource usage measurements and other operating metrics. Measurements may be taken while a consumer, such as a virtual machine instance, uses computing resources, such as those provided by a host. A profile may be dynamically determined based on those measurements. Profiles may be generalized such that groups of consumers with similar usage profiles are associated with a single profile. Assignment decisions may be made based on the profiles, and computing resources may be reallocated or oversubscribed if the profiles indicate that the consumers are unlikely to fully utilize the resources reserved for them. Oversubscribed resources may be monitored, and consumers may be transferred to different resource providers if contention for resources is too high.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: April 26, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Michael David Marr, Matthew D. Klein
  • Patent number: 9323505
    Abstract: Systems and methods are provided for handling database deadlocks induced by database-centric applications (DCAs). SQL statements and transactions associated with the DCAs are analyzed and parsed to generate Petri net models. A supervisory modeler generates augmented Petri net models based on the Petri net models, which are used in generating supervisory control. The supervisory control is used in handling database deadlocks.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: April 26, 2016
    Assignee: Accenture Global Services Limited
    Inventors: Mark Grechanik, Qing Xie, Chen Fu
  • Patent number: 9317327
    Abstract: In accordance with aspects of the disclosure, systems and methods are provided for generating one or more potential configurations corresponding to one or more parameters used for computing infrastructure planning by determining a sizing grammar for each of the one or more potential configurations corresponding to the one or more parameters, interpreting the sizing grammar based on one or more grammar rules to output configuration information for each of the one or more potential configurations, and translating the configuration information for each of the one or more potential configurations based on one or more motif descriptions to output resource information for each of the one or more potential configurations.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 19, 2016
    Assignee: BMC Software, Inc.
    Inventor: Sudheer Apte
  • Patent number: 9316689
    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: April 19, 2016
    Assignee: Breker Verification Systems
    Inventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
  • Patent number: 9313216
    Abstract: The present disclosure provides a method and system for monitoring an application. The method includes creating a simulated system service; establishing a connection with a function in a device driver that manages an Input/Output (I/O) channel of the device; intercepting data transmitted from the application to the function in the device driver that manages the I/O channel of the device; replacing, based on the intercepted data, a system service requested by the application with a corresponding simulated system service; and recording a request received by the simulated system service and forwarding the request to an analysis module for analysis.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: April 12, 2016
    Assignee: Beijing Netqin Technology Co., Ltd.
    Inventors: Yang Zeng, Huaguo Shi, Wei Yang, Yaowei Chen, Yu Lin, Shihong Zou
  • Patent number: 9311444
    Abstract: A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: April 12, 2016
    Assignee: Sandia Corporation
    Inventor: John Teifel
  • Patent number: 9311437
    Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: April 12, 2016
    Assignee: Synopsys, Inc.
    Inventors: Neville A. Clark, James R. Torossian
  • Patent number: 9285425
    Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 15, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 9286427
    Abstract: Described herein are systems and methods for a partitioned extraction-simulation technique that efficiently combines a partitioned extraction technique and a partitioned simulation technique by removing and not performing particular steps of the techniques to provide a more efficient netlist extraction and circuit simulation process. In some embodiments, a plurality of circuit simulators directly receive and process a plurality of sub-region netlists that are based on a spatial partitioning of the IC layout. In further embodiments, an EDA hybrid cloud system is implemented using pipelining and serializing of memory data. In these embodiments, an overall EDA process is divided into a plurality of pipelined stages to accelerate the computational speed of the overall EDA process. In further embodiments, EDA data is transferred, over a network, from a memory of one computer system directly to a memory of another computer system by serializing the EDA data.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 15, 2016
    Assignee: Gear Design Solutions
    Inventors: Altan Odabasi, Murat Becer, Mustafa Yazgan, Lei Yin, John Lee
  • Patent number: 9280911
    Abstract: A context-aware training system senses sensing a user action that may expose the user's computer to a cybersecurity threat. The system selects training action from a collection of available training actions and causes the training action to be selected to the user.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 8, 2016
    Assignee: Wombat Security Technologies, Inc.
    Inventors: Norman Sadeh-Koniecpol, Kurt Wescoe, Jason Brubaker, Jason Hong
  • Patent number: 9282201
    Abstract: A system for creating and editing image and or text-based projects includes a server connected to a network and having access a processor and a data repository, and software running from a non-transitory physical medium, the software providing for establishing a client-server connection between the server and at least one user-operated computing appliance connected to the network, initiating and maintaining an active data session between one or more users involved in project creation and or in project editing through a graphics user interface (GUI), establishing a layout grid and defining gridlines as snap-to targets, establishing snap guides for specified assets to be placed on a canvass in an image and or text-based project, and establishing a distance threshold representing the distance between an asset and a gridline before snapping occurs, selectively de-activating or deleting gridlines for snap-to functionality with certain assets based on breach of an asset population threshold.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: March 8, 2016
    Assignee: Interactive Memories Inc.
    Inventors: Aryk Erwin Grosz, Dan Schult
  • Patent number: 9268622
    Abstract: A system and method may generate executable block diagrams having blocks that run in accordance with message-based execution semantics. A message may include an input data payload that does not change over time, and the message may persist for only a determined time interval during execution of block diagram. A verification engine may provide one or more tools for evaluating and verifying operation of message-based blocks. The verification engine may support one or more verification blocks that may be added to the block diagram and associated with the diagram's message-based blocks. The verification blocks may capture and present messages exchanged among the message-based blocks. The verification blocks may also specify an expected interaction of messages, and determine whether the actual messages are equivalent to the expected interaction.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: February 23, 2016
    Assignee: THE MATHWORKS, INC.
    Inventors: Alan J. Moore, Ebrahim Mehran Mestchian
  • Patent number: 9269173
    Abstract: An information processing apparatus includes: a resistance value acquiring unit that acquires a resistance value of at least one component corresponding to a physical quantity that is transmitted between two components, using inter-component information having component identifiers respectively indicating two components; a display information generating unit that generates, using the inter-component information, display information for displaying a transmission path diagram, which is an image showing a transmission path having nodes respectively associated with at least two components, and is an image in which information indicating the resistance value acquired by the resistance value acquiring unit is arranged at a node associated with at least one component from which the resistance value has been acquired; and an output unit that outputs the display information generated by the display information generating unit.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: February 23, 2016
    Assignee: SOFTWARE CRADLE CO., LTD.
    Inventor: Jun Eto
  • Patent number: 9262308
    Abstract: A system generates a test path set in a very efficient manner. The test path set may be tailored to test a target physical system, such as a complex set of source code, a manufacturing line of multiple process nodes, or other physical system. The system may generate the test path set to meet certain goals in testing the target physical system, for example comprehensive testing of system paths, system nodes, or particular subsets. As one example, the system may efficiently generate a test path set that uses the minimum number of test paths to test a coverage goal, for example traversing each of the prime paths in the target physical system.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: February 16, 2016
    Assignee: Accenture Global Services Limited
    Inventors: Anurag Dwarakanath, Aruna Jankiti
  • Patent number: 9245074
    Abstract: A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget. The method also includes computing power assertions, performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, and reducing a weighting of the power assertions relative to the timing constraints based on the degradation. The executing the performing the re-synthesis, the comparing, and the reducing are done iteratively until the degradation is below a threshold value.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Pinaki Chakrabarti, Kaustav Guha, Ricardo H. Nigaglioni, Sourav Saha
  • Patent number: 9246629
    Abstract: A dynamically-reconfigurable multiband multiprotocol communications jamming system and method is provided that are particularly suited for the generation of effective radio-frequency waveforms/noise output that successively translates up and down the RF spectrum. The system and method are particularly suited for strategically targeting specific frequencies in order to disrupt a communications network or networks, and can be rapidly deployed via delivery platforms, such as artillery and other projectile mechanisms, remote operated vehicles (unmanned aerial, sea or land systems) or targeted air or land delivery via manned assets or automated or robotic support means, or manual delivery by personnel.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: January 26, 2016
    Assignee: Talpha Technologies, Inc.
    Inventors: Timothy W. Coleman, Dondon B. Gabriel, Boris Kogan
  • Patent number: 9229441
    Abstract: A system construction supporting tool that supports construction of a programmable controller system, the system construction supporting tool including: a product-specification storage unit that stores therein information related to product specifications of units to be used as elements for constructing the programmable controller system; an arranged-unit-information storage unit that stores therein information related to arrangements of units already arranged in an edition operation on a display screen; a unit-list-display control unit that extracts arrangeable units based on the information stored in the arranged-unit-information storage unit and the information stored in the product-specification storage unit; and a unit-list display unit that displays a list of the units extracted by the unit-list-display control unit on the display screen.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: January 5, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Nakamura, Yuzuru Tone, Koji Aoyama, Tomohiro Okada
  • Patent number: 9229831
    Abstract: A test device is provided for testing a device under test (DUT) having a control interface compliant with a standard selected from a plurality of standards each supporting a common set of management data input/output (MDIO) and non-MDIO control signals. The test device includes a test interface and an integrated control interface. The integrated control interface adapts to the standard with which the control interface of the DUT complies, so that the integrated control interface directly and fully controls the DUT via at least the common set of MDIO and non-MDIO control signals. The integrated control interface exchanges control signals selected from the common set of MDIO and non-MDIO control signals with the control interface of the DUT to monitor the DUT and thereby obtain status information about the DUT.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: January 5, 2016
    Assignee: Viavi Solutions Deutschland GmbH
    Inventors: Reiner Schnizler, Paul Brooks
  • Patent number: 9218440
    Abstract: This disclosure describes a design tool that verifies timing of an integrated circuit design by partitioning the integrated circuit design's gate-level netlist into target cell partition netlists and performs transistor-level circuit simulation on each target cell partition netlist. The design tool performs a back tracing procedure on each target sequential cell to define the target cell partition netlists. The design tool then identifies timing modes that enable valid logical paths through the target cell partition netlists from source sequential cells to the target sequential cells. In turn, the design tool performs transistor-level circuit simulation (e.g., SPICE simulations) on each target cell partition netlist to check for timing violations based upon the timing modes.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: December 22, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Brian J. Mulvaney
  • Patent number: 9183033
    Abstract: According to one exemplary embodiment, a method for analyzing root causes applies an application-level dependency discovery and anomaly detection to find application-level dependencies in one or more virtual machines (VMs), and generate an application-level topology with anomaly, and then transfers the application-level topology with anomaly to a VM-level dependency, and transfers the VM-level dependency to a physical machine level (PM-level) dependency via a physical and virtual resource mapping, and eventually generates a group of event sets. A prioritized event list is generated by prioritizing the group of event sets.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 10, 2015
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: En-Tzu Wang, Tzi-Cker Chiueh, Je-Jone Ko, Shu-Chun Yeh
  • Patent number: 9146709
    Abstract: A system and method for detecting decomposition errors in a parallel processing software design having at least two decomposition levels, where each decomposition level has at least one process. The system and method further identifies improper control flow, looping structure and/or dataflow within the software design and restructures the software design to remove any improper elements.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: September 29, 2015
    Assignee: Massively Parallel Technologies, Inc.
    Inventor: Kevin D. Howard
  • Patent number: 9146902
    Abstract: In order to perform computation concerning a large sparse matrix of values, a computer stores in its memory the nonzero values of each row and as many null or preferably zero values as are required to make up a predetermined number of stored values for each row. Associated column indices are also stored. Storage in this format can be carried out by massively parallel processing using a graphics processing unit. The format is acceptable input for programs written to expect input in conventional compressed sparse row format yet avoids the constraints which enforce serial processing in order to store in that conventional format.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: September 29, 2015
    Inventor: Paul Frederick Cilgrim Dickenson
  • Patent number: 9141735
    Abstract: The present disclosure provides systems for predicting semiconductor reliability. In an embodiment a method for predicting the semiconductor reliability includes receiving a degradation parameter input of a semiconductor device and using a degradation equation to determine a plurality of bias dependent slope values for degradation over a short time period according to the degradation parameter input. The plurality of slope values include at least two different slope values for degradation over time. The system accumulates the plurality of slope values and projects the accumulated slope values over a long time period to determine a stress effect for the semiconductor device.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Lin Lo, Ke-Wei Su, Min-Chie Jeng, Feng-Ling Hsiao, Cheng Hsiao, Yi-Shun Huang, Yi-Chun Chen
  • Patent number: 9141979
    Abstract: Provided are methods of providing a virtual service that may provide partial real time service to clients of a production computing service that is unavailable. Methods may include generating, based on transaction data corresponding to a production computing service that is available, a production computing service model that includes multiple request types and multiple confidence values that correspond to ones of the request types. Methods may include responding to a request received from a client of the production computing service with a model-generated response to the request in response to the production computing service being unavailable. The production computing service is updated with the request received from the client and the model-generated response responsive to the production computing service being available after being unavailable.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: September 22, 2015
    Assignee: CA, Inc.
    Inventors: Victor Ooi, Steven Cornelis Versteeg, Robert Williams
  • Patent number: 9134979
    Abstract: A basic block within a thread program is characterized for convergence based on mapping the basic block to an indicator subnet within a corresponding Petri net generated to model the thread program. Each block within the thread program may be similarly characterized. Each corresponding Petri net is enumerated to generate a corresponding state space graph. If the state space graph includes an exit node with an odd execution count attribute, such as by Petri net coloring, then the corresponding basic block is divergent. The corresponding basic block is convergent otherwise. Using this characterization technique, a thread program compiler may advantageously identify all convergent blocks within a thread program and apply appropriate optimizations to the convergent blocks.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: September 15, 2015
    Assignee: NVIDIA Corporation
    Inventor: Manjunath Kudlur
  • Patent number: 9125067
    Abstract: A system and method for generating a calibration database in a communications network. A grid of geographic locations may be generated to cover a region in a communications network having a plurality of cellular sites. A set of network measurement reports (NMRs) is generated for the region, the NMR being a collection of measurement parameters observed at selected geographic locations in the grid. A label may then be generated representing a first measurement parameter observed from ones of the plural cellular sites at one of the selected geographic locations, the label including a relative ranking by cellular site of the first measurement parameter. Using this generated label, a calibration database for the communications network may be populated and locations of mobile devices determined therefrom.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: September 1, 2015
    Assignee: CommScope Technologies LLC
    Inventors: Martin Alles, Suryanarayana Kalenahalli
  • Patent number: 9107199
    Abstract: Provided is a method of transmitting a signal of a multi-node system employing a plurality of nodes and a plurality of base stations that can be controlled by being connected with the plurality of nodes. The method includes: mapping at least one base station among the plurality of base stations to at least one node among the plurality of nodes; and transmitting by the at least one base station a signal to a user equipment via the mapped node, wherein the plurality of nodes are installed in a geographically distributed manner, and the node mapped to the at least one base station varies temporally.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: August 11, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Ji Won Kang, Su Nam Kim, Bin Chul Ihm, Jin Young Chun, Sung Ho Park
  • Patent number: 9106550
    Abstract: Described is a system and method for determining a classification of an application that includes initiating a stress test on the application, the stress test including a predetermined number of stress events, wherein the stress events are based on a network impairment. A response by the application to each stress event is identified and the application is classified as a function of the response into one of a first classification and a second classification, the first classification indicative of a normal application and the second classification indicative of an undesired application. If, the application is in the second classification, a network response procedure is executed.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: August 11, 2015
    Assignee: AT&T Intellectual Property II, L.P.
    Inventors: Nicholas Geoffrey Duffield, Balachander Krishnamurthy
  • Patent number: 9098339
    Abstract: Embodiments related to predictive cloud-based presimulation are described herein. For example, one disclose embodiment provides, on a computing device, a method comprising receiving an input of state from a client device and executing a server simulation of a digital experience based on the input of state, the server simulation configured to run concurrently with, and ahead of, a client simulation on the client device. The method further comprises generating a plurality of simulation results from the server simulation, selecting one or more simulation results from the plurality of simulation results based on a likelihood the client simulation will utilize a particular simulation result, and sending the one or more simulation results to the client device.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: August 4, 2015
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Joel Pritchett
  • Patent number: 9087167
    Abstract: Aspects of the invention relate to techniques for predicting circuit performance variations due to device mismatch. Circuit simulation is performed to generate circuit simulation results based on a circuit description and information of circuit element parameters. Based on the simulation results, sensitivity information for the circuit design and current/charge deviations caused by individual circuit element parameter variations may be computed. Based on the sensitivity information and the current/charge deviations, steady-state mismatch effect information is determined. The determination may comprise first computing output parameter deviations caused by the individual variations of the circuit element parameters and then computing a total output parameter deviation based on the output parameter deviations.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: July 21, 2015
    Assignee: Mentor Graphics Corporation
    Inventor: Fabrice Alain Robert Veersé
  • Patent number: 9077643
    Abstract: Systems and methods are provided for programmatically simulating one or more system conditions for a network resource using one or more services. In one implementation, a server receives a request to initiate a treatment. The request identifies a treatment definition. The server determines, based on the treatment definition, the one or more services and deploys the one or more services to the network resource. The one or more services simulate the one or more system conditions.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: July 7, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Luis Felipe Cabrera, Peter N. De Santis
  • Patent number: 9053460
    Abstract: A Configuration Management DataBase (CMDB) is utilized when determining if resources, which are modeled in and managed by the CMDB, are in compliance with a new resource rule that affect how the resource operates. In one embodiment, the computer-implementable method includes the step of, in response to detecting a rule change, transmitting a new rule to a rule control logic in a resource management database, wherein the rule change changes a rule for an attribute of a resource in a data processing system, and wherein the resource management database describes attributes of resources in the data processing system.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Allen M. Gilbert, David L. Kaminsky, A. Steven Krantz
  • Patent number: 9047114
    Abstract: Methods and systems are provided for analyzing parallelism of program code. According to a method, the sequential execution of the program code is simulated so as to trace the execution procedure of the program code, and parallelism of the program code is analyzed based on the result of the trace to the execution procedure of the program code. Execution information of the program code is collected by simulating the sequential execution of the program code, and parallelism of the program code is analyzed based on the collected execution information, so as to allow programmers to perform parallel task partitioning of the program code with respect to a multi-core architecture more effectively, thus increasing the efficiency of parallel software development.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bo Feng, Rong Yan, Kun Wang, Hua Yong Wang
  • Publication number: 20150142409
    Abstract: In an approach for simulating a photographic setup, a computer receives information detailing a first type of device. The computer determines the received first type of device is not included in a device database. The computer inserts the first type of device into the device database. The computer receives a selection of one or more types of devices. The one or more selected types of devices are included in the device database and include the first type of device. The computer receives a configuration for each of the one or more selected types of devices. The computer creates a simulation of a photographic setup. The simulation is based on the one or more selected types of devices and the received configurations.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: International Business Machines Corporation
    Inventors: Michael C. Collins, John F. Kelley, Douglas E. Lhotka, Todd P. Seager
  • Patent number: 9037446
    Abstract: In a method for simulating temperature and electrical characteristics within an circuit, a temperature of at least one volume within the circuit as a function of a resistance within the at least one volume is repeatedly calculated and the resistance as a function of the temperature is repeatedly calculated until the temperature is within a predetermined tolerance of a previous temperature result and until the resistance is within a predetermined tolerance of a previous resistance result. Once the temperature is within a predetermined tolerance of the previous temperature result and the resistance is within a predetermined tolerance of the previous resistance, then an output indicative of the temperature is generated.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: May 19, 2015
    Assignee: Georgia Tech Research Corporation
    Inventors: Jianyong Xie, Madhavan Swaminathan
  • Publication number: 20150134317
    Abstract: Systems, methods, and software to facilitate simulating machines used in industrial automation are disclosed herein. In at least one implementation, an API is utilized to establish at least a communication link between a simulation model created in a simulation application and an industrial controller system outside of the simulation model, wherein the simulation model comprises definitions for a virtual representation of at least a portion of a machine used in an industrial automation environment. Data is then exchanged between the industrial controller system and the simulation model over the communication link.
    Type: Application
    Filed: June 10, 2014
    Publication date: May 14, 2015
    Inventors: Francisco Maturana, Haithem Mansouri, Jaroslav Kriz