Abstract: A computing device and a method for scattering parameter equivalent circuit reads a scattering parameter file from a storage device. A non-common-pole rational function of the scattering parameters in the scattering parameter file is created by applying a vector fitting algorithm to the scattering parameters. Passivity of the non-common-pole rational function is enforced if the non-common-pole rational function does not satisfy a determined passivity requirement.

Abstract: A method for simulating a response of a circuit to an ESD input stimulus applied to the circuit includes the steps of: receiving a description of the circuit into a circuit simulation program, the circuit including at least one mutual inductance element indicative of magnetic coupling in the circuit; generating a linear approximation of nonlinear elements in the circuit at respective DC bias points of the nonlinear elements; obtaining a frequency domain transfer function of the circuit; obtaining a time domain impulse response of the circuit as a function of the frequency domain transfer function; integrating the time domain impulse response to yield a step response of the circuit, the step response being indicative of a response of the circuit to the ESD input stimulus; and analyzing the step response of the circuit to determine whether the circuit will operate within prescribed parameters corresponding to the circuit.

Abstract: Systems and methods for segmenting an impedance matching model are described. One of the methods includes receiving the impedance matching model. The impedance matching model represents an impedance matching circuit, which is coupled to an RF generator via an RF cable and to a plasma chamber via an RF transmission line. The method further includes segmenting the impedance matching model into two or more modules of a first set. Each module includes a series circuit and a shunt circuit. The shunt circuit is coupled to the series circuit. The series circuit of the first module is coupled to a cable model and the series circuit of the second module is coupled to an RF transmission model. The series circuit and the shunt circuit of the first module are coupled to the series circuit of the second module. The shunt circuit of the second module is coupled to the RF transmission model.

Abstract: The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.

Abstract: A method for assembling an electrical circuit includes measuring actual values of components of a given type that are held in a stock, and storing the measured actual values in a computerized stock-record. An actual property of an electrical circuit under assembly is determined. Based on the determined actual property, and on a specified response of the circuit, a required value is calculated for a set of one or more of the components of the given type. Responsively to the calculated required value, the stock-record is searched, and a set of one or more of the components is selected from the stock and assembled into the circuit.

Abstract: A delay analysis device composed of a storage device and a data processing device analyzes a chip fabricating a semiconductor integrated circuit. Delay calculation is performed via an RC simulation with reference to a layout-implemented macro net list, macro layout data, and a cell timing library, thus producing macro delay information. An initial stage of a macro is annotated by the global clock path delay information including the edge information so as to produce a global clock delay-annotated macro net list, which is then converted into a macro delay-annotated net list. Based on the macro delay-annotated net list and timing constraint, the delay analysis device calculates delay times of signal paths and clock paths as well as clock skews with a high precision. It checks whether or not the relationship between the delay times of signal paths and clock paths meets the timing constraint, thus producing delay analysis information.

Abstract: A method for expressing a hierarchy of scalabilities in complex systems, including a discrete event simulation and an analytic model, for analysis and prediction of the performance of multi-chip, multi-core, multi-threaded computer processors is provided. Further provided is a capacity planning tool for migrating data center systems from a source configuration which may include source systems with multithreaded, multicore, multichip central processing units to a destination configuration which may include destination systems with multithreaded, multicore and multichip central processing units, wherein the destination systems may be different than the source systems. Apparatus and methods are taught for the assembling of and utilization of linear and exponential scalability factors in the capacity planning tool when a plurality of active processor threads populate processors with multiple chips, multiple cores per chip and multiple threads per core.

Abstract: An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for computations or can be used in the development of a model in a modeling environment. The algorithm and architecture resulting from the algorithm use the latency of the components that are used to process the associative operations. The algorithm minimizes the number of components necessary to produce an output of multi-argument associative operations and also can minimize the number of inputs each component receives.

Abstract: The disclosure provides leakage power recovery that considers side transition times of multi-input cells. In one embodiment, a leakage power recovery system is disclosed that includes: (1) a power recovery module that considers side transitions when making a first conditional replacement of a cell in a path of a circuit design with a lower leakage cell and estimates delays and slack of the at least one path of the circuit design, and (2) a speed recovery module that makes a second conditional replacement of a slower lower leakage cell of the path with a higher leakage cell when there is a timing violation with respect to the path, determines if any other cells of the at least one path has a slower input transition and makes a third conditional replacement of a driver thereof to a higher leakage cell when the driver is one of the slower lower leakage cells.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: A coupled analysis simulation apparatus includes a coupled analysis processing unit configured to perform coupled analysis by performing electromagnetic field analysis and circuit analysis in coordination with each other, the electromagnetic field analysis being performed on a space including conductive layers to which an electronic circuit module is connected, the circuit analysis being performed on the electronic circuit module; a first generating unit configured to generate a virtual conductive part in a section or a region including connection parts connecting the electronic circuit module with the conductive layers; and a second generating unit configured to generate virtual connection parts that virtually connect the virtual conductive part with the conductive layers at positions where the connection parts are connected to the conductive layers.

Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.

Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Abstract: A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.

Abstract: In one embodiment, a method is provided for processing a circuit design having first and second sets of ports configured to couple to respective first and second sets of ports of a device on a hardware platform. In a data-acquisition mode, the circuit design is simulated using a user-selectable plug-in that couples the ports of the circuit design to an interface circuit. During the simulation, the interface circuit communicates data between respective ports of the circuit design and ports of the device. In a deployment mode, the circuit design is implemented in the hardware platform, in which the first and second sets of ports of the circuit design are respectively coupled to the first and second sets of ports of the device.

Abstract: One or more embodiments provide a load balancing solution for improving the runtime performance of parallel HDL simulators. During compilation each process is analyzed to determine a simulation cost based on complexity of the HDL processes. During simulation, processes to be executed in the same simulation cycle are scheduled using the simulation costs computed at compile-time in order to reduce the delay incurred during simulation.

Abstract: Roughly described, a method for synthesizing a circuit design from a logic design includes developing candidate solutions for a particular signal path, a first candidate solution identifying a first library cells followed immediately downstream thereof by a first set of zero or more buffers, and a second candidate solution identifying a second library cell followed immediately downstream thereof by a second set of zero or more buffers, the first library cell and first set of buffers in combination being different from the second library cell and second set of buffers in combination. The computer system selects among the candidate solutions at least in part in dependence upon sensitivity of the solution to load capacitance in the particular path, and stores the selected solution in the storage for subsequent use in further developing and fabricating an integrated circuit device.

Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: In one embodiment of the invention, a method of simulating a circuit is disclosed including simulating an analog component of the circuit over a first simulation time period with a first envelope simulation; adaptively switching from simulating the analog component with the first envelope simulation to simulating the analog component with a transient simulation over a second simulation time period; and adaptively switching from simulating the analog component with the transient simulation to simulating the analog component with a second envelope simulation over a third simulation time period. The adaptive switching from the first envelope simulation to the transient simulation may be in response to the envelope simulation accuracy falling below a predetermined level of accuracy in comparison with a transient simulation or in response to the second simulation time period including expected digital transitions where one or more digital events may occur to change the analog input signals to the analog component.

Abstract: An image processing method includes the following steps. An input data including a number of original data are received. The original data are converted into a number of converted emulation voltage signals. At least a simulation circuit model including at least a spatial data node, at least a diffusion node and at least a connection device is established, wherein, the at least a connection device is coupled to a part or all of the at least a spatial data node and the at least a diffusion node. A part or all of the converted emulation voltage signals are supplied to the diffusion node to achieve voltage diffusion among the spatial data nodes and the diffusion nodes via the connection device, so that at least a diffused emulation voltage signal is obtained on the diffusion nodes. Then, processed image data are generated according to the diffused emulation voltage signals.

Abstract: When a wait statement is encountered in an HDL simulation, the simulation kernel executes functions corresponding to other processes while waiting for the wait to mature. However, the preservation of variables and states of each process and procedure in the call chain can be complex and inefficient. An embodiment of the present invention provides a method to suspend procedures in simulation of an HDL circuit design such that processes that call procedures containing wait statements are executed on a secondary runtime stack and can be suspended by saving the state of simulation and switching simulation execution to the primary runtime stack.

Abstract: A method for design simulation includes partitioning a verification task of a design into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device, which includes a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.

Abstract: Certain embodiments of the invention may include systems and methods for providing electrical fault restoration. According to an example embodiment of the invention, a method can include sectioning a de-energized region into two or more de-energized areas; simulating opening or closing of one or more circuit switches associated with the two or more de-energized areas; compiling a listing of simulated energized areas and simulated de-energized areas, based on the simulated opening or closing of the one or more circuit switches; evaluating the listing of simulated energized areas and simulated de-energized areas, based at least in part on one or more configurable strategy modules; and generating a restoration plan based at least in part on the evaluation.

Abstract: The disclosure relates to the analysis of compensated layout shapes. A method in accordance with an embodiment includes: analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device; and applying a pattern template to a content of the bucket structure to identify a shape adjacent to the semiconductor device; wherein the pattern template is derived from layout groundrules.

Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings.

Abstract: According to one embodiment, a simulation apparatus includes a hardware model execution unit that executes a hardware model, a software model execution unit that executes a software model, a simulation time management unit that sets a first simulation time indicating a total elapsed time of a simulation time of the hardware model, ahead by the simulation time of which the HW model notified, and sets the second simulation time indicating a total elapsed time of a simulation time of the software model, ahead by the simulation time of which the SW model notified, and a scheduler that compares the first simulation time with the second simulation time, causes the SW model or the HW model to be executed based on the comparison result, and causes only the hardware model to be executed instead of execution of an idle loop when the SW model awaits an interrupt from the HW model.

Abstract: Provided is a method of configuring a large signal model of an active device. The method may include configuring a large signal model of a first active device, preparing a first measured value on a first characteristic of a second active device, the second active device being larger than the first active device, processing the large signal model of the first active device using a circuit simulator to configure a large signal model of the second active device, simulating the large signal model of the second active device to obtain a calculated value on the first characteristic, comparing the measured and calculated values on the first characteristic to each other, and establishing the large signal model of the second active device, if a difference between the measured and calculated values on the first characteristic may be smaller than a predetermined error margin.

Abstract: A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model, and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter model or Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter model or Barycenter compact model.

Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.

Abstract: A computer-based method for marking signal transmission lines of a printed circuit board (PCB) layout includes: reading names of to-be-checked signal transmission lines in a name file; determining the to-be-checked signal transmission lines in a displayed PCB layout according to the read names; and marking the determined to-be-checked signal transmission lines in the displayed PCB layout. A related computing device is also provided.

Abstract: Described are apparatus and method for simulating spintronic integrated circuit (SPINIC), the method comprising: generating a spin netlist indicating connections of spin nodes of spin circuits and nodes of general circuits; and modifying a modified nodal analysis (MNA) matrix for general circuits to generate a spin MNA matrix for solving spin circuits and general circuits of the spin netlist.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract: A microcontroller having a computing unit and a logic circuit. The microcontroller carries out computations for a regulation or control in a vehicle. The computing unit is connected to the logic circuit, and the logic circuit has an arrangement for computing an exponential function and is configurable.

Abstract: A method and a system for determining the observability of faults in an electronic circuit include a processor that simulates, in a simulation phase, a behavior of the electronic circuit using a simulation model, and that determined, in an analysis phase, based on the simulation, and for each of a plurality of elements of the electronic circuit, time periods in which an occurrent fault could cause a deviation in analysis output signals, where the occurrent fault is determined not to cause any deviation in output signals in other time periods.

Abstract: An arithmetic device calculates the surface potential of a silicon layer by performing computation based on a mathematical expression and device parameters stored in a storage device. Likewise, the arithmetic device calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in a partially depleted state and when the silicon is in a fully depleted state. The arithmetic device then performs computation based on the calculated surface potential of the silicon layer, the calculated surface potential of the bulk layer, and mathematical expressions stored in the storage device, and obtains the surface potential of the bulk layer by iterative calculation. The arithmetic device performs computation based on the surface potential of the bulk layer obtained by iterative calculation and mathematical expressions stored in the storage device, and calculates the lower surface potential of the silicon layer.

Abstract: A critical path emulating apparatus includes a critical path emulator (CPE) and an interconnection circuit. The CPE is capable of emulating a critical path of a target device, and supporting a plurality of speed information detection modes. The interconnection circuit is capable of supporting a plurality of interconnection arrangements, wherein when the interconnection circuit is configured to have a first interconnection arrangement, the CPE is capable of being used in a first speed information detection mode, and when the interconnection circuit is configured to have a second interconnection arrangement, the CPE is capable of being used in a second speed information detection mode.

Abstract: Systems and methods are provided to optimize critical paths by modulating systemic process variations, such as regional timing variations in IC designs. A method includes determining a physical location of an element in the semiconductor chip design within the critical path. The method further includes modulating a systemic process variation of the semiconductor chip design to speed up the critical path based on a polysilicon conductor perimeter density associated with the element.

Abstract: Redundancy extraction in electromagnetic simulation of an electronic device/system includes discretizing first and second spaced conductive layers of a computer model of an electronic device/system into first and second meshes M1 and M2. For each edge between cells of each mesh, a current flow across the edge in response to application of an exemplary bias to the geometry is determined. A square impedance matrix Z* is determined which, for each instance of equal magnitude and opposite direction current flows (EMODCF) in edges E1 and E2 of M1 and M2, has one less row and one less column than the total number of edges in M1 and M2. A voltage column vector V* is also determined which, for each instance of EMODCF, has one less row than the total number of edges in M1 and M2. A current column vector [I*]=[V*]/[Z*] is then determined.

Abstract: Before supplying a series of instructions to a circuit simulator, methods and systems cache the series of instructions and partition the series of instructions into an active portion and an inactive portion. Instead of supplying the entire series of instructions to the circuit simulator, the methods and systems supply only the instructions directed to the active portion of the integrated circuit to the circuit simulator. Thus, the circuit simulator creates a reduced circuit simulation from just the instructions directed to the active portion (instead of a full integrated circuit that would have been simulated with the entire series of instructions). The reduced circuit simulated by these systems and methods has less circuit elements relative to any integrated circuit that would have been simulated with the entire series of instructions. Thus, this reduced circuit is only a portion of the integrated circuit that would have been simulated.

Abstract: A simulation method to cause an information processing device to calculate, including: reversely tracing a first flux incident on any position on a surface of a workpiece subject to processing treatment from the position; when the first flux strikes another position on the workpiece surface as a result of the reverse tracing of the first flux, calculating a second flux to be the first flux by scattering at the another position and reversely tracing the second flux from the another position; and, by repeating calculation and reverse tracing of flux, when the reversely traced flux no longer strikes the workpiece surface, carrying out comparison of the flux with an angular distribution of a flux incident on the workpiece, and when the current flux is within the angular distribution, obtaining an amount of flux having contributed to the scattering for a flux group from the first flux to the current flux.

Abstract: Provided is a circuit simulation model that can suitably represent capacitor characteristics, thereby realizing accurate circuit design and circuit analysis. A SPICE model is constituted of a capacitor unit in which a capacitor is replaced with a linear voltage dependent current source, a low-pass filter unit that has a function of extracting a DC bias voltage, a calculation circuit unit that is configured by combining an adder, a multiplier, and the like to perform a calculation of a circuit equation derived from an equivalent circuit for a capacitor such as an idealized C circuit model, an RC circuit model, or the like, and a linear voltage dependent voltage source that applies a total voltage applied across the capacitor to the calculation circuit.

Abstract: An apparatus and method for performing periodic noise (Pnoise) simulation with full spectrum accuracy is disclosed herein. Noise contributions of a circuit under consideration are identified and separated for different computation treatment. The different computation treatment results in computational efficiency without sacrificing accuracy of simulation results.

Abstract: The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S2). The voltage fluctuation analysis step at the gate level is executed on an entire chip TP. Next, a step of obtaining waveforms of power supply voltage and ground voltage (Vss) according to the voltage fluctuation analysis step is executed (step S4). Subsequently, a signal analysis step at a transistor level is performed (step S6). The signal analysis step at the transistor level is performed in an area narrower than the entire chip TP, for example, on one or more functional modules. After that, a step of obtaining a signal analysis result according to the signal analysis step is executed (step S8).

Abstract: A method of generating an ion implantation distribution by a computer is disclosed. The method includes calculating ion implantation distribution regions in a case of generating the ion implantation distribution with a large tilt angle and generating an analytical model of the ion implantation distribution in correspondence with each of the ion implantation distribution regions by using a Gauss distribution model, in which the ion implantation distribution regions have different influence on a channel region depending on a gate structure formed on the ion distribution regions.

Abstract: In a particular embodiment, a first digital function module is created that represents a first analog circuit and a second digital function module is created that represents a second analog circuit. A first value representing a first analog signal is transmitted from the first digital function module to the second digital function module while concurrently or substantially currently, the second digital function module transmits a second value representing a second analog signal to the first digital function module. In a particular embodiment, the first digital function module is a current signal related to an output of the first analog circuit and the second analog signal from the second digital function module is a voltage signal related to an output of the second analog circuit. The values may be transmitted along a bidirectional analog data bus capable of communicating real floating point numbers.

Abstract: There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a plurality of pieces of cycle-based mapping information (21) for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit (10) and configuration selection information (22) for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus (1) includes a control unit (11) that reconfigures at least part of the logic region (10) using at least one of the plurality of pieces of cycle-based mapping information (21) according to a request in each cycle based on the configuration selection information (22).

Abstract: A parameter correction method includes: obtaining, from a variability-aware simulation, a simulation result value of a predetermined product performance for a reference candidate value set concerning statistics of predetermined product characteristics; calculating a likelihood by substituting the reference candidate value set, the obtained simulation result value, statistics of measurement values of the predetermined product characteristics and a measurement value of the predetermined product performance into a likelihood function that is defined from a probability density function for the statistics of the predetermined product characteristics and a probability density function for the predetermined product performance, and is a function to calculate a combined likelihood of the statistics of the predetermined product characteristics and the predetermined product performance; and searching for a reference candidate value set in case where the calculated likelihood becomes maximum, by carrying out the obtaini