Abstract: Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signal propagation delay is dominated more by an interconnect capacitance term or by an interconnect capacitance and resistance product term. If it is dominated more by the interconnect capacitance term, then the parameter values used for a minimum propagation delay calculation are obtained assuming a smallest capacitance process variation case and the parameter values used for a maximum propagation delay calculation are obtained assuming a largest capacitance process variation case. If the signal propagation delay is dominated more by the interconnect capacitance and resistance product term, then the opposite assumptions are made. Preferably the approximate determination is made by comparing Rint to k*Rd.

Abstract: A method and apparatus for designing a processor-based emulation integrated circuit (chip) having a selectable fastpath topology. Included are initially designing an N-level fastpath topology comprising a plurality of processors, then reducing the N-level fastpath topology to an M-level topology such that the performance of the topology meets a design criterion, e.g., capable of evaluating data during a time of an emulation step. In this manner, an emulator chip designer may configure the fastpath topologies without redesigning the chip layout.

Abstract: A processor-based emulation system for emulating an integrated circuit design, the processor-based emulation system including emulation circuitry and capture circuitry. The capture circuitry is operable to capture processing results from the emulation circuitry. The captured processing results can be used to identify functional errors in the integrated circuit design. Because the processor-based emulation system includes capture circuitry, emulation circuitry is not used for capturing the processing results.

Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.

Abstract: There is disclosed a simulation model and method for designing a semiconductor device being used for a simulation apparatus for designing a semiconductor device that includes using assuming units as to carrier transient density and current flow of electrodes along with a non-quasi-static model describing unit of the simulation apparatus. A simulation apparatus and computer readable medium with a simulation program for executing the method are also included.

Abstract: A method of semi-automatic data collection, data analysis and model generation for performance analysis of computer networks and software is provided. The invention provides a graphical user interface which indicates the overall data flow in the performance analysis process and guides the user through the proper sequence of steps in that process. Underneath the graphical user interface, the invention provides software tools which include novel data pipeline for transformation of network traces, resource data and application data into organized hash tables, and further into spreadsheets for introduction into computer network simulation programs. The invention also provides novel algorithms for recognizing transaction and parentage between transactions from low level network trace data. The invention further provides novel methods of visualization of trace data and transaction and parentage associations.

Abstract: A method of simulating a restorable register in a power domain of an RTL (register transfer level) design includes: specifying the power domain in the RTL design, wherein the power domain includes one or more registers and is configured to change power levels separately from other portions of the RTL design; identifying the restorable register in the power domain, wherein the restorable register is updated during power-on operations in the power domain; simulating the restorable register in a power cycle; and saving one or more values from the simulated restorable register. Simulating the restorable register includes: maintaining one or more backup values during a power-off operation for updating the restorable register after the power-off operation; and updating the restorable register during a power-on operation after the power-off operation by using the one or more backup values.

Abstract: A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

Abstract: A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.

Abstract: An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete.

Abstract: A control system, a safety system, etc., within a process plant may each use one or more state machine function blocks that can be easily integrated into a function block diagram programming environment. Such a state machine function block may include one or more inputs, which may cause a state machine implemented by the state machine function block to change states. The state machine function block may determine a next state to which it is to transition based, at least in part, on data indicative of the next state to which to transition, if any. The configuration data may be retrieved from a database based on the current state of the state machine and at least one of the inputs. The state machine function block may also include one or more outputs that are generated based on the state of the state machine.

Abstract: Methods, media, and means for forming asynchronous logic networks are provided. In some embodiments, methods for forming an asynchronous logic network are provided. The methods include: receiving a logic network including vertices and signals, wherein the vertices include vertices with multiple output signals; determining a set of signals of the signals included in the logic network to be covered; selecting at least one vertex in the logic network to cover each signal in the set of signals; replacing the at least one selected vertex with a robust vertex; and replacing at least one non-selected vertex with a relaxed vertex.

Abstract: It is determined whether an i-th instruction is for a memory access. If the i-th instruction is the memory access, it is determined whether an address to access according to the i-th instruction coincides with an address that has been accessed by a first execution block. If the addresses coincide with each other, it is determined whether a cycle of a second execution block currently executing precedes that of the first execution block. If the cycle of the second execution block precedes that of the first executing block, a memory model is accessed. A necessary number of cycles for execution of a j-th instruction is added to the current number of cycles, and the address, a cycle, data, and a data size at the time of the current access (before re-writing) are written in a delay table.

Abstract: A method for testing a variable capacitance measurement system including a fixed voltage source, a variable capacitance sensor, and a circuit to process information output by this sensor. The method connects an electrically controllable electronic simulation device to replace the variable capacitance sensor, models the electrophysical behaviour of the sensor, and tests the system.

Abstract: Methods and apparatus are provided for efficiently generating test components for testing and evaluating a design under test. As a design is being configured, generated test components are made available. In one example, test components are automatically generated and included in a simulation testbench based on selected components in the design. Generally, the test components complement the selected components in the design. Moreover, the test components can be automatically seeded with initial contents.

Abstract: A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin information for the module. Sensitivities of performance on yield to the variables in the subset combinations are determined. It is then determined whether yield of the target module is acceptable, and if the yield is not acceptable, a design which includes the target module is adjusted in accordance with the sensitivities to adjust the yield.

Abstract: A leakage current distribution verification support method includes a process including obtaining the estimated number L of cells in the custom macro circuit and the first arithmetic expression including a polynomial with a term having a common parameter ? representing variations arising from each cell in the custom macro circuit and with a term having a parameter ? representing variations arising from the entirety of the custom macro circuit, generating a second arithmetic expression including a polynomial with a term having a parameter ?n (n=1, 2, . . . , L) and a term having the parameter ?, setting coefficients in the polynomial included in the second arithmetic expression in such a manner that a result of calculation of the second arithmetic expression becomes equal to a result of calculation of the first arithmetic expression, and outputting the second arithmetic expression in which the coefficients have been set.

Abstract: Techniques are presented for a multi-tier distributed frame work for mass configuration of products by design and synthesis. Products are represented as components having hierarchical relationships with one another. The components include form information, function information, behavioral information, and constraint information. Components may be created from scratch or retrieved from a plurality of sources over a network. In some embodiments, the components may include optimization constraints and derived from other components to meet the optimization constraints.

Abstract: A method and system are described that allow conversion of a three-dimensional representation of a wire harness to a two-dimensional representation. In one aspect, the three-dimensional representation of the wire harness is converted to a two-dimensional orthogonal representation with branches in the wire harness arranged perpendicularly. In another aspect, when more than four branches enter a single node in the wire harness, one or more of the branches are placed within a predetermined angle to the perpendicular lines. The orthogonal representation allows simplified detection of disconnects in the wire harness that are otherwise difficult to visualize in three dimensions.

Abstract: A model parameter extracting apparatus includes: a binning processor for carrying out a binning process; and a model parameter extractor for extracting a model parameter for each of multiple bins formed by the binning process. The model parameter extractor extracts a first model parameter corresponding to a first end portion of a target bin. Based on the first model parameter, the model parameter extractor sets up a candidate for a second model parameter corresponding to a second end portion of the target bin. Subsequently, based on the first model parameter and the candidate for the second model parameter, the model parameter extractor finds a start-point-side gradient and an end-point-side gradient of a limited curve representing an electric characteristic of a semiconductor device. Then, based on a result of a comparison between the gradients, the model parameter extractor extracts the second model parameter.

Abstract: An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete.

Abstract: A method of preparing a circuit simulator, said method comprising initializing a normalized adjusted gate voltage value. Then performing the steps of determining a normalized adjusted gate voltage datum in dependence upon the initial normalized adjusted gate voltage value. Storing the normalized adjusted gate voltage datum at a memory address in a one-dimensional array based on the normalized adjusted gate voltage. Decrementing the normalized adjusted gate voltage value by a predetermined decrement amount. And verifying the decremented gate voltage value. Then repeating until a stop gate voltage value is reached.

Abstract: Methods for generating realistic waveforms with controllable voltage noise and timing jitter in a computer-based simulation environment and the simulation of a subset of those waveforms with system elements along the signal path is disclosed. By deriving a generic, re-useable, parameterized Fourier series, time-domain clock and pseudo-random data signals are generated from a subset of their true harmonic components. Time-domain signal parameters including high, low, and common-mode voltage levels, transition slew-rates, transition timing, period and/or frequency, may be designated by the user, and the computer calculates the harmonic components that will combine through the inverse Fourier transform to provide the required time-domain characteristics. By computing the frequency content of the signal directly it is possible to simulate the interaction of the signal with various system blocks while remaining in the frequency domain, thereby reducing simulation time and memory requirements.

Abstract: For the purpose of providing a simulation model allowing gate simulation but is capable of keeping the circuit information on the functional block (IP) secret, a method of generating a simulation model provided herein by the present invention comprises a step of generating a net list containing circuit information of an electronic circuit using a functional block; and a step of deleting the circuit information based on the net list, and generating a gate simulation model carrying out a timing simulation, including logic information and delay information between input/output of the functional block.

Abstract: There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies. The second process uses result data saved by the first process to reproduce internal node data not saved by the first process. Result data for the interface node between hierarchies indirectly determines a value for the internal node. Result data to be saved is data concerning the interface node between hierarchies. The amount of saved data and the time needed for the second process are independent of a hierarchical level or a higher-level or lower-level hierarchy.

Abstract: A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.

Abstract: A simulation environment is disclosed wherein both analog and RF signals are simulated in a single flow by a mixed-domain simulator. The simulator includes a simulator kernel with an analog solver and an RF solver to allow both analog- and RF-type of signals to be solved in an interrelated fashion. The simulator may also include a partitioner that divides the circuit into various RF and analog modules to be solved. User input may control the partitioning process, but the simulator may refine the partitions or generate sub-partitions to provide a higher probability of convergence.

Abstract: The present invention provides a delay analysis system which makes it possible to make delay analysis considering circuit logical information in order to give more accurate delay times. In addition to circuit connection information and delay time information on the rises and falls of the input and output terminals of the circuits which are stored in a delay analysis library, the delay analysis system according to the present invention contains, in the library, logical operation information which represents correspondence between the logical values of each input terminal and their output logical values of the circuits.

Abstract: An LSI (Large-Scale Integrated) circuit system capable of preventing antenna damage occurring in MOS (Metal Oxide Semiconductor) transistors due to an erroneous operation of a wiring formed during manufacturing processes of LSIs or like as an antenna. Layout data after installation of wirings is read by layout reading processing and up-sizing candidate table is created by sizing candidate table creating processing using various libraries so that candidate values are arranged for every function cell in ascending order of gate areas. By antenna error net detecting processing, a net having wiring layers causing an antenna error is detected. A gate pin, its instance, type of a cell connected to the net is recognized by gate pin/cell recognizing processing and a cell enabling prevention of an antenna error is up-sized by cell sizing processing by referring to a gate area stored in an up-sizing candidate table.

Abstract: Method and apparatus for simulating electrical pipe-to-soil impedance of a coated segment of a pipeline includes simulating a current injection point to a buried pipe section, simulating a first output signal from a magnetometer positioned at a first location over the buried pipe section, simulating a second output signal from a magnetometer positioned at a second location over the buried pipe section, simulating bonding of pipe coating of the pipe section, and simulating soil resistance of a soil environment surrounding the buried pipe section. The invention includes both field-test simulation with calibration pipe samples, and bench-test simulation using electronic simulation of the pipe coating. The simulations may be used for test and general calibration of MEIS pipeline coating inspection systems.

Abstract: Method and apparatus for designing an integrated circuit by providing an IC layout design. Adding one or more assist features to the IC layout design. Identifying which of the one or more added assist features in the IC layout design will cause one or more defects in the resultant wafer die manufactured from the IC layout design. Amending the one or more identified assist features.

Abstract: An integrated circuit verification device includes a trace-back unit having structure data of an integrated circuit to be verified, and configured to trace back nodes of the integrated circuit in a direction from an output node to an input node; and a state defining unit having data with respect to a target state of the output node of the integrated circuit, and configured to sequentially define states of back-traced nodes to satisfy the target state of the output node.

Abstract: A system and method for deriving semiconductor manufacturing process corners using surrogate simulations is disclosed. The method may be used to determine individual performance metric yields, the number of out-of-specification conditions for a given number of simulation samples, and a total yield prediction for simultaneous multi-variable conditions. A surrogate simulation model, such as a Response Surface Model, may be generated from circuit simulation data or parametric data measurements and may be executed using a large number of multi-variable sample points to determine process corners defining yield limits for a device. The model may also be used to simulate process shifts and exaggerated input ranges for critical device parameters. In some embodiments, the derived process corners may better represent physically possible worst-case process corners than traditional general-purpose process corners, and may address differences in process sensitivities for individual circuits of the device.

Abstract: The present invention utilizes clock bursting to minimize command latency in a logic simulation hardware emulator/accelerator. The emulator/accelerator includes an emulator system having logic gate functions representing a design under test. The logic gate functions further include special burst clock logic for toggling a clock signal to a plurality of latches within the design under test for a predefined number of clock cycles. A host workstation, coupled to the emulator system by a high-speed cable, provides control for the emulator system. In normal operation, the host workstation encodes a predefined number of clock cycles for the emulator to run, then transmits the encoded number of cycles to the burst clock logic via the high-speed cable. The host workstation then generates a trigger signal within the high-speed cable, which directs the burst clock logic to read and decode the predefined number of cycles and begin toggling the clock signal.

Abstract: A method for clock modeling in a simulation tool is described. An internal time (I) may be defined that governs the simulator tool's clock period. An external time (E) may be defined. The internal time may have a smaller resolution than the external time. A calibration period (C) may be defined for the clock. The calibration period may be smaller than 0.5E and greater than I. The largest inaccuracy of any clock edge may be monitored, and the clock may be calibrated if the largest inaccuracy is greater than (C?1).

Abstract: An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.

Abstract: A unified simulation system is provided. The unified simulation system includes an input database storing input data comprising an input parameter and environment information, a unified simulator executing a unified process-device-circuit simulation of characteristics of a semiconductor apparatus based on the input data and at least one predetermined model and outputting a simulation result as output data, and an output database storing the output data. The unified simulator includes a process simulator simulating at least one process based on the input data and outputting process characteristic data, a device simulator simulating at least one device based on the process characteristic data and outputting device characteristic data, and a circuit simulator simulating a circuit comprising the at least one device. Accordingly, multiple devices can be simultaneously optimized for the optimization of circuit characteristics and an accurate specification at process and device levels can be provided.

Abstract: According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of the multiple signals are then included within a presentation of simulation results.

Abstract: A method and apparatus are provided to allow co-verification of hardware and software elements asynchronously from a programmable logic device (PLD).

Abstract: A method of synthesis of a model representing a design of an integrated circuit is provided including associating a test environment with a first model representing a design of an integrated circuit; translating the first model of the design to a second model of the design; and automatically generating an adaptor that adapts the second model to the test environment.

Abstract: A method and system comprises extracting resources required to run a discrete test case or set of associated test cases on a design. The method and system further includes building a simulation model based on the extracted resources and executing the simulation model using only the extracted resources, exclusive of an entire design, to test a specific function or group of interrelated functions represented by the discrete test case or set of associated test cases for design verification, and correlating the simulation results with the test plan.

Abstract: A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then simulates shutdown conditions to ensure the correctness of the generated isolation logic module. The isolation logic is generated based on user-defined voltage constraints.

Abstract: A method for generating model files of target devices of an integrated circuit includes providing the target devices; providing a device target set for the target devices, wherein the device target set comprises target values of parameters of the target devices; determining a nearest known model related to the target devices, wherein the nearest known model comprises a first model file; performing a sensitivity analysis to determine sensitive parameters in the first model file; modifying the sensitive parameters in the first model file to generate a second model file; and determining a fitness value of a circuit simulated using the second model file with values of parameters in the device target set.

Abstract: In a fast simulation technique, the output node of a power supply module of the integrated circuit can be designated as an ideal power node. At this point, the power supply module can be designated a fan-in block and any blocks connected to the power node can be designated fan-out blocks. Then, DC initialization and transient simulation for each time step can be performed for the circuit. During the transient simulation, any inter-relationship of the fan-out blocks can be determined and a sensitivity model can be calculated for each fan-out block. Because the power node is designated as an ideal power node, the results of the sensitivity model for each fan-out block can be added asynchronously to a total loadings of the power node. The total loadings can be loaded into a matrix, which is computed for the fan-in block, and a simulation waveform point can be output.

Abstract: A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Path Smoothing utility identifies one or more movable gates based on at least one selection criteria. A set of legalized candidate locations corresponding to one or more identified movable gates is generated. A disjunctive timing graph based on the generated set of legalized candidate locations is then generated. An optimal location of one or more movable gate(s) is determined using a recursive branch-and-bound search and stored in the computing device.

Abstract: A circuit analysis portion obtains an output characteristic of each of first noise source candidates. A noise evaluate portion obtains intensity of a noise crosstalking from each of the first noise source candidates to a low noise-tolerance terminal based on a second transfer function and the output characteristic of each of the first noise source candidates. Further, the first noise source candidates having the intensity of at least a prescribed value are set as second noise source candidates that are highly possibly the noise source. The analysis portion sets a noise source equivalent circuit to each of the second noise source candidates, and performs a second electromagnetic field analysis of the circuit substrate. The analysis portion sequentially repeats the second electromagnetic field analysis to every second noise source candidate. Thus, the route of the crosstalking noise can efficiently be analyzed.

Abstract: A system and method of generating a set of circuit simulation data, applying data mining to for knowledge extraction from the data, and graphically presenting the extracted knowledge in a format that is easy to digest to a designer.

Abstract: The present invention detects the occurrence of a bottleneck on the basis of the states of respective elements of the storage system and presents a measure for eliminating the bottleneck before actually changing the constitution of the storage system. The host element N1 is connected to the element N10 in the storage device via the elements N3, N6 and N8 (S1). Element N1 is a device file or the like, for example. Element N10 is a logical volume or the like, for example. When a bottleneck occurs in the intermediate element N8 (S2), the bottleneck is detected (S4) on the basis of collected information on the respective elements of the storage system (S3). A measure that is effective in eliminating the bottleneck is then reviewed and selected (S5, S6). This measure manipulates any of the elements N1 and N2 or N9 and N10 located at the two ends of the path.

Abstract: A system and method for binding a GUI element to a data source of live measurement data are described. A data source component may be included in a program and may be configured with a binding to a data source of live measurement data in response to user input. A GUI element may also be included in the program, and the binding configured for the data source component may be associated with the GUI element in response to user input. Associating the binding with the GUI element may effectively bind the GUI element to the data source of live measurement data and may enable the GUI element to automatically display the live measurement data from the data source during execution of the program. A system and method for binding a GUI element in a program to a data target for live measurement data are also described. A GUI element may be included in a program, and the GUI element may be configured to display live measurement data during execution of the program.

Abstract: Disclosed are apparatus, methods and software that implement a partial element equivalent circuit (PEEC) method having global basis functions on cylindrical coordinates to determine wide-band resistance, inductance, capacitance, and conductance from a large number of three-dimensional interconnections in order to provide for the electrical design of system-in-package (SIP) modules, and the like. The apparatus, methods and software use a modal equivalent network from mixed potential integral equation with cylindrical conduction and accumulation mode basis functions, which reduces the matrix size for large three-dimensional interconnection problems. Combined with these modal basis functions, the mixed potential integral equations describe arbitrary skin and proximity effects, and allow determination of partial impedance and admittance values. Additional enhancement schemes further reduces the cost for computing the partial inductances.