Abstract: An apparatus and methods for the verification of digital design descriptions are provided. In an exemplary embodiment, a method of verifying a property in a digital design description is provided. The method includes deriving an abstraction of the digital design description, determining a counterexample by an approximate reachable state computation, justifying the counterexample, determining a justification frontier, updating the abstraction from the justification frontier, and producing a verification result for the digital design description. One feature of this embodiment is that it provides for efficient digital circuit verification. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: A methodology for combining two or more S-parameter blocks/matrices (each representing a circuit or network, or the interconnection between a circuit or network) into a single S-matrix are described. Such a matrix may be beneficially used to simulate the circuit or network represented by the multiply interconnected circuits or networks.

Abstract: Disclosed herein are computer aided design (CAD) techniques to implement a unified data schema and graphical user interface (GUI) to link ECU/devices, in-vehicle communications, and vehicle harness information together with respect to architectural relation, performance relation, and cost relation, and to facilitate a designer's understanding and manipulation of this information. The domain-specific information from each domain is converted to objects in this unified data schema and stored in a unified database that is accessible to every domain, so that the impact of the current state in the device domain can be accessed and analyzed by a designer from any domain. This approach enables design data sharing and real-time collaboration between different electrical/electronic (E/E) design domains, thereby facilitating the realization of design data collaboration, design change management, and product lifetime management (PLM) and product data management (PDM) implementation.

Abstract: A method for adjusting a data set defining a set of process runs, each process run having a set of data corresponding to a set of variables for a wafer processing operation is provided. A model derived from a data set is received. A new data set corresponding to one process run is received. The new data set is projected to the model. An outlier data point produced as a result of the projecting is identified. A variable corresponding to the one outlier data point is identified, the identified variable exhibiting a high contribution. A value for the variable from the new data set is identified. Whether the value for the variable is unimportant is determined. A normalized matrix of data is created, using random data and the variable that was determined to be unimportant from each of the new data set and the data set. The data set is updated with the normalized matrix of data.

Abstract: A method is provided to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising: obtaining a value for each cell of the plurality that is indicative of both the cell's power dissipation and the cell's rate of output voltage change; ordering the cells of the plurality based upon the values; identifying a difference between values of cells that are proximate each other within the ordering of the cells that meets a threshold; and designating a cut point within the ordering of the cells based upon the identified difference.

Abstract: Analog and radio frequency system-level simulation using frequency relaxation. Embodiments of the invention use a frequency relaxation approach for analog/RF system-level simulation that accommodates both large system size and complex signal space. The simulator can determine an output response for a system by partitioning the system into blocks and simulating the propagation of an input signal through the blocks. The input signal can take various forms, including a multi-tone sinusoidal signal, a continuous spectra signal, and/or a stochastic signal. Frequency relaxation is applied to produce individual responses. The output response can be computed based on obtaining convergence of the individual responses. The input to embodiments of the simulator can be a circuit netlist, or a block-level macromodel.

Abstract: A method of simulating device mismatch effects on transient circuit behaviors utilizes a circuit model corresponding to an electronic circuit. The circuit model includes a plurality of circuit elements and one or more noise sources. The noise sources have noise characteristics that correspond to device mismatch effects associated with the circuit elements. A noise analysis is performed on the circuit model to generate a noisy steady-state waveform of a selected output of the electronic circuit. Then, the noisy steady-state waveform is translated into a prediction of the variation of a respective circuit parameter associated with the electronic circuit.

Abstract: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.

Abstract: The present method is a method of modeling Drain-Induced Barrier Lowering (DIBL) in a transistor model, the transistor model being based on a MOSFET transistor. The transistor model includes a base, a source, a drain, a gate, and a gate terminal. In the present method, a voltage is applied to the gate terminal, a voltage is applied to the drain, and an electrical potential is applied between the gate terminal and gate. The magnitude of electrical potential applied between the gate terminal and gate is varied in proportion to the magnitude of voltage applied to the drain.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Abstract: A method and apparatus are provided to model, analyze, and build linear time invariant systems with delays. The method and apparatus model a linear time invariant system as a linear fractional transformation of matrices of a delay free linear time invariant model with a bank of pure delays. The method and apparatus of the present invention can further accommodate input delays and output delays associated with the linear time invariant system with delays.

Abstract: Disclosed is a method for detecting properties of a Metal Oxide Silicon (MOS) varactor, which includes: establishing a MOS varactor model equation in conjunction with an area of a gate; calculating values of the coefficients of the MOS varactor model equation through measurements for test materials; and extracting the properties of a capacitor of the MOS varactor using the calculated values of the coefficients. According to the method, the MOS varactor model equation can be expressed by Cgate=[Cigate×Area+Cpgate×Perimeter]×N, wherein, Cgate denotes gate capacitance for voltage applied to the gate, Cigate denotes intrinsic gate capacitance, Cpgate denotes perimeter gate capacitance, and N denotes the number of gate fingers. The MOS varactor model equation can be applicable to various sized capacitors, so that it is possible to estimate a gate capacitance for voltage applied to a gate, considering the differences due to the surface shapes of a device.

Abstract: Data structures and algorithms are provided to automatically generate an analog stimulus to apply to a simulation of the analog DUT. A constraint solver is provided to determine suitable values to use in the stimulus generation. The suitable values are random values within a range of allowed values. For example, a number of different stimuli are generated for successive application to the analog DUT, each with a different magnitude within a range of allowed magnitudes. Data structures and algorithms are provided to monitor analog electrical properties at nodes of the analog DUT. Data structures and algorithms are provided to define constraints on the analog electrical properties and determine whether the constraints were violated. Data structures and algorithms are provided to define simulation coverage conditions in the analog domain and determine whether the defined analog domain coverage conditions have been satisfied.

Abstract: A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function.

Abstract: A method for generating test cases for software and a test case generator comprising a simulator that drives software under test from one input state to the next. The simulator is constrained by predetermined criteria to visit states that meet the criteria thus preserving computer resources. The states reached by the simulator are tested.

Abstract: The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.

Abstract: An electromagnetic field analysis apparatus includes an information input device configured to input information as to wirings and components of an analysis object and a modeling device configured to generate a simulation model of the analysis object based on the inputted information as to wirings and components of the analysis object. A model simplification device simplifies the simulation model into a simplified simulation model by dividing the analysis object according to the simulation model into a plurality of cells and thinning out, when a plurality of elements are included in a cell, the plurality of elements.

Abstract: A method for simulating an electric circuit comprising components and receiving external stimuli, wherein the determination at a given time of the voltages at the circuit nodes comprises several iterations, each consisting of defining a probable voltage for each node, of calculating the currents of each component based on the component model, then of repeating until the mesh equation is verified, and wherein for the first time, a current of a component is calculated based either on the full accurate model, or on the simplified linear model, or on the compound model which is a fitting, according to the interval between the voltages at the component's terminals between the initial time and the first time, and the simplified, full or compound model is used respectively if the interval is smaller than a first threshold, greater than a second threshold or between the first and second thresholds.

Abstract: An apparatus for estimating a change amount in a register transfer level structure includes: a correspondence relationship creating unit which describes a correspondence relationship among a behavioral description, a control data flow graph, and a register transfer level structure of a register transfer level description created by performing high-level synthesis on the behavioral description, based on the behavioral description which is input, the control data flow graph which is input and created by performing high-level synthesis on the behavioral description, and binding information which is input and created by performing high-level synthesis on the behavioral description; and a register transfer level change amount estimating unit which estimates and outputs a change amount in the register transfer level structure, the change amount in the register transfer level structure being necessary to change the register transfer level description to a description equivalent to a partially changed behavioral desc

Abstract: A settings emulator for a circuit breaker trip unit includes a handheld enclosure and a plurality of adjustable rotary switches mounted on the handheld enclosure. The adjustable rotary switches define a plurality of different trip settings for the circuit breaker trip unit. A communication channel is also mounted on the handheld enclosure. A microprocessor is enclosed by the handheld enclosure. The processor reads the different trip settings from the adjustable rotary switches and communicates the different trip settings through the communication channel to the circuit breaker trip unit.

Abstract: A logic simulation method includes causing a physical specification detector to detect physical specifications of an analog circuit (a PLL circuit and a DLL circuit) as a verification object described in a logic library; causing a monitor to monitor whether a signal or setting during a logic simulation satisfies the physical specifications; and causing a warning section to issue a warning when the signal or the setting fails to satisfy the physical specifications.

Abstract: A mask inspection system 10 inspects an inspection object pattern while comparing an inspection object data obtained in such a way as to image the inspection object pattern with a reference pattern data. The mask inspection system 10 is provided with an inspection information preparing part 12 producing inspection algorithm and inspection sensitivity to the reference pattern data based on wafer simulation, a converting part 13 generating a reference graphic data with inspection information while adding the inspection information to the reference graphic data, and a defect judging part 16 judges propriety of an inspection object pattern data while comparing reference graphic data with an inspection object data in every pixel based on the inspection information added to the reference graphic data with inspection information.

Abstract: The embodiments of the present invention provide methods for choosing a via layout pattern(s) for power distribution network in a package for a semiconductor die. The chosen via layout pattern allows the power distribution network to meet the limitation on the loop inductance in order to avoid causing a large ?V affecting the functionality of semiconductor devices on the die. In addition, the chosen via layout pattern also meets the limitation of total number of vias allowed for the power distribution network in the package.

Abstract: A method, system and program product are disclosed for statistical modeling an integrated circuit that provides information about partial correlations between model parameters. The invention determines a variance-covariance matrix for data to be modeled; conducts principal component analysis on the variance-covariance matrix; and creates a statistical model with an independent distribution for each principal component, allowing calculation of each individual model parameter as a weighted sum by a circuit simulator. The statistical model provides information about how well individual transistors will track one another based on layout similarity. This allows the designer to quantify and take advantage of design practices that make all transistors similar, for example, by orienting all gates in the same direction. A method, system and program product for simulating a circuit using the statistical model are also included.

Abstract: A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.

Abstract: A pin-based memory power modeling method using arc-based characterization includes steps as follows. All power arcs of a memory model are identified and characterized. A power arc is selected from the identified and characterized power arcs. Output bus switching power is computed by removing overlapping power using the selected power arc, and a temporary value for various input ramp times and output loads is derived. Output pin power for the selected power arc is calculated using the temporary value and a ratio of a number of output bits switching over an entire bus width. Switching power for the selected power arc is calculated by a power estimation tool based on port activity and an input intrinsic power value.

Abstract: A method for simulating a response of a circuit to an ESD input stimulus applied to the circuit includes the steps of: receiving a description of the circuit into a circuit simulation program, the circuit including at least one mutual inductance element indicative of magnetic coupling in the circuit; generating a linear approximation of nonlinear elements in the circuit at respective DC bias points of the nonlinear elements; obtaining a frequency domain transfer function of the circuit; obtaining a time domain impulse response of the circuit as a function of the frequency domain transfer function; integrating the time domain impulse response to yield a step response of the circuit, the step response being indicative of a response of the circuit to the ESD input stimulus; and analyzing the step response of the circuit to determine whether the circuit will operate within prescribed parameters corresponding to the circuit.

Abstract: One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.

Abstract: A system and method of analyzing a power grid in an integrated circuit includes inputting a circuit design to a test bench, inputting a plurality of initial values for the circuit design in to the test bench, setting a current time t to 0 value for an initial time (t0) of the operation of the circuit design, representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model, describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations, storing the plurality of linear equations in a matrix Y0 for time t0, resolving the matrix Y0 to determine a DC operating point, updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t1=t+h where h is a time step value equal to the current time t and a next simulated operation time, storing the updated plurality of linear equations in a matrix Y1 for ti

Abstract: A differential amplifier and a method for generating a computer simulation model thereof are disclosed. The device is thermally stable through adoption of a ballast resistor to a differential structure of a unit transistor pair, such that the differential amplifier prevents heat effect phenomena, such as performance deterioration and device destruction by heating, and, at the same time, improves or maintains other performances, thereby achieving high gain, high efficiency, high linearity, and wide bandwidth characteristics. Therefore, the differential amplifier can be easily designed as undesired effects of parasitic resistor of emitter or via or bonding wire, etc. for the differential amplifier are reduced in a differential mode.

Abstract: Programmable devices include configurable logic hardware for implementing logic gates, registers for storing data, and secondary hardware for additional functions, such as loading and clearing. The secondary hardware can implement portions of the user design, thereby decreasing the number of gates to be implemented elsewhere. A set of possible alternative implementations of portions of the user design is identified by enumerating the inputs connected with a register. Logic diagrams are created for the set of inputs, and alternative implementations are identified from the logic diagrams by recognizing patterns similar to the secondary hardware functions. To determine an implementation that balances gate savings against routing costs, alternative implementations are grouped according to compatible inputs and ranked by the number of registers in each group. The implementation with the highest rank is selected, and selected registers are removed from other alternative implementations.

Abstract: An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.

Abstract: A method of generating debug data in a simulation environment includes generating a listing of one or more signals that relate to a failure signal; monitoring simulation data of the one or more signals for transitions between a defined state and an undefined state; and generating a waveform of data based on the transitions between the defined state and the undefined state.

Abstract: Methods and apparatus utilizing media characterization of memory devices facilitate the development of signal processors for analyzing memory device outputs. Models are developed from capturing output of memory devices of the type utilizing analog signals to communicate data values of two or more bits of information. The models are used to generate signals representative of the expected output of a memory device having an input data pattern. Read channels and/or controllers then process those signals to determine an output data pattern. By comparing the output data pattern to the input data pattern, the accuracy of the signal processing can be gauged.

Abstract: In a method of generating variation-aware library data for statistical static timing analysis (SSTA), a “synthetic” Gaussian variable can be used to represent all instances of one or more mismatch variations in all devices (e.g. transistors), thereby capturing the effect on at least one timing property (e.g. delay or slew). By modeling device mismatch with synthetic random variables, the variation behavior (in terms of the distribution of delay, slew, constraint, etc.) can be interpreted as the outcomes of process variations instead of modeling the variation sources (e.g. transistor shape variations, variations in dopant atom density, and irregularity of edges).

Abstract: A simulation of an electronics system which performs a set of operations of interest. A simulated supervisory circuit detects a state in which all the operations have been completed, and also determines the amount of time until the occurrence of the next relevant event. Simulation time is then advanced by that amount of time. This enables simulation time corresponding to an inactive system to be eliminated.

Abstract: Method and system for application specific integrated circuit (ASIC) simulation, wherein the ASIC includes plural logical elements is provided. The method includes, monitoring transitions at an output of a logic element of the ASIC; checking if the transition is to an unknown value (X); verifying if the unknown value is based on a design error; forcing the output of the logic element to a known value if the unknown is an unwanted condition; propagating the known value to logic elements in the ASIC; and releasing the known value after a next command.

Abstract: An area partitioning processing unit equally partitions a power source network analysis object area of an LSI according to the number or size of partitioned areas specified by a user or partitions the power source network analysis object area according to the user's specification. A border processing unit extracts and adds a range-of-influence part of the power source network that can electrically influence a border between the partitioned area partitioned by the area partitioning processing unit and an adjacent power source network area. A modeling processing unit performs processing of resistance modeling of the partitioned area or a correction spot with the range-of-influence part added thereto by the border processing unit. A power source network analyzing processing unit analyzes a resistance model modeled by the modeling processing unit and calculates potential of each via as a current source to a load element.

Abstract: A power circuit protection and control device simulator emulates in real time identical circuit protection and control functions performed by the actual device being simulated and generates real time simulated operational information concerning at least one of the device or the power circuit. A human-machine interface, such as through a web browser, allows a user to input power circuit operational parameters, such as motor current and load, and device variable circuit protection and control operational parameters, such as trip class, ground fault detection or phase unbalance protection. The simulator displays in real time simulated operational information on the human-machine interface. The simulator may be used to simulate operation of an electronic overload relay and an electric motor controlled by the relay.

Abstract: A circuit simulation apparatus includes a first acquisition unit that acquires information on a jitter transfer function of a jitter pass element with respect to a predetermined frequency band, a second acquisition unit that acquires information pertaining to input jitter to the jitter pass element, a first calculation unit that determines a jitter frequency based on the information acquired by the first acquisition unit or the second acquisition unit to calculate a jitter transfer function value which is a value of the jitter transfer function acquired by the first acquisition unit at the jitter frequency, and a second calculation unit that calculates output jitter from the jitter pass element based on the information pertaining to the input jitter acquired by the second acquisition unit and the jitter transfer function value calculated by the first calculation unit.

Abstract: The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added.

Abstract: Method and apparatus for channel simulation is disclosed. The claimed invention provides method and apparatus 1200 to simulate a propagation channel, particularly a multiple-input-multiple-input (MIMO) channel. The claimed invention further provides a method and apparatus for efficient optimization of antenna by the enhanced channel simulation. The claimed invention takes both antenna characteristics and channel characteristics as inputs, and output time-varying channel realizations to generate the system metrics as the optimization target for antenna under optimization. The claimed invention advantageous provides enhanced channel simulation to meet the accuracy requirement of antenna evaluation.

Abstract: Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks.

Abstract: A hardware simulation and validation system is provided using a plurality of signal interface controllers to exchange stimulus and response signals with a hardware simulation. The action of the signal interface controllers is coordinated by a test scenario manager which exchanges test scenario controlling messages with the signal interface controllers. The test scenario controlling messages specify simulation actions to be performed and when those simulation actions are to be performed.

Abstract: A system, method, computer program and article of manufacture for channel analysis. Channel analysis is a multi gigahertz capacity time domain circuit simulation which uses the impulse response of the channel to determine optimum filter settings and to produce wave form plots in a fraction of the time of circuit simulation.

Abstract: A circuit simulating apparatus includes a block dividing unit that divides a logic circuit into a plurality of partial circuits; a pattern generating unit that generates a simulation-purpose pattern to an input terminal of the partial circuit; and a phase-difference setting unit that sets a phase difference between input simultaneously-changing signals as phase-difference setting information for each input terminal of the analysis-target circuit. The apparatus also includes a signal-waveform generating unit that generates a simulation signal waveform reflecting the phase difference for each input terminal of the analysis-target circuit; and a simulation performing unit that receives an input of the simulation signal waveform for each input terminal of the analysis-target circuit to obtain a timing analysis result of the analysis-target circuit based on the input result.

Abstract: A method of testing an electronic circuit is provided. The method comprises radiating a laser beam onto the electronic circuit, and determining a plurality of samples of a response signal output by the electronic circuit during the period when the laser beam is radiated. The method further comprises accumulating the plurality of samples to generate a value, and generating a test result based on the value.

Abstract: A method and system for feedback circuit design are disclosed. In one aspect, a method of feedback circuit design includes simulating a reference circuit design having a feedback stage at a target crossover frequency, determining an initial phase margin at the target crossover frequency, and adding an impedance network to the feedback stage if the initial phase margin is less than a threshold phase margin. The design of the impedance network is determined such that the initial phase margin is increased.

Abstract: In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level at at least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter.

Abstract: A system and method are disclosed which may include measuring a leakage current level of a processor or multiprocessor chip; and storing an indicator value indicative of the leakage current level in a memory associated with the processor or multiprocessor chip.