Circuit Simulation Patents (Class 703/14)
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Patent number: 7698678Abstract: Apparatus and program product for designing vertical parallel plate (VPP) capacitor structures in which the capacitor plates in different conductive layers of the capacitor stack have a different physical spacing. The methodology optimizes the physical spacing of the plates in each conductive layer to achieve a targeted electrostatic discharge protection level and, thereby, supply electrostatic discharge robustness.Type: GrantFiled: August 13, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventor: Steven H. Voldman
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Patent number: 7698118Abstract: A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.Type: GrantFiled: April 15, 2004Date of Patent: April 13, 2010Assignee: Mentor Graphics CorporationInventor: Frederic Reblewski
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Publication number: 20100085679Abstract: A method for simulating the effect of trapped charge in an electrostatic chuck on the chuck performance comprises creating a trapped-charge electrical model having a trapped-charge capacitor and a gap-trapped resistor, and coupling the model to a plurality of voltage sources. The trapped-charge capacitor and the gap-trapped resistor may be varied in relation to a plurality of electrostatic chuck physical parameters.Type: ApplicationFiled: December 12, 2008Publication date: April 8, 2010Applicant: LAM Research CorporationInventors: Konstantin Makhratchev, Brian McMillin
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Publication number: 20100088083Abstract: A method of integrated circuit simulation comprising the steps of providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type. Providing a temperature lookup table having predetermined temperature data. Providing a transistor lookup table having predetermined current and temperature data. Simulating operation of an integrated circuit by, for each transistor in the integrated circuit, determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and comparing the current value calculated to the current value obtained previously; and updating active transistor list detecting a change in the current value. Then incrementing a simulation time step and repeating simulation steps for all transistors.Type: ApplicationFiled: October 8, 2008Publication date: April 8, 2010Applicant: VNS PORTFOLIO LLCInventor: Steven Leeland
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Patent number: 7693700Abstract: Circuits, methods, and apparatus for including interconnect parasitics without greatly increasing circuit simulation complexity and run times. Interconnect paths are reduced to one of a number of simplified topologies based on path width, length, or other parameters. The input drive waveform is similarly approximated. A grid array is formed in advance, where each point in the grid array corresponds to a set of values relating to a path topology, input waveform, and resulting output waveform. The simplified interconnect path and input waveform are mapped into a set of parameters which corresponds to a location in the predetermined grid array. The output waveform is determined by interpolating output waveforms from gridpoints surrounding the location.Type: GrantFiled: June 13, 2003Date of Patent: April 6, 2010Assignee: Altera CorporationInventors: Tim Vanderhoek, David Lewis
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Patent number: 7694248Abstract: An apparatus for supporting verification includes a detecting unit that detects description data of a false path from setting data for a system mode operation of a target circuit to be verified; an analyzing unit that analyzes the description data in the system mode operation and a test mode operation of the target circuit; a diversion determining unit that determines, based on a result of analysis by the analyzing unit, whether the description data is divertible to the test mode operation; and a generating unit that generates setting data for the test mode operation based on a result of determination by the determining unit.Type: GrantFiled: October 14, 2005Date of Patent: April 6, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Toshihito Shimizu, Koichi Itaya, Hitoshi Watanabe
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Patent number: 7693701Abstract: A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.Type: GrantFiled: June 3, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Owen Chiang, Christopher M. Durham, Peter J. Klim, James D. Warnock
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Publication number: 20100082308Abstract: A circuit simulation apparatus is provided with a parameter calculating tool and a circuit simulator. The parameter calculating tool is configured to extract gate spacings between gates of a target MOS transistor and adjacent MOS transistors integrated in an integrated circuit from layout data of the integrated circuit, and to calculate a transistor model parameter corresponding to a threshold voltage of the target MOS transistor based on the extracted gate spacings. The circuit simulator is configured to perform circuit simulation of the integrated circuit by using the calculated transistor model parameter.Type: ApplicationFiled: September 25, 2009Publication date: April 1, 2010Inventor: Hideo Sakamoto
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Publication number: 20100082304Abstract: A power supply noise analysis model creation method comprising; obtaining a distance which appears most frequently, from among the distances from a vias judged to be the nearest to the vias, respectively, as a reference via pitch, generates four nodes for the via of target wherein the four nodes generates the middle point with the other four via that are near the via of the target, obtaining meshes which include the nodes, respectively, by dividing the power island structure and the power supply pair by dividing lines which pass between the generated nodes, and converting each of the meshes obtained to a circuit element equivalent to the mesh.Type: ApplicationFiled: September 28, 2009Publication date: April 1, 2010Applicant: FUJITSU LIMITEDInventors: Shogo Fujimori, Koutarou Nimura, Tendou Hirai
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Publication number: 20100083196Abstract: By carrying out circuit simulations, paretos that are non-dominated solutions in a solution specification space for respective items in the requirement specification are obtained for all of circuit configurations having possibility that requirement specification is satisfied, and a provisional optimal solution, which is on a pareto curved surface identified by the obtained paretos and whose distance with the requirement specification is shortest, is identified. Furthermore, a circuit configuration corresponding to the provisional optimal solution is identified and the provisional optimal solution is mapped to values of circuit parameters. Then, the pertinent circuit configuration and values of the circuit parameters, which are obtained by the mapping, are outputted.Type: ApplicationFiled: September 24, 2009Publication date: April 1, 2010Applicant: FUJITSU LIMITEDInventor: Yu Liu
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Patent number: 7689400Abstract: Systems, method, and media for reconstructing data from simulation models are disclosed. Embodiments may include a method for accessing an alias from an alias file. The method may generally include searching for a net name and, if the net name is not found, searching an alias index file for an alias index entry associated with the net name, the alias index entry having a net name and an associated position. The method may also generally include, if the net name entry is found, accessing from an alias file an alias associated with the net name. A further embodiment may generally include receiving a net name and a position of an alias in the alias file, creating an alias index entry for the alias having a net name and the position of the alias, and storing the created alias index entry in the alias index file.Type: GrantFiled: January 2, 2009Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Charles Lenier Alley, Anthony Joseph Bybell
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Patent number: 7689960Abstract: A method for verifying library components and designs on a via customizable ASIC, which may include the process of adding capacitors to model possible via sites of a model of an un-customized portion of or a whole ASIC, and replacing the capacitors with resistors to model where custom vias have been placed on the ASIC to implement a desired component or design. Views of this model may then be generated to verify the functionality of the component or design, and component models for timing, function and via customization may then be generated for the component library.Type: GrantFiled: January 25, 2006Date of Patent: March 30, 2010Assignee: eASIC CorporationInventors: Jonathan Park, Yit Ping Kok, Soon Chieh Lim, Yin Hao Liew, Wai Leng Chek
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Patent number: 7689399Abstract: A method for automatic extraction of design properties of a hardware design, is provided. The method includes running a hardware design simulation to generate simulation results for the hardware design. The simulation results are then analyzed to extract properties. The extracted properties can be a powerful tool for the design engineers and the test-writers to learn more about the functional coverage of the test suites.Type: GrantFiled: August 31, 2004Date of Patent: March 30, 2010Assignee: Sun Microsystems, Inc.Inventors: Sudheendra G. Hangal, Naveen Chandra
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Patent number: 7689941Abstract: Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.Type: GrantFiled: May 11, 2007Date of Patent: March 30, 2010Assignee: Altera CorporationInventors: Teng Chow Ooi, Yanzhong Xu, Jeffrey T. Watt, Haiming Yu
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Patent number: 7689952Abstract: A system that includes a candidate generator that generates candidate vectors having as components performance specifications of an electrical circuit design. The system also includes a performance estimator that generates performance vectors of the electrical circuit design, the performance vectors having as components performance values of the electrical circuit design. The candidate vectors and the performance vectors are input into a statistical estimator that calculates a statistical parameter, for example, yield, for each candidate vector in accordance with the performance vectors. The system further includes a filter that receives the candidate vectors and their respective statistical parameters, and outputs a filtered candidate vector with its corresponding filtered statistical parameter. A display system visually represents the filtered candidate vector and its corresponding filtered statistical parameter.Type: GrantFiled: July 19, 2007Date of Patent: March 30, 2010Assignee: Solido Design Automation Inc.Inventors: Trent Lorne McConaghy, Charles Cazabon, Jiandong Ge, Shawn Rusaw, Kristopher Breen, Jason Coutu
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Patent number: 7689948Abstract: Methods and systems for the integration of models and accurate predictions to score the circuit design, which translates to a more accurate and less complex yield prediction. In the present inventive approach, the computer-implemented methods and systems use at least one processor that is configured for performing at least predicting a physical realization of a layout design based at least in part on one or more model parameters, determining one or more hotspots associated with the layout design, determining a score for each of the one or more hotspots associated with the layout design, and categorizing the one or more hotspots according to at least the score in some embodiments. In some embodiments, the methods or the systems further use at least one processor for the act of determining one or more hotspots by using at least the design intent or the manufacturing information.Type: GrantFiled: February 24, 2007Date of Patent: March 30, 2010Assignee: Cadence Design Systems, Inc.Inventors: David White, Roland Ruehl, Mathew Koshy
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Publication number: 20100076736Abstract: A statistical SPICE model parameter calculation method in which it is possible to create a variation model having high accuracy and size dependency. A principal component analysis is performed, for respective device sizes, of a measurement of an element characteristic value of a semiconductor device on which multipoint measurement is performed (principal component analysis process). A statistical SPICE model parameter that reproduces variation of an element characteristic value for a plurality of device sizes is calculated based on a result of the principal component analysis obtained for each of the device sizes and predetermined device size dependency (parameter calculation process).Type: ApplicationFiled: September 23, 2009Publication date: March 25, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: TAKASHI SHIMIZU
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Publication number: 20100076742Abstract: Various embodiments include methods and apparatus for simulating a transistor using a simulation model that includes a transistor simulation model coupled to diode simulation model.Type: ApplicationFiled: September 23, 2008Publication date: March 25, 2010Applicant: Atmel CorporationInventor: Adam H. Pawlikiewicz
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Publication number: 20100076741Abstract: A system for determining a worst condition, wherein, in a model for which one or more parameters included in a model function that simulates a circuit performance index are random variable(s) to simulate the circuit performance index and fluctuations thereof, the parameter(s) for which the circuit performance index assumes a maximum or minimum value that is to be assumed from the viewpoint of designing is determined as the worst condition; the system comprises a worst condition search unit that searches for a point, having a maximum or minimum value of the circuit performance index, on an equi-probability surface corresponding to a preset good product ration within a space defined by the parameter(s); the point thus searched being determined as the worst condition.Type: ApplicationFiled: February 13, 2008Publication date: March 25, 2010Inventor: Kiyoshi Takeuchi
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Publication number: 20100077372Abstract: Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.Type: ApplicationFiled: September 25, 2008Publication date: March 25, 2010Inventors: Hua Xiang, Laertis Economikos, Mohammed F. Fayaz, Stephen E. Greco, Patricia A. O'Neil, Ruchir Puri
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Patent number: 7685553Abstract: An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.Type: GrantFiled: April 11, 2007Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Evanthia Papadopoulou, Ruchir Puri, Mervyn Y. Tan, Louise H. Trevillyan, Hua Xiang
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Patent number: 7685541Abstract: Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is identical between the blocks in a group. For each group of blocks, a respective set of parameters having different values on subblocks of at least two blocks in the group is determined. An HDL specification is generated for each group. The HDL specification for a group has for each parameter in the set of parameters, a parameter input.Type: GrantFiled: May 1, 2008Date of Patent: March 23, 2010Assignee: Xilinx, Inc.Inventors: Jeffrey D. Stroomer, Roger B. Milne, Isaac W. Foraker, Sean A. Kelly
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Patent number: 7685554Abstract: Determining data rates and data types in a an electronic design. In one embodiment, an electronic design is created in a memory arrangement in response to user input. The electronic design includes a plurality of functional blocks and a plurality of nets connecting the functional blocks. In response to user input, an output data rate and an output data type of data output from at least one of the functional blocks are determined. The input data rate and input data type to each functional block coupled via a net to the at least one functional block are equal to the output data rate and output data type, respectively, from the at least one functional block. For each functional block, an output data rate and output data type are determined as a function of the input data rate and the input data type of the functional block.Type: GrantFiled: July 20, 2005Date of Patent: March 23, 2010Assignee: Xilinx, Inc.Inventors: Sean A. Kelly, Roger B. Milne, Jeffrey D. Stroomer, Sreekanth Juttu
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Patent number: 7684969Abstract: Forming of a statistical model for a set of independently variable parameters for analysis of a circuit design is disclosed. In one embodiment, a method includes establishing a timing model including delay and delay changes due to process parameter variations (Pi) that impact timing; selecting an element of the circuit design that dominates circuit delay in the timing model; determining a delay sensitivity of each of a set of derived process parameters (Vj) for the element that are linear combinations of the process parameter variations (Pi); and selecting only those derived process parameters with a high sensitivity for use in the statistical model. The invention simplifies the statistical model and reduces the number of calculations require for timing analysis. A method of performing a timing analysis using the simplified statistical model is also disclosed.Type: GrantFiled: September 2, 2005Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Peter A. Habitz, Mark R. Lasher, William J. Livingstone
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Patent number: 7684968Abstract: Generating a high-level, bit-accurate and cycle-accurate simulation model. The various embodiments generate the simulation model from a functional description of a module and an HDL description of the module. The functional description may be un-timed and specified in a high-level language. The HDL description is realizable in hardware. The simulation model is created by obtaining the control specification from the HDL description and combining the control specification with the data path description from functional description.Type: GrantFiled: December 9, 2004Date of Patent: March 23, 2010Assignee: Xilinx, Inc.Inventors: Gabor Szedo, Singh Vinay Jitendra, L. James Hwang
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Patent number: 7685543Abstract: Disclosed is a simulation apparatus including an input unit, storage unit, arithmetic unit, controller, and output unit. The input unit inputs a first potential at the source end, which corresponds to the gate end of a TFT, on that surface of a thin polysilicon film which faces the gate, a second potential at the source end on the back surface of the thin polysilicon film on which the gate is formed, a third potential at the drain end, which corresponds to the gate end of the TFT, on that surface of the thin polysilicon film which faces the gate, and a fourth potential at the drain end on the back surface of the thin polysilicon film. A drain current is calculated by performing an arithmetic operation on the basis of the first to fourth potentials, and a model is formed by including defect states.Type: GrantFiled: July 12, 2007Date of Patent: March 23, 2010Assignee: Advanced LCD Technologies Development Center Co., Ltd.Inventors: Hiroshi Tsuji, Yoshiteru Shimizu
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Patent number: 7685542Abstract: A method for testing logic devices configured across asynchronous clock domains includes deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at least one data input thereto originating from a source located within an asynchronous clock domain with respect thereto. The deactivation of a local clock signal for each of the plurality of latches is implemented in a manner so as to permit data capture within the first plurality of latches, and wherein the deactivation of a local clock signal for each of the plurality of latches is further implemented in a manner so as to permit at-speed data launch therefrom to downstream latches with respect thereto during at-speed testing.Type: GrantFiled: February 9, 2007Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Gary D. Grise, Vikram Iyengar, Mark R. Taylor
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Publication number: 20100070257Abstract: Disclosed are methods, systems, and computer program products for evaluating performance aspects of electrical circuits, and particularly digital logic circuits. An exemplary method comprises obtaining access to a simulation dump file comprising state indications of the values of a plurality of signals of an electrical circuit at a plurality of simulation time points, and receiving an evaluation task that defines an output based on one or more input signals, with each input signal being a signal for which state indications are provided in the simulation dump file. The method further comprises generating, from the simulation dump file, one or more state representations for the input signals of the evaluation task, with each state representation being representative of the state of an input signal over a period of simulation time, and generating values of the output of the evaluation task at a plurality of simulation time points from the state representations.Type: ApplicationFiled: September 12, 2008Publication date: March 18, 2010Applicant: MIPS Technologies, Inc.Inventors: Ajit Karthik Mylavarapu, Sanjai Balakrishnan Athi
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Publication number: 20100065821Abstract: A molecular quantum interference device is provided. A method for the design of such devices is also provided, the method including modelling of device performance.Type: ApplicationFiled: September 17, 2008Publication date: March 18, 2010Inventors: John Boland, Stefano Sanvito, Zekan Qian, Rui Li, Shimin Hou
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Patent number: 7681151Abstract: A method is provided that includes pattern-matching portions of a block diagram model as being equivalent, and creation of a common set of instructions in place of the occurrences of the pattern-matched portions to enhance the efficiency of simulation or generated code for the block diagram model, such as by a reduced image size. Diagnostics are also available to provide information on the execution structure of the block diagram and guidance on how to modify block of the block diagram to obtain reduced image size by increasing the amount of matching patterns. Also, automatically generated hierarchical structures, a tool to control the function signature and the ability for a user to control file packaging which all provide flexible control over the generated code for block diagrams, are provided.Type: GrantFiled: February 6, 2007Date of Patent: March 16, 2010Assignee: The Math Works, Inc.Inventors: John Ciolfi, Michael David Tocci, Mojdeh Shakeri, Murali Yeddanapudi, Kai Tuschner, Ramamurthy Mani
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Patent number: 7680642Abstract: An equivalent circuit for a coil incorporated in a circuit simulator is a model of an equivalent circuit for a coil included in a circuit simulator for analysis of an electrical device including a coil forming a magnetic circuit. The equivalent circuit of a coil included in an electric motor or other electrical device is preferably comprised of a resistance component (R), induced voltage component (?d?/dt), and inductance component (L). The equivalent circuit of the inductance component is provided with a current source, a voltage extractor for extracting the voltage across the terminals of this current source, a current generator for determining the value of the current of the current source based on the value of the voltage output by this voltage extractor, and a current-carrying path connected in parallel to the current source and carrying a regenerative current at the time of off operation.Type: GrantFiled: December 28, 2005Date of Patent: March 16, 2010Assignee: The Japan Research Institute, LimitedInventors: Hiroshi Hashimoto, Hiroyuki Sano, Tomoyuki Arasawa
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Patent number: 7681156Abstract: A circuit simulator includes: a DC analysis section which analyses a static stable potential on a transmission circuit if a capacitor which blocks a DC current while allowing an AC current to pass therethrough is connected in series in the line of the transmission circuit; and an initial potential application section which applies, as an initial potential in the simulation, the stable potential obtained by the DC analysis section to an application position on the upstream side of the capacitor in the flow of the signal through the transmission circuit. The simulator also includes a circuit simulation section which performs the simulation of the transmission circuit under the initial potential applied by the initial potential application section.Type: GrantFiled: September 5, 2006Date of Patent: March 16, 2010Assignee: Fujitsu LimitedInventors: Makoto Suwada, Masaki Tosaka, Megumi Nagata
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Patent number: 7676351Abstract: A method and system for combining the process variations in circuits and distributed interconnect-based electromagnetic (EM) objects in order to capture a statistical behavior of overall circuit performance parameters. In an exemplary approach, a coupled circuit-EM system is decoupled at the points where the EM objects connect to the circuit portion, and circuit ports are defined at those points. The sources of variation are identified and used to determine Y-parameters for the ports with EM elements and for all EM elements based on the SPICE-like and EM full-wave simulations. A response surface is generated for each variable and is used to extract circuit and EM parameters by generating many random vectors representing combinations of the random variables. These Y-parameters are merged to produce a probability density function (PDF) of one or more performance metrics for the electronic device or system.Type: GrantFiled: July 16, 2007Date of Patent: March 9, 2010Assignee: University of WashingtonInventors: Vikram Jandhyala, Arun V. Sathanur, Ritochit Chakraborty
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Patent number: 7676347Abstract: In one embodiment, there is disclosed a system for accumulation of summaries of test data. The system includes a data populator having code to: (1) generate data objects from the test data and store the data objects in a data model, (2) arrange the data objects in a tree structure, (3) generate summaries of the test data, (4) store the summaries of the test data in the tree structure, and (5) delete the data objects. The system also includes a number of clients in communication with the data model, the clients having code to: (1) selectively read the test data from the data objects stored in the data model, and (2) read the summaries of the test data stored in the tree structure. Other embodiments are also disclosed.Type: GrantFiled: January 31, 2006Date of Patent: March 9, 2010Assignee: Verigy (Singapore) Pte. Ltd.Inventors: Carli Connally, Reid Hayhow, Bryan F. Carpenter
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Patent number: 7676779Abstract: A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.Type: GrantFiled: September 11, 2007Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Reinaldo A. Bergamaschi, Sean M. Carey, Brian W. Curran, Prabhakar N. Kudva, Matthew E. Mariani, Mark D. Mayo, Ruchir Puri
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Patent number: 7676355Abstract: Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, the present invention provides to an end customer IP hardware which is suitable for prototype testing, but unusable for production purposes. One method limits the physical or electrical mode of operation of a hardware platform used for prototype testing of intellectual property (such as limiting the number of electrical contacts between the hardware and an external electrical device or limiting the data format(s) usable in the hardware during prototype testing). Another method limits the temporal operation of a hardware platform using an internal counter within the software provided by the intellectual property owner.Type: GrantFiled: March 10, 2006Date of Patent: March 9, 2010Assignee: Altera CorporationInventors: Philippe Molson, Tony San
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Publication number: 20100057411Abstract: A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via.Type: ApplicationFiled: June 26, 2009Publication date: March 4, 2010Applicant: Qualcomm, Inc.Inventors: Xia Li, Wei Zhao, David Bang, Yu Cao, Seung H. Kang, Matthew Nowak
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Publication number: 20100057425Abstract: A system for creating manufacturing test rules. Stimuli for an electronic design are generated automatically by a stimuli generator. The stimuli generator takes into account certain limitations of the design when automatically generating the manufacturing test rules. The design is tested by a testbench using the stimuli. A simulation log for the design is generated by the testbench. The simulation log is then processed by a simulation log processor. An HDL representation of the design is generated by the simulation log processor using the processed simulation log. A gate-level version of the design is generated by a synthesis tool using the HDL representation of the design. The gate-level version of the design is further processed by the synthesis tool to make any necessary modifications. Then, the gate-level version of the design is outputted as the final manufacturing test rule. Thus, creating manufacturing test rules can be completely automated.Type: ApplicationFiled: September 2, 2008Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Glen Gerowitz, Michael Patrick Muhlada, Chad Everett Winemiller
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Publication number: 20100057426Abstract: A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.Type: ApplicationFiled: October 26, 2009Publication date: March 4, 2010Applicant: MENTOR GRAPHICS CORPORATIONInventor: Frederic Reblewski
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Publication number: 20100057417Abstract: Generating a hardware description for a programmable hardware element based on a graphical program including multiple physical domains. A graphical program may be received which includes a first portion of a first physical domain for simulating a first portion of a physical system. The graphical program may include a second portion of a second physical domain for simulating a second portion of the physical system. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to simulate the physical system.Type: ApplicationFiled: September 29, 2009Publication date: March 4, 2010Inventors: Duncan G. Hudson, III, Rishi H. Gosalia
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Publication number: 20100057412Abstract: Characteristics of a circuit element are predicted accurately by taking account not only of the temperature variation due to self-heating of the element but also of temperature variation due to heat transmission from an adjoining heater element.Type: ApplicationFiled: December 13, 2007Publication date: March 4, 2010Applicant: NEC CorporationInventors: Masahiro Tanomura, Naotaka Kuroda, Masafumi Kawanaka
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Publication number: 20100057424Abstract: The invention relates to a method for rating the quality of a test program for integrated circuits simulated by means of a computer, comprising (a) provision of a first file which describes an integrated circuit; (b) simulation of a mutated integrated circuit which is obtained by incorporating mutations into the integrated circuit described in the first file; (c) supply of input values to the mutated integrated circuit and recording of the output values produced for these input values by the mutated integrated circuit; (d) comparison of the output values produced by the mutated integrated circuit with expected values which are provided by the test program, where the expected values have been generated in a reference system; and (e) rating of the quality of the test program on the basis of the comparison results.Type: ApplicationFiled: July 28, 2005Publication date: March 4, 2010Inventors: Joerg Grosse, Mark Hampton
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Patent number: 7673265Abstract: A simulation apparatus, including a first simulator assigning an operating cycle number, a second simulator assigning an operating cycle number, and a control portion for synchronously controlling the first simulator and the second simulator, the control portion causing communication between the first simulator and the second simulator so as to control control-information and synchronous-information of the first simulator and the second simulator, the control-information controlling operations of the first simulator and the second simulator, wherein the control portion sets up the operating cycle numbers of the first simulator and the second simulator at a first cycle value when a synchronous condition of the synchronous-information is established, the control portion sets up at least one of the operating cycle numbers of the first simulator and the second simulator at a second cycle value being larger than the first cycle value when the synchronous condition of the synchronous-information is not established.Type: GrantFiled: September 6, 2007Date of Patent: March 2, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Akiba, Takashi Miura
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Patent number: 7672827Abstract: A system and method for simulating the electrical operation of a mixed analog/digital system includes the capability for analog circuit block inputs to respond to the condition in which digital gate outputs connected to the analog circuit block input are presented in high-impedance or floating signal states, thereby providing for simulation of a wide variety of mixed analog/digital designs in which this condition occurs. In a simulated design, an analog input of one or more analog circuit blocks is transformed into an analog tri-statable input-output referred to as an ioput. The ioput is capable of driving an analog signal when the digital gate outputs connected to the analog block input are presented in a high-impedance Z state; otherwise, the ioput acts as an analog input to the analog circuit block.Type: GrantFiled: August 28, 2000Date of Patent: March 2, 2010Assignee: Cadence Design Systems, Inc.Inventors: Alexander D. Schapira, Asha Chandra, Jonathan A. Eiseman
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Patent number: 7673288Abstract: A method is provided that speeds up software testing using abbreviation of software tests that skips the execution of a portion of the software test. Intermediate results are generated for one or more software tests, with each intermediate result corresponding to a software test, and a respective key is generated from each intermediate result. A determination is made whether the respective key for each intermediate result is stored in a file cache used for storing files under keys. Generation of a final result for the corresponding software test of each intermediate result is bypassed in response to the respective key being present in the file cache. A final result for the corresponding software test of each intermediate result is generated from the intermediate result in response to the respective key not being present in the file cache. The respective key is stored in the file cache in response to generation of each final result.Type: GrantFiled: November 1, 2005Date of Patent: March 2, 2010Assignee: XILINX, Inc.Inventor: Jeffrey D. Stroomer
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Patent number: 7673259Abstract: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.Type: GrantFiled: December 30, 2005Date of Patent: March 2, 2010Assignee: Cadence Design Systems, Inc.Inventors: Luciano Lavagno, Alex Kondratyev, Yosinori Watanabe
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Publication number: 20100049495Abstract: The present invention relates to a system for synthesizing an electronic circuit at plural abstraction levels. The system includes one or more evaluation tools for evaluating the performance and/or behavior of the circuit at the abstraction levels. The system further includes means for passing parameters and/or performances between abstraction levels and/or evaluation tools. The system is adapted for evaluating the performance and/or behavior of the circuit using at least part of the passed parameters and/or performances at a plurality of the abstraction levels within one synthesis iteration.Type: ApplicationFiled: October 2, 2007Publication date: February 25, 2010Inventors: Kenneth Francken, Martinus Antonius Hendrikus Vogels, Jan Maria Jozef Decaluwe
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Patent number: 7669154Abstract: This invention intends to provide timing analysis methods, timing analysis programs, and timing analysis tools for the purpose of performing timing verification in optimum conditions without any excessive variations by statistically dealing with variations in elemental devices forming a semiconductor integrated circuit. In order to verify a timing between two signals, a delay value of a signal propagating through a signal path selected as a candidate for timing analysis is obtained, and with respect to a random variation amount of the delay value, a random variation amount corresponding to the number of gate circuit stages forming the signal path is obtained. Then, based on the delay value and the random variation amount, a most severe variation amount between the two signals in a most severe operating condition is obtained, and based on the most severe variation amount, a respective individual variation coefficient is allocated for each gate circuit, thereby performing a timing analysis.Type: GrantFiled: August 19, 2005Date of Patent: February 23, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Toshikatsu Hosono
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Patent number: 7665046Abstract: A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.Type: GrantFiled: April 3, 2007Date of Patent: February 16, 2010Assignee: Synopsys, Inc.Inventors: Chun Kit Ng, Kenneth S. McElvain
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Publication number: 20100036516Abstract: The invention relates to a method of simulating an electronic circuit, represented in the form of masks and connections, comprising: a) the definition of the circuit in the form of a first list (140) of electrical components and their interconnections, b) the separation of the data of this first list into a first sub-assembly (170) of components to be modified by a filtering step, and into a second sub-assembly (160) of components not to be modified by this filtering step, c) the filtering of the data of the first sub-assembly (170) of components, d) the definition of the circuit in the form of a second list (190) of electrical components and their interconnections, from the data of the second sub-assembly (160) and the data resulting from step c), e) the simulation (195) of the circuit by means of this second list, f) if the result of the simulation is satisfactory, the manufacture of the circuit.Type: ApplicationFiled: June 3, 2009Publication date: February 11, 2010Applicant: EDXACTInventors: Francois CHARLET, Mathias Silvant