Abstract: Aspects of the invention relate to techniques for detecting and correcting electrical hotspots in a layout design for a circuit design comprising an analog circuit. Layout parameters for device instances associated with electrical constraints are first extracted. Based on the extracted layout parameters, electrical parameter variations for the device instances may be computed to identify one or more electrical hotspots in the layout design. A sensitivity analysis of the one or more electrical hotspots is performed to generate repair hints. Based on the repair hints, the layout design is adjusted.

Abstract: A method of identifying memory nodes includes reading a netlist of the design. For a sequential cell of the design, constraint arcs between constraint and related pins can be extracted. For each constraint arc, an original vector set including initialization waveforms can be generated. A plurality of simulations can be run using a plurality of vector sets to generate a plurality of node sets. Each simulation generates a corresponding node set that toggles based on waveforms provided by a corresponding vector set. Each vector set is derived from the original vector set. A final set of memory nodes for the sequential circuit cell can be calculated by subtracting one node set from another node set. In one embodiment, the method can further include pruning non-gate connected nodes from the final node set.

Abstract: A method and system for controlling granularity of transaction recording and visualizing system performance and behavior in a discrete functional verification software simulation environment is disclosed. According to one embodiment, a simulation of a model is run in a discrete event simulation system for a period of time. During the simulation, statistical values of attribute for a plurality of transactions occurring during the period of time are monitored. Based on a granularity setting, a group of consecutive transactions is grouped into a super transaction, and the statistical values representing the super transaction are recorded to represent the group of transactions. The super transactions are visualized in a visualization tool for analyzing the performance of the model.

Abstract: A system for generating behavioral models for analog circuits may include a database that is configured to store a parameterized hardware description language model of an analog circuit and an analog circuit simulator template of the analog circuit. The system may also include an interface module configured to receive data for an instance of the analog circuit in a schematic format. The system may also include an analog circuit simulator configured to use the received data and the analog circuit simulator template to generate a value for a parameter of the parameterized hardware description language model of the analog circuit. The system may also include a model constructor configured to generate a behavioral hardware description language model of the instance of the analog circuit based on the parameterized hardware description language model of the analog circuit and the generated value.

Abstract: An abstract trace may be defined based on a coverage goal. An execution of a System Under Test (SUT) is guided in accordance with the coverage goal. Non-deterministic decision, which correlates to receiving a stimulus to the SUT, is decided based on a probability function. After one or more executions, the probability function is modified based on a measurement of similarity between the abstract trace and each of the one or more executions. The modification of the probability function may be performed using on Cross-Entropy method. The modification is performed in order to cause determination of non-deterministic decisions in executions to better correlate with the abstract trace. In some exemplary embodiments, a determination whether the abstract trace is reachable is determined based on a rate of convergence of the executions to the abstract trace.

Abstract: A method for compensating for a dielectric absorption effect in a measurement configuration during measurements by an instrument having measurement terminals includes providing a feedback loop in the instrument, the loop having a gain adjustment and a simulation impedance and being adapted to provide a signal counter to the dielectric absorption at the measurement terminals; applying a transient calibration signal to the test terminals for at least two values of the gain adjustment; measuring a response to the calibration signal for each of the at least two values; and determining an operating value of the gain adjustment based on the measured responses. The operating value is used for subsequent measurements by the instrument, the simulation impedance modeling the dielectric absorption characteristics of the measurement configuration.

Abstract: A circuit is simulated by using distributed computing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing (e.g., using multiple processor cores or multiple processors). Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.

Abstract: A computer-implemented method for modeling Spatially Correlated Variation (SCV) in a design of an Integrated Circuit (IC) is disclosed. In one embodiment, the method includes: generating a set of coefficient values for a position dependent SCV function, the set of coefficient values being selected from a set of random variables; obtaining a set of coordinates defining a position of each of a plurality of devices in a defined field; evaluating the position dependent SCV function to determine a device attribute variation for each of the plurality of devices based upon the coordinates of each of the plurality of devices; modifying at least one model parameter based upon the evaluation of the position dependent SCV function; and running a circuit simulation using the at least one modified model parameter.

Abstract: A simulation testing system is used to test power consumption of an electronic device including a plurality of electronic components. The simulation testing system includes a power supply unit, a main controller connected to the power supply unit, and a simulation system comprising a plurality of heating resistors arranged in a matrix. Each of plurality of heating resistor is connected to the power supply unit via a switch controlled by the main controller. The main controller turns on a number of the switches to power on the number of the plurality of heating resistors and to simulate a plurality of electronic components of the electronic device.

Abstract: The interactive grouping tool offers the flexibility to simplify the schematic diagram of an integrated circuit (IC) design by grouping circuit elements that are not specified to be of interest into entities of any size. Circuit elements of various types and functionalities, including ports and pins, can be combined together into the same entity without modifying the underlying design logic and connectivity. By grouping and hiding the unnecessary details, the tool reduces clutter in a schematic diagram and greatly eases the process of traversing, debugging, and analyzing the schematic diagram. Users can choose to dynamically group the circuit elements on the schematic diagram without going through any compilation or synthesis process. Users can also choose to revert any of the entities back to the original schematic diagram with the ungrouping operation. For specific or batch manipulation of the schematic diagram, the tool provides a scripting interface for users to enter commands.

Abstract: A static voltage drop analyzing apparatus applied to a Multi-Threshold Complementary Metal-Oxide-Semiconductor (MTCMOS) transistor is provided. The static voltage drop analyzing apparatus includes a calculating module, a processing module, and a measuring module. The calculating module calculates a voltage drop tolerance according to the voltage drop characteristic of the MTCMOS transistor. The processing module selects a simulation metal layer corresponding to the voltage drop tolerance from a plurality of candidate simulation metal layers, and adds the simulation metal layer into the MTCMOS transistor. The measuring module measures the voltage drop of the simulation metal layer added into the MTCMOS transistor. The measured voltage drop of the simulation layer added into the MTCMOS is substantially the static voltage drop of the MTCMOS transistor.

Abstract: Modeling systems and methods for constructing one or more models of a computing system using collected data. Certain model-based systems build topology models and/or model instances by transforming collected performance data into a collection-location independent form. In certain examples, systems include at least one agent for collecting performance data from monitored resource(s), canonical data transform (CDT) configurations, and a data transformation module for performing data transform operation(s) on the performance data based on at least one CDT configuration. The data transform operation may include generating and/or updating a topology model, assigning metrics to model object(s), updating properties of model object(s), creating associations between existing model objects, or the like. Certain systems and methods also allow for a single piece of data to be processed by multiple models or for pieces of data collected from different locations to be matched and/or associated with the same model object.

Abstract: A mechanism for providing equation-level diagnostic error messages for system models undergoing circuit simulations is discussed. The components in a model of a system being simulated are converted into multiple numerical equations where each equation corresponds to a component in the system being simulated or a topology equation for the system model. Each numerical equation is numerically analyzed in order to identify illegal configurations in the system. Upon detection of an error, an error message listing the components associated with the illegal configuration is generated for the user.

Abstract: A circuit design is simulated in a simulation environment. When a simulation model in the simulation environment transfers state information to a second simulation model, the simulation environment receives the state information and makes it available to the second simulation model without simulating the transfer through the simulated circuit design.

Abstract: A mechanism for improving speed of simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having identical properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, then output values of the previously-evaluated transistor or device are used in calculating the output values of the present transistor or device.

Abstract: A processor for use in simulating operation of a portion of an electrical circuit is provided. The processor is configured to receive at least one input indicative of electrical circuit data related to the electrical circuit being simulated, generate a model of the electrical circuit based on the at least one input, receive a user input that indicates the portion of the electrical circuit to be simulated, generate, based on the user input and the electrical circuit model, a partial circuit snapshot that corresponds to the portion of the electrical circuit, and apply at least one event to the partial circuit snapshot to simulate operation of the corresponding portion of the electrical circuit.

Abstract: A computer-implemented method for simulating an electrical circuit. The method includes (a) setting a first temperature distribution in the electrical circuit, (b) performing an electrical simulation across the electrical circuit taking into consideration the first temperature distribution, (c) performing a thermal simulation across the electrical circuit taking into consideration a result of the electrical simulation, to obtain a second temperature distribution, and (d) determining whether a criterion for termination the simulation is met. If the criterion is met, terminate the simulation. If the criterion is not met, assign the second temperature distribution to the first temperature distribution, and repeat steps (b), (c), and (d).

Abstract: A system and method of accelerating sparse matrix operations in full accuracy simulation of a circuit includes determining repetitive blocks of the circuit, determining a set of values of a current block, determining whether the state of the current block is sufficiently close to the state of a stored block solution when the corresponding values are within a predetermined error range, and performing a reduced computation using the stored block solution to provide a solution for the current block when the states are sufficiently close to each other. The reduced computation includes retrieving previously stored solutions and performing substantially simplified matrix and vector operations while maintaining accuracy of the solution. Reduced precision versions of the values may be used to generate a hash index used to store the block solutions. Stored redundant device information may also be used to simplify device solutions in a similar manner.

Abstract: For multicore power performance management, a first core has a first architecture and is designed for a first voltage-frequency domain. A second core has the first architecture and that is designed for a second voltage-frequency domain.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (IC) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one IC chip; obtaining user input data about the at least one IC chip; and running an IC library defining program using the chip design data in its original format and the user input data in its original format, the running of the IC library defining program including: determining a process variation for the at least one IC chip based upon the chip design data and the user input data; converting the process variation into shape variation data; and providing the shape variation data in a text format to a scatterometry modeling program for use in the scatterometry analysis.

Abstract: An energy-aware backfill scheduling method combines overestimation of job run-times and processor adjustments, such as dynamic voltage and frequency scaling, to balance overall schedule performance and energy consumption. Accordingly, some scheduled jobs are executed in a manner reducing energy consumption. A computer-implemented method comprises identifying job performance data for a plurality of representative jobs and running a simulation of backfill-based job scheduling of the jobs at various combinations of run-time over-estimation values and processor adjustment values. The simulation generates data including energy consumption and job delay. The method further identifies one of the combinations of values that optimizes the mathematical product of an energy consumption parameter and a job delay parameter using the simulation generated data for the plurality of jobs.

Abstract: A method for simulating an arc flash event on an electrical power system is disclosed. The virtual system model of the electrical system is modified to introduce a short circuiting feature. The standard to supply equations used in the arc flash event calculations is chosen. The arc flash event is simulated using the modified virtual system model in accordance with the chosen standard. The quantity of arc energy released by the arc flash event is calculated using results from the simulation. The report that forecasts an aspect of the arc flash event is communicated.

Abstract: In a fast simulation technique, the output node of a power supply module of the integrated circuit can be designated as an ideal power node. At this point, the power supply module can be designated a fan-in block and any blocks connected to the power node can be designated fan-out blocks. Then, DC initialization and transient simulation for each time step can be performed for the circuit. During the transient simulation, any inter-relationship of the fan-out blocks can be determined and a sensitivity model can be calculated for each fan-out block. Because the power node is designated as an ideal power node, the results of the sensitivity model for each fan-out block can be added asynchronously to a total loadings of the power node. The total loadings can be loaded into a matrix, which is computed for the fan-in block, and a simulation waveform point can be output.

Abstract: A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.

Abstract: Methods for generating waveforms with realistic transitions, controllable timing jitter, and controllable amplitude noise in a computer-based simulation environment are disclosed. A first method includes obtaining signal information for one or more parallel data signals. In one embodiment, signal information for the one or more parallel data signals is mapped from an HDL format to a new time scale, and during this operation, timing jitter is added independently to the parallel data signals. These jittery parallel data signals may then be returned to the original HDL format, or another format, for simulation. In another embodiment, rather than mapping to a single time vector, information from each signal is modified to have a time scale commensurate with noise and jitter to be added. Timing jitter is superimposed onto each transition, rise and fall times are incorporated, and missing voltage and timing information for each data signal is interpolated into vectors representing the signals.

Abstract: A machining-related data processing system has a configuration in which a controller for machine tool comprising an NC device and an assisting device is connected to a data processing device via a telecommunication line.

Abstract: An approach for methodology enabling a verification of IC designs that compensates for degraded performance due to a physical placement, particularly a stacked physical placement is disclosed. A set of stacked devices from a plurality of devices in an IC design is determined. One or more instance parameters indicating a physical placement of a device in the set is determined. A compensation metric indicating one or more electrical characteristics of a device in the set is determined based on the one or more instance parameters.

Abstract: Methods and systems perform a simulation on an integrated circuit design by applying a first value to a first variable and a second value to a second variable of the simulation to produce a first matrix corner simulation value. The methods and systems repeat the simulation using different values for the first and said second variables to produce a second matrix corner simulation value, a third matrix corner simulation value, and a fourth matrix corner simulation value. The methods and systems create a matrix, and the matrix has the first matrix corner simulation value, the second matrix corner simulation value, the third matrix corner simulation value, and the fourth matrix corner simulation value. The methods and systems interpolate all remaining values within the matrix based upon existing simulation values within the matrix.

Abstract: Methods, system and computer program products are disclosed for providing a graphical modeling environment in which a graphical model is generated and executed. In the graphical modeling environment, elements are provided to define or describe signals associated with resources that are coupled to the graphical modeling environment. The high-level signal definition or description elements define or describe the signals associated with the resources regardless of the hardware of the resources. With the use of high-level signal definition or description elements, the users have the capability to deal with the signals transmitted to/from the resources without the specific knowledge of the hardware of the resources.

Abstract: In one embodiment, a plurality of kernels are provided. Each kernel may simulate a partition of a design under test. A plurality of event regions are provided. The regions may be in an ordered priority. Events for the device under test may be determined for event regions in each of the kernels. An event region to execute events in is then determined and all kernels may execute events in the same event region. Kernels then execute events for the determined event region. When finished executing events in an event queue, data synchronization may occur. In this case, information may be synced among kernels, such as status and state values for shared objected are synchronized.

Abstract: An analysis apparatus for a printed circuit board. The analysis apparatus includes a processor that executes a process of rewriting physical property data of a wiring layer of a printed circuit board to a value. The value is based on physical property data of an electronic part having a heat-generating attribute. The electronic part is mounted on the portion of the wiring layer. The analysis apparatus converts the physical property data of the portion of the wiring layer that has the electronic part to physical property data of an insulating layer of the printed circuit board.

Abstract: In one embodiment, the invention is a method and apparatus for table-lookup-based models for yield analysis acceleration. One embodiment of a method for statistically evaluating a design of an integrated circuit includes simulating the integrated circuit and generating a lookup table for use in the simulating, the lookup table comprising one or more blocks that specify a device element for an associated bias voltage, wherein the generating comprises generating only those of the one or more blocks that specify the device element for a bias voltage that is required during the simulating.

Abstract: Techniques for monitoring and predicting environmental operating conditions in a data center are provided. In one aspect, a method for real-time, three-dimensional analysis of environmental operating conditions in a data center includes the following steps. High spatial resolution three-dimensional measurements of one or more environmental variables in the data center made at a time t1 are obtained. Real-time measurements of the environmental variables in the data center made at a time t2, wherein t2 is later in time than t1, are obtained. The high spatial resolution three-dimensional measurements are combined with the real-time measurements to derive a model for the environmental variables in the data center at the time t2. The model is used to predict three-dimensional distributions of the environmental variables in the data center at the time t2. A base model can be created and used to derive the model for the data center at the time t2.

Abstract: A web simulator includes a sensor database, an account database that stores access authorization table, an authentication processing unit that specifies access authorization of an access by reference to the access authorization table, a sensor registration and update unit that registers/updates sensor information in the sensor database in accordance with an instruction of access, and a simulation execution unit that executes simulation of a connection circuit in which a sensor indicated by the registered/updated sensor information and a semiconductor device having an analog front-end circuit are connected.

Abstract: A system, method and SPICE model evaluation module executable on a many-core processor. In one embodiment, the module includes: (1) a setup module operable to generate topology matrices T1 and T2, (2) a device evaluation/update module associated with the setup module and operable to generate and update source elements SA for a matrix A and Sb for a right-hand-side vector b and (3) a generation module associated with the device evaluation/update module and operable to generate A using T1 and SA and further generate b using T2 and Sb.

Abstract: A system, method, and computer program product are provided for creating a hardware design. In use, one or more parameters are received, where at least one of the parameters corresponds to an interface protocol. Additionally, a data flow is constructed based on the one or more parameters. Further, an indication of one or more control constructs is received, where a hardware design is capable of being created, utilizing the constructed data flow and the one or more control constructs.

Abstract: Aspects of the invention relate to techniques for modeling content-addressable memory for emulation. An emulation device according to various embodiments of the invention comprises one or more memory modeling blocks reconfigurable to emulate a content-addressable memory or a random-access memory. The emulation device may be processor-based or FPGA-based. Each of the one or more memory modeling blocks comprises memory circuitry and a dedicated comparison unit configured to compare a search word or a portion of a search word received by the each of the one or more memory modeling blocks with data stored in the memory circuitry. The comparison unit may comprise a comparator and a register coupled to the comparator and configured to store matching data. The matching data may be unencoded matching data. A plurality of the memory modeling blocks may be programmable to emulate a single content-addressable memory.

Abstract: Methods determine temperature and voltage relationships for integrated circuit library elements to produce a continuous temperature-voltage function. Some of the library elements can be used or combined to form an integrated circuit design. Further, the performance characteristics for integrated circuit chips produced according to the integrated circuit design can be defined, such performance characteristics include an operating temperature range, etc. The continuous temperature-voltage function is applied to the performance characteristics to determine a plurality of temperature/voltage combinations for the integrated circuit chips. Each of the temperature/voltage combinations comprises an operating voltage for each operating temperature within the operating temperature range of the integrated circuit chips. Next, the integrated circuit chips are produced according to the integrated circuit design. The temperature/voltage combinations are recorded in memory of the integrated circuit chips.

Abstract: An apparatus and method for detecting memory access violations in simulations is disclosed herein. A detection tool is designed to automatically perform a violation check for each memory read or write operation simulated in a modeled system. The detection tool is capable of handling a modeled system including one or more memories and/or one or more processors.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract: A non-transitory, computer-readable recording medium stores therein a verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition>the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in

Abstract: A computer-implemented method for verifying a model in a product lifecycle management (PLM) system includes defining a model and an envelope of allowable model states and, based on one or more requirements, deriving at least one counterexample objective. The method also includes optimizing a set of parameters related to the allowable model states and the allowable model context, redefining at least one of the model and the allowable model states when the at least one counterexample objective is outside of a specified tolerance, and, after a predefined number of iterations, defining the model as verified.

Abstract: Systems and methods for process aware metrology are provided. One method includes selecting nominal values and one or more different values of process parameters for one or more process steps used to form the structure on the wafer, simulating one or more characteristics of the structure that would be formed on the wafer using the nominal values, and determining parameterization of the optical model based on how the one or more characteristics of the structure vary between at least two of the nominal values and the one or more different values.

Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.

Abstract: One particular implementation takes the form of an apparatus or method for parallelizing a sequential power simulation of an integrated circuit device. The implementation may temporally divide the simulation so that separate time segments of the simulation can be run at the same time, thereby reducing he required time necessary to perform the power simulation. More particularly, a logic simulation may be performed on the integrated circuit and snapshots of the logic devices of the integrated circuit may be taken at a specified period. The separate time segments of the simulation may then be simulated in a parallel manner to simulate power consumption of the integrated circuit. Performing the power simulation on the separate time segments may reduce the required time of a typical power consumption simulation of an integrated circuit.

Abstract: Some embodiments include a method for identifying high-temperature regions in a microchip. In some embodiments, the method includes selecting grids on the microchip, wherein each grid includes devices and interconnects connecting the devices. The method can also include determining, for each grid, a temperature factor value based on geometric area of the grid, geometric area occupied by the devices, switching factor of the of the interconnects, and length of the interconnects connecting the devices. The method can also include determining, for each grid, thermal sensitivity for the grid by generating a plot based on a Guassian equation.

Abstract: Disclosed herein are methods and devices used for the physical design validation of integrated circuits. One method used for the physical design validation of integrated circuits includes comparing the original circuit netlist of an integrated circuit and the layout data of the integrated circuit and assigning labels to the input and output terminals of the components in the integrated circuit based on the results of the comparison.

Abstract: Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. The optimization can be performed iteratively, wherein in each iteration a gate optimization problem can be modeled for the portion of the circuit design based on circuit information for the portion of the circuit design. An objective function can be created, wherein the objective function includes at least one penalty function that imposes a lower and/or upper bound on at least one variable that is being optimized. In some embodiments, gradients of the objective function, which includes the penalty function, can be computed to enable the use of a conjugate-gradient-based numerical solver.

Abstract: A simulation apparatus performs a simulation of a program for executing a plurality of instructions included in an instruction set of a processor. A bus model unit accepts an access request to a memory storing the program, performs arbitration for a bus, and calculates a cycle count of the processor until use of the bus is granted, for each instruction of the program. A cycle count accumulation unit computes a cycle count required for executing the program based on the cycle count for each instruction calculated by the bus model unit.

Abstract: One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.