Abstract: A data backup system can be implemented in a data storage enclosure that houses a backup controller. The backup controller may be connected to a storage media and a backup media via a switch. The backup media can be resassigned from an unavailable condition to an available condition by the backup controller in response to predicted degradation in the storage media. The backup media may be connected to a root complex of the backup controller via a backup partition and selection feature.

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Abstract: Embodiments are described for performing an uninterrupted restore in a storage system in view of one or more abort events. A restore agent receives writes one or more data blocks to a conditional construction container. A parent interrupt service routine (ISR) polls for abort events. In response to an abort event, an intermediate interrupt is generated that spawns a child processes for each process of the restore. The intermediate ISR logs each child ISR, the process it is responsible for, and the intermediate interrupt, for later restoration of the restore state. After a recovery of the above event, then each child ISR can be called to restore its state. After restoring the state, the restore agent resumes the restore from where the abort event was detected. The child ISRs are re-entrant. If another abort event is detected, the restore state can again be saved and later resumed from that state.

Abstract: A data processing apparatus and method of data processing are provided which make use of a processor state check instruction to determine if the data processing apparatus is currently operating in a processor state, defined by at least one runtime processor state configuration value, which matches a processor state check value defined by the processor state check instruction. Dependent on the required runtime processor state configuration value(s) matching the processor state check value, the processor state check instruction is treated as an ineffective instruction. When the at least one runtime processor state configuration value does not match the processor state check value an exception is generated. Improved security of the data processing apparatus is thus provided.

Abstract: An apparatus and method are described for efficiently processing and reassigning interrupts. For example, one embodiment of an apparatus comprises: a plurality of cores; and an interrupt controller to group interrupts into a plurality of interrupt domains, each interrupt domain to have a set of one or more interrupts assigned thereto and to map the interrupts in the set to one or more of the plurality of cores.

Abstract: This disclosure describes performing a pre-activate check of reader nodes prior to deploying a new serialization format at writer nodes in a service provider network. Prior to activating a new serialization format on writer nodes, writer nodes query a metrics service within the service provider network for an aggregated serialization format version metric value for reader nodes, where the aggregated serialization format version metric value corresponds to a percentile of reader nodes that do not currently de-serialize objects using the newest deserialization format, e.g., the percentile of reader nodes that are not configured to recognize serialized objects serialized in the newest serialization format. The aggregated serialization format version metric values are based on a metric indicating the most recent serialization format version that a reader node is configured to de-serialize, which are emitted as reader nodes read serialized objects from a data store of the service provider network.

Abstract: An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. In addition, the bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.

Abstract: The present disclosure provides trusted kernel-based anti-attack data processors. One exemplary processor comprises: a trusted kernel exception vector table configured to provide a handling entry for kernel switching; a trusted kernel stack pointer register storing a trusted kernel stack pointer that points to a trusted kernel stack space; and a trusted zone in the trusted kernel stack space, the trusted zone including a program status register storing a flag bit of a starting kernel for the kernel switching, a program pointer, and a general register. When the data processor performs kernel switching from a non-trusted kernel to a trusted kernel, the trusted kernel locates the handling entry for the kernel switching and performs the switching. An underlying software protection mechanism can be provided for switching entries of a trusted kernel. Therefore, security during switching processes between a trusted kernel and a non-trusted kernel can be improved.

Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include switching mode logic to switch between the first mode and the second mode.

Abstract: Provided is a method and apparatus for implementing microkernel architecture of industrial server. The method includes calculation of dependency of control programs according to a microkernel task type weight and a microkernel task priority weight and/or a control program running time weight prior to startup of a system, and determination of the number of the control programs running on each physical core and each control program running on multiple physical cores according to the dependency.

Abstract: A device receives test parameters associated with testing an application that utilizes source data, and causes source containers, for the source data, to be temporarily created in a cloud computing environment, based on the test parameters. The device provides the source data to the source containers in the cloud computing environment, and causes other containers, for the application, to be temporarily created in the cloud computing environment, based on the test parameters. The device creates a file for testing the application with the source containers and the other containers, based on the test parameters, and causes the application to be executed with the source containers and the other containers, based on the file. The device receives results associated with executing the application with the source containers and the other containers.

Abstract: An apparatus for cache coherency between a device and a processor includes a buffer module that buffers data in a non-cache coherent space of an electronic device communicatively coupled to a processor. The apparatus includes an update module that updates at least one identifier with respect to the buffered data. The at least one identifier is stored in a cache coherent space of the electronic device. The apparatus includes a coherence notification module that notifies the processor of a cache incoherence. The cache incoherence indicates that the cache coherent space of the electronic device that includes the updated at least one identifier differs from a cache coherent space of the processor that includes a copy of the at least one identifier prior to the update.

Abstract: An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.

Abstract: The invention is a method and device for normalizing communication. The method includes receiving on a first device a first message via a first protocol from a second device; transmitting a second message to a third device via a second protocol, wherein the second message is transmitted using a first spreading factor; initiating a delay timer upon transmitting the second message, wherein a duration of the delay timer is based on a second spreading factor, wherein the second spreading factor is greater than or equal to the first spreading factor; receiving a third message from the third device via the second protocol, wherein the third message is transmitted using the first spreading factor, and wherein the third message is in response to the second message; and upon the expiration of the delay timer, sending a fourth message to the second device via the first protocol. The device includes the hardware and instructions to perform the method.

Abstract: Systems and methods related to memory paging and memory translation are disclosed. The systems may allow allocation of memory pages with increased diversity in the memory page sizes using page tables dimensioned in a manner that optimizes memory usage by the data structures of the page system.

Abstract: A compute node, a failure detection method thereof and a cloud data processing system are provided. The method is adapted to the cloud data processing system having a plurality of compute nodes and at least one management node, and includes following steps: performing a self-inspection on operating statuses of services being provided and resource usage statuses, and reporting an inspection result to the management node by each compute node; dynamically adjusting a time interval of a next report and informing the management node of the time interval by the compute node; and checking a report condition of the inspection result according to the time interval by the management node, so as to determine whether the compute node fails.

Abstract: Storage virtualization techniques allow directories to be stored remotely, for example, by a cloud storage provider, but in a manner that appears to a user or application running on a local computing device as if the directories are stored locally—even though the data of those directories may not be resident on the local computing device. That is, the contents of directories that may exist in the cloud look and behave as if they were stored locally on a computing device.

Abstract: Techniques and mechanisms for configuring services which variously facilitate data protection. In an embodiment, circuitry coupled to a memory comprises both a first circuit which calculates integrity information based on data, and a second circuit which evaluates data validity based on such integrity information. A configuration of the circuitry provides a combination of one or more services which is specific to a corresponding domain of the memory. With respect to accesses to the corresponding domain, the configuration prevents an access to the first circuit while an access to the second circuit is permitted. In another embodiment, a processor signals the circuitry to transition to another configuration which, with respect to accesses to the corresponding domain, permits access to both the first circuit and the second circuit.

Abstract: The present invention relates to a system for protecting a battery, and to a battery protecting system, which obtains state information of a battery through two different state obtaining units and diagnoses whether the battery has a problem based on the two elements of state information obtained through the two state obtaining units and reference state information, thereby more certainly diagnosing a state of the battery and stably protecting a load from the battery in the problem state.

Abstract: The present invention discloses a method for affinity binding of interrupt of a virtual network interface card, and a computer device. The method includes: receiving a request message sent by an IaaS resource management system, where the request message carries an interrupt affinity policy parameter of a virtual network interface card; performing one-to-one correspondence affinity binding between multiple virtual central processing units VCPUs and multiple physical central processing units PCPUs; performing affinity binding between a virtual interrupt of the virtual network interface card and a VCPU; and performing affinity binding between a physical interrupt of the virtual network interface card and a corresponding PCPU according to the affinity policy parameter.

Abstract: An apparatus includes a buffer, a sequencing circuit, and an execution unit. The buffer may be configured to store a plurality of instructions. Each of the plurality of instructions may be in a first thread. In response to determining that the first instruction depends on the value of a condition variable and to determining that a count value is below a predetermined threshold, the sequencing circuit may be configured to add a wait instruction before the first instruction. The execution unit may be configured to delay execution of the first instruction for an amount of time after executing the wait instruction. The sequencing circuit may be further configured to maintain the plurality of instructions in the first buffer after executing the wait instruction, and to decrement the count value in response to determining that the value of the condition variable is updated within the amount of time.

Abstract: Systems, methods, and other embodiments associated with handling secure interrupts between security zones are described. According to one embodiment, an apparatus includes a memory divided between a secure zone and a non-secure zone and storing a plurality of applications. The secure zone provides exclusive access to secure assets of the apparatus. A processor with an interface module configured to, in response to receiving an interrupt request from a requesting application that executes on the processor in the non-secure zone, tunnel the interrupt request into the secure zone of the processor. The non-secure zone and the secure zone are configured as operating environments of the processor with separate security controls. The processor includes a monitor module configured to issue the secure interrupt to a trusted application that is one of the plurality of applications in the secure zone, wherein the trusted application is registered to handle the secure interrupt.

Abstract: An electronic device includes a storage device including a plurality of doorbell registers; a host configured to perform a first interface operation with the storage device using a first command queue managed by a first doorbell register from among the plurality of doorbell registers; and a third-party device configured to perform a second interface operation with the storage device using a second command queue managed by a second doorbell register from among the plurality of doorbell registers, without an intervention of the host, wherein at least the second doorbell register is allocated as one of one or more dedicated registers for use only with operations of the third-party device.

Abstract: Systems and methods for speculative execution of commands using a controller memory buffer are disclosed. Non-Volatile Memory Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on a host device placing commands into the submission queue and thereafter notifying a memory device of the commands placed in the submission queue. The submission queue may be resident in the memory device, such as in the controller buffer memory. Prior to notice by the host device, the memory device may determine that the commands have been placed in the submission queue and may speculatively execute the commands. Determining whether to begin processing a command prior to the host device notifying the memory device that the command is posted to the submission queue may be based on a type of command, such as a read or write command. The host device may override a command, such as a flush command, posted to the submission queue, and processing of the command canceled.

Abstract: The present invention involves systems and methods for replacement of function calls. In one embodiment, a function call is intercepted and modified to enforce a policy on a client device. The function call is intercepted by scanning code loaded for a launch of an application. The function call includes a first pointer value. The function call is modified by changing a first pointer value to a second pointer value. The second pointer value points to a customized function.

Abstract: Dynamic binary instrumentation (DBI) or dynamic binary translation (DBT) of an examined process can be postponed until a point of interest is reached. Portions of the examined process can be run in native mode until the point of interest is reached. Upon reaching the point of interest, DBI and/or DBT can be performed.

Abstract: Methods of guaranteed reception and of processing of a digital signal in an avionics system comprise a plurality of computers, each computer comprising processing electronics and a software layer, which, on receipt of an event, carries out the following steps: at a first instant, sending to each of the other computers of a first signal (ACK) of reception of the event; at a second instant termed “TimeOut ACK”, if the electronic computer has not received one of the first signals emanating from one of the other computers, sending of a second failure signal (FAIL) to each of the other computers; at a third instant termed “TimeOut GARANTEED”, if a second failure signal has been received by the computer, absence of taking into account of the event by the computer and if no failure signal has been received by the computer, taking into account of the event by the data processing electronics of the computer.

Abstract: Methods and system are disclosed that generate an execution schedule to optimize a transformation of business. In one aspect, from multiple tables residing in multiple databases and storing business data associate with multiple business management systems, dependencies between the tables may be determined based on attributes associated with the tables. When execution time for transforming business data exists, a decrease time algorithm or a critical path algorithm may be executed to generate execution schedule and to calculate processor idle times during the transformation of business data. Based on the calculated processor idle times, whether or not to execute a local optimization algorithm may be determined. Based on the determination, execution schedule that optimize the transformation of business data may be generated. The transformation of business data may be executed based to the generated execution schedule that optimizes a time consumed for transforming the business data in the tables.

Abstract: Embodiments of the present disclosure provide a system, a computer program product and a method for detecting and handling errors in a bus structure by obtaining error information from a plurality of hardware registers associated with a bus; in response to determining that a number of the errors in one or more hardware registers of the plurality of hardware registers exceeds a predetermined threshold, detecting performance of hardware devices corresponding to the one or more hardware registers; and in response to determining performance deterioration of one hardware device in the hardware devices corresponding to the one or more hardware registers, determining that an error occurs in the hardware device.

Abstract: A method comprises receiving a non-privileged disable interrupts instruction from a user application executing in user space, the non-privileged disable interrupts instruction having an operand with a non-zero value; determining a value in a special purpose register associated with disabling interrupts; and in response to determining that the value in the special purpose register associated with disabling interrupts is zero, disabling interrupts and placing the non-zero value of the operand in the special purpose register associated with disabling interrupts.

Abstract: Embodiments of the present disclosure relate to a method and a device of managing input/output of a storage device. The storage device at least includes a first I/O port and a second I/O port. The method comprises receiving a first I/O request for the storage device, and determining a type of the first I/O request. Based on the type of the first I/O request, the first I/O request is dispatched to the first I/O port or the second I/O port. If the first I/O request is a read request, the first I/O request may be dispatched to the first I/O port, and if the first I/O request is determined as a write request, the first I/O request may be dispatched to the second I/O port. The method may reuse at least one of the first I/O port or the second I/O port.

Abstract: Systems, methods, and computer program products to perform an operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt, and responsive to the lightweight HDEC interrupt, initiating an asynchronous hardware operation on the shared processor prior to completion of the dispatch cycle.

Abstract: The invention relates to a device for integrating software components of a distributed real-time software system, said components being run on target hardware and on a development system, wherein the target hardware comprises computing nodes, and the development system comprises one or more computers. The device is designed as an expanded development system in which the computing nodes of the target hardware are connected to the computers of the development system via one or more time-controlled distributor units, wherein the expanded development system has a sparse global time of known precision, and wherein the computing nodes of the target hardware are connected to the computers of the development system via the one or more time-controlled distributor units such that the data content of a TT message template of a TT platform of the target hardware can be provided both by a simulation process of the development system as well as by an operative process of the target hardware in a timely manner.

Abstract: Apparatuses, systems and methods associated microprocessor segment registers are disclosed herein. More particularly, the present disclosure relates to providing an auxiliary segment register(s) and/or auxiliary segment descriptor table(s), and various ways for their use, for example, providing new instructions for their access, or remapping existing processor resources. A machine might provide isolated execution regions and/or protected memory by associating or exclusively reserving some or all of the auxiliary segment register(s)/table(s) with a specific task, program, instruction sequence, etc. In some embodiments, such as in Internet of Things (IoT) or wearable devices, auxiliary resources may be employed to isolate mutually-distrustful code regions to facilitate engaging unknown devices. Other embodiments are also described and/or claimed.

Abstract: The invention provides for a method for running a computer network and such a computer network. The computer network comprises a number of devices being arranged in a stable daisy-chained loop, wherein each device comprises a bridge having at least three ports, whereby during running the computer network each device can take different states to avoid a loop, and whereby in case of rebooting the ports of at least one of the devices keep their current port states.

Abstract: Embodiments of the disclosed subject matter include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits, and other electronic components having, for example, different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. The interface utilizes request and acknowledge phases and signals and an initiator-target relationship between components that allow each side to throttle the communication rate to an accepted level for each component or achieve a desired bit error rate. Other devices, methods, and interfaces are disclosed.

Abstract: In an embodiment, a system includes a processor and a non-volatile storage device. The non-volatile storage device may include a stored firmware program and a firmware loader. The firmware loader may be executable by the processor to read a first instruction of the stored firmware program; and generate, based on the first instruction, a set of runtime instructions to be included in a runtime firmware program, where the stored firmware program and the runtime firmware program are composed in a same programming language. Other embodiments are described and claimed.

Abstract: A method, system, and computer program product for IO leveling comprising receiving an IO, determining if there is a delay for processing IO because of pending IO, based on a positive determination there is a delay for processing IO, determining a priority for the IO, and based on the priority of IO determining whether to process the IO.

Abstract: The invention relates to a method for debugging software components of a distributed real-time software system, wherein the target hardware comprises computer nodes and the development system comprises one or more computers.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract: Register restoration or register reloading is selected. A restoration request to restore a plurality of architected registers is obtained. A determination is made as to whether a snapshot associated with the plurality of architected registers is valid. The snapshot provides in-core values for the plurality of architected registers. Based on the snapshot being valid, a determination is made as to whether the snapshot is to be used to recover an individual architected register of the plurality of architected registers. Based on determining the snapshot is to be used, the snapshot is used to recover the individual architected register. Based on determining the snapshot is not to be used, memory is used to recover the individual architected register.

Abstract: The present disclosure discloses a processor security checking method, system and checking device. The processor security checking method includes: acquiring recording information of data read and write operations between a processor and a peripheral device, where the data read and write operation is a data read and write operation initiated by the processor or a data read and write operation initiated by the peripheral; and determining whether the processor is secure according to the recording information of the data read and write operation and an analysis result on the data read and write operation by the checking device. The embodiments of the present disclosure may detect hardware vulnerabilities and improve the security of hardware usage.

Abstract: Embodiments of the invention are directed to computer-implemented methods, computer systems, and computer program products for testing hardware. The method includes reading a stream of test instructions. The method further includes determining if test instruction exceptions present in the stream of test instructions. The method further includes inserting an interrupt into the test instruction stream for each determined test instruction exception. The method further includes generating one or more error messages for each determined test instruction exception.

Abstract: Embodiments of the invention are directed to computer-implemented methods, computer systems, and computer program products for testing hardware. The method includes reading a stream of test instructions. The method further includes determining if test instruction exceptions present in the stream of test instructions. The method further includes inserting an interrupt into the test instruction stream for each determined test instruction exception. The method further includes generating one or more error messages for each determined test instruction exception.

Abstract: A method includes performing operations to swap a system from a first userspace to a third userspace. Operations of the method include: operating the system using the first userspace, loading a second userspace into an operating system memory space accessible to a kernel, and installing a custom init replacement. Operations of the method further include signaling an init system to execute the custom init replacement, thereby operating the system using a second userspace, loading the third userspace into a second memory location accessible to the kernel, and signaling the init system to execute the custom init replacement a second time, thereby operating the system using the third userspace.

Abstract: Techniques for monitoring based on a memory layout of an application are disclosed. A memory layout may be received, obtained, and/or generated from an application executing on a computer. Based on one or more attributes of a plurality of memory regions of the memory layout a memory layout fingerprint is generated. Additionally, memory region fingerprints are generated based on the one or more attributes for respective memory regions. The memory layout fingerprint and the memory region fingerprints are compared to respective previous memory layout fingerprints and the memory region fingerprints in order to determine whether malicious code and/or application drifting has occurred.

Abstract: Technologies for optimization of a memory controller include a computing device having a memory manager, a memory trainer, and a platform firmware. The memory manager reserves a space in memory of the computing device that is inaccessible to an operating system of the computing device. The memory trainer utilizes the reserved space to perform a memory training to determine configuration settings of the memory controller. After the configuration settings of the memory controller have been determined, the platform firmware configures the memory controller with the determined configuration settings.

Abstract: A network interface device includes an interface configured to receive data packets for a host processing device and an engine supporting a network interface device component of an application that is provided on the host processing device. In response to receiving data packets for the application, the engine is configured to cause at least some of the data packets to be available to the component of the application, to cause the data packets to be delivered to a protocol stack of the host processing device, and to receive control information associated the data packets from the protocol stack of the host processing device. The interface is configured to output an acknowledgement message comprising the control information.

Abstract: In an embodiment, processors may have associated special purpose registers (SPRs) such as model specific registers (MSRs), used to communicate IPIs between the processors. In an embodiment, several types of IPIs may be defined, such as one or more of an immediate type, a deferred type, a retract type, and/or a non-waking type. The immediate IPI may be delivered and may cause the target processor to interrupt in response to receipt of the IPI. The deferred IPI may be delivered within a defined time limit, and not necessarily on receipt by the target processor. The retract IPI may cause a previously transmitted IPI to be cancelled (if it has not already caused the target processor to interrupt). A non-waking IPI may not cause the target processor to wake if it is asleep, but may be delivered when the target processor is awakened for another reason.

Abstract: A method for preventing battery from expanding is applied to awake an embedded controller to measure variations of a temperature and a storage capacity of a battery module of an electric device at a preset frequency to timely control the battery module to discharge when the electric device is in an off-state, so as to prevent the battery module from expanding and deforming.