Abstract: A mechanism is described for facilitating callback interrupt handling for multi-threaded applications in computing environments. A method of embodiments, as described herein, includes detecting a task issued by a thread associated with an application processor, where the task is to be processed by a graphics processor at the apparatus. The method may further include scheduling the task at the graphics processor, and emulating an interrupt to the application processor, where the emulated interrupt disables one or more graphics interrupts while the task is being processed by the graphics processor. The method may further include facilitating an interrupt handler to communicate a signal to the application processor to wake up the thread, where the thread is facilitated to perform one or more tasks independent of the task being processed by the graphics processor.

Abstract: Apparatus and a corresponding method for processing received datagram fragments are provided. Fragments are considered in fragments lists, which comprise a linked list of fragments. The fragments lists are referenced by corresponding entries stored in fragment list storage, where all received fragments from a given datagram will form part of the same fragment list, but a given fragment list can comprise fragments from multiple datagrams. An accumulated size of the payloads for a linked list of fragments is maintained and allows a determination to be made of whether it appears that sufficient fragments have been received that reassembly of a datagram may be possible. Access to a selected fragment list entry is made atomically, wherein the existing entry is first read and then if a datagram reassembly is to be attempted a write access sets the selected fragment list entry to a null entry before that datagram reassembly is attempted.

Abstract: Systems, methods, and computer readable medium are provided that improve the management of interrupt requests in multiple processor computer systems. Interrupt requests can be classified into three categories and the structure of the categories provide for specifying a list that needs to be migrated. The list can contain only those interrupt requests that can be handled by some of the processors that will never unplug or based on affinity. When a processor is about to unplug, the computer system can migrate that list. The system can also manage the other interrupt requests.

Abstract: Method and system for writing a history buffer in a processing unit is provided. At least a first instruction and a second instruction are dispatched in a single processing cycle, targeting a same register file entry. The processing unit includes two or more processing slices, each processing slice comprising a corresponding history buffer and at least a portion of a register file. Upon determining that first result data corresponding to the first instruction is older than second result data corresponding to the second instruction, the first result data is written into a history buffer bypassing the register file entry, in response to the determination. Further, the second result data is written into the register file entry.

Abstract: A system is described that comprises: a master device and a slave device. The slave device comprises: a first die comprising an interface comprising a decoder configured to support a MIPI™ RFFE slave protocol; at least one second die comprising a simplified address decoder, operably coupled to the first die; and a shared control bus that is configured to support at least a clock signal and a data signal shared between the master device and the at least one second die on the slave device. The interface of the first die is configured to generate at least one circuit enable signal, routed to the at least one second die. The simplified address decoder is configured to process the clock signal and the data signal in response to the at least one circuit enable signal.

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

Abstract: An electronic device includes a plurality of processes, an interrupt waiting unit for each of the processes, and an interrupt handler. The interrupt handler processes the interrupt. The interrupt waiting unit sets an interrupt waiting flag to wait for an occurrence of the interrupt. The interrupt handler, when the interrupt occurred, sets an interrupt style of the occurred interrupt and releases the interrupt waiting flag from the set state. The interrupt waiting unit, when the interrupt waiting flag was released from the set state, sets the interrupt waiting flag if the interrupt style set by the interrupt handler is not an interrupt style matched with the process, and operates the process if the interrupt style set by the interrupt hander is the interrupt style matched with the one of the processes. The interrupt waiting flag is located to each of the processes.

Abstract: Systems and methods for sharing message-signaled interrupt vectors in multi-processor computer systems. An example method may comprise: associating an interrupt vector with a first device component; associating the interrupt vector with the second device component; creating, in a first interrupt descriptor table (IDT) associated with a first processor, a first interrupt descriptor to reference a first interrupt service routine to process a first interrupt triggered by the first device component; and creating, in a second IDT associated with a second processor, a second interrupt descriptor to reference a second interrupt service routine to process a second interrupt triggered by the second device component, wherein the first interrupt descriptor and the second interrupt descriptor reference the interrupt vector.

Abstract: Methods, devices, and non-transitory processor-readable storage media for a computing device to merge concurrent writes from a plurality of processing units to a buffer associated with an application. An embodiment method executed by a processor may include identifying a plurality of concurrent requests to access the buffer that are sparse, disjoint, and write-only, configuring a write-set for each of the plurality of processing units, executing the plurality of concurrent requests to access the buffer using the write-sets, determining whether each of the plurality of concurrent requests to access the buffer is complete, obtaining a buffer index and data via the write-set of each of the plurality of processing units, and writing to the buffer using the received buffer index and data via the write-set of each of the plurality of processing units in response to determining that each of the plurality of concurrent requests to access the buffer is complete.

Abstract: The disclosed embodiments provide a system that operates a processor in a computer system. During operation, the system uses the processor to maintain a count of outstanding input/output (I/O) requests for a component in the computer system. Next, the system facilitates efficient execution of the processor by overriding a latency tolerance reporting (LTR) value for the component based on the count.

Abstract: The invention provides a processing system, comprising a memory comprising a processor call stack; a stack space usage register configured to determine the stack space usage of the processor call stack and to store a usage parameter indicative of the determined stack space usage; a first threshold register configured to store a pre-determinable first stack level threshold; and a first comparator configured to compare the usage parameter with the first stack level threshold and to output a first interrupt blocking signal, if the usage parameter exceeds the first stack level threshold, the first interrupt blocking signal being configured to block the decoding of interrupt signals input to the processing system and having interrupt priorities lower than or equal to or just lower than a first interrupt priority threshold. The invention further provides a method for stack management, especially in a processing system.

Abstract: An information processing device includes a processor; and a control device coupled to the processor and configured to receive a packet, determine whether a mask for an interrupt is set, when the received packet is an error message for notifying occurrence of an error in communication between the processor and any of one or more other devices, transmit the interrupt to the processor, when determining that the mask for the interrupt is not set, inhibit transmitting of the interrupt to the processor, when determining that the mask for the interrupt is set; and one or more counter circuits respectively configured to count a number of the error message received while the mask for the interrupt is set, and transmit a value of the number of the error message to the processor in accordance with an instruction from the processor.

Abstract: An information processing device includes an interrupt information output request part configured to detect an input of interrupt information, which is information newly output with an output part and which includes a plurality of contents, when output information is being output with the output part. An output controller restricts the scope of the interrupt information being output with the output part based on the type of the output information. Thus, the information processing device is able to switch an operation as to whether or not to output personal information such as an incoming notice with the output part.

Abstract: A method for implementing a packet I/O engine on a programmable computing platform is provided, where the engine performs I/O functions for plural threads generated by a plurality of user applications. In the method, the platform is configured such that only one thread is permitted to initialize and configure the resources. Furthermore, I/O-device queues each for buffering packets either transmitted to or received from an individual external I/O device are set up. For a plurality of unsafe I/O-device queues determined, among the I/O-device queues, to be multi-thread unsafe, a plurality of multi-producer, multi-consumer software queues for buffering packets delivered between the plurality of the unsafe I/O-device queues and the plurality of user applications is set up.

Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

Abstract: A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.

Abstract: In an asymmetric multi-CPU system on which a plurality of type of CPUs with different data processing performance and power consumption are mounted in groups for each type, a plurality of forms of combination of the types and numbers of CPUs are defined in such a way that the maximum numbers of the overall data processing and power consumption very by stages. Then, the system performs a control of allocation of the data processing to the CPU identified by the form selected from the definition information according to the data processing environment, in order to reduce unnecessary power consumption according to the data processing environment, such as data processing load, and to easily achieve the required data processing performance.

Abstract: A method and apparatus for scanning files, wherein the method comprises: during the traversing of a directory, performing first processing on the traversed directory, the first processing comprising: acquiring a directory attribute of the traversed directory, and determining whether the traversed directory is a remapped directory according to the acquired directory attribute, and if so, performing no scanning processing on the traversed directory, and if not, performing scanning processing on the traversed directory, with the scanning processing comprising: scanning various files in the traversed directory to acquire a scanning result, and/or, performing second processing on various sub-directories in the traversed directory; and the second processing comprises: traversing the various sub-directories, and performing the same processing as the first processing on the traversed sub-directories.

Abstract: A mapping technique sets coalescing latency values for computing systems that use multiple data queues having a shared base timer. A computing system having at least one receive queue and at least one transmit queue receives user-provided coalescing latency values for the respective queues, and converts these user-provided latencies to coalescing latency hardware register values as well as a base timer register value for the shared base timer. The hardware register values for the coalescing latencies together with the shared base timer register value determine the coalescing latencies for the respective queues. This mapping technique allows a user to conveniently set coalescing latencies for multi-queue processing systems while shielding the user settings from hardware complexity.

Abstract: A system having master and slave devices and communicating over an I2C bus has SDA and a SCL lines that are normally high unless a device pulls the voltage of the line Low. Normal data signals on the SDA line are set during the low phase of the clock signals on the SCL line and transferred to a receiver during the high phase of the clock signals. A slave device provides an alert signal on the SDA line during the low phase of the clock signals to send an alert signal to the master device. The alert signal may be a pulse signaling the slave device wakeup or a pulse pattern identifying the alerting slave device.

Abstract: The present invention relates to aSoC, which includes a master device, a slave device, a high-speed bus, and a monitoring apparatus. The master device is connected to a first port of the high-speed bus, and the slave device is connected to a second port of the high-speed bus, so that the master device is capable of accessing the slave device. The monitoring apparatus is arranged between the first port of the high-speed bus and the master device, and/or between the second port of the high-speed bus and the slave device, and configured to record, based on a high-speed bus communication protocol, state information of each command that passes through the first port and/or the second port, and when state information of a command indicates that an operation of the command is in a timeout state, report an interrupt to locate a faulty node on the high-speed bus.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

Abstract: A supervisory hardware device in a processor core detects a flush instruction that, when executed, flushes content of one or more general purpose registers (GPRs) within the processor core. The content of the one or more GPRs is moved to a history buffer (HB) and an instruction sequencing queue (ISQ) within the processor core, where the content includes data, an instruction tag (iTag) that identifies an instruction that generated the data, and error correction code (ECC) bits for the data. In response to receiving a restore instruction, the supervisory hardware device error checks the data in the ISQ using the ECC bits stored in the ISQ. In response to detecting an error in the data in the ISQ, the supervisory hardware device sends the data and the ECC bits from the ISQ to an ECC scrubber to generate corrected data, which is restored into the one or more GPRs.

Abstract: Low Latency Interconnect Integrated Event Handling has been disclosed. In one implementation a hardware based interrupt controller coupled with a hardware based event queue manager, dedicated hardware based queues, and processor instruction extensions allows for off-loading event processing from an operating system thereby dramatically lowering wasted processor cycles while speeding up event processing.

Abstract: A tuning engine for a virtualized computing system is described that periodically collect performance metrics from the virtualized computing system, and detects whether a change in system state has occurred based on the collected metrics. The tuning engine may determine whether the virtualized computing system is densely virtualized, and accordingly modify operations and configuration settings of various components in charge of handling networking for the virtualized computing system.

Abstract: Generally, this disclosure describes systems (and methods) of moderating interrupts in a virtualization environment. An overflow interval is defined. The overflow interrupt interval is used to trigger activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

Abstract: A method comprising is described. The method includes receiving an interrupt targeting a virtual processor, determining a status of the virtual processor and directly delivering the interrupt to the virtual processor upon determining that the virtual processor is operating in a running state.

Abstract: A technique for handling interrupts in a data processing system includes maintaining, at an interrupt presentation controller (IPC), an interrupt acknowledge count (IAC). The IAC provides an indication of a number of times a virtual processor thread implemented at a first software stack level has been interrupted in response to receipt of event notification messages (ENMs) from an interrupt source controller (ISC). In response to the IAC reaching a threshold level, the IPC transmits an escalate message to the ISC. The escalate message includes an escalate event number that is used by the ISC to generate a new ENM that targets a second software stack level that is different than the first software stack level and is associated with another virtual processor thread.

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Abstract: Storage system and application intercommunication is provided. A first kernel-mode module determines a first event corresponding to an operational parameter of a first node based, at least in part, on a shared namespace accessible by the first kernel-mode module and a second kernel-mode module. An interrupt is issued based on the first event from the first kernel-mode module to the second kernel-mode module via an interface. The second kernel-mode module issues a second event to a second node, wherein the second event corresponds to the object of the shared namespace.

Abstract: A method of handling interrupts includes receiving an event notification message (ENM) that specifies a level, an event target number (ETN), and a number of bits to ignore. A group of virtual processor threads that may be potentially interrupted are determined based on the ETN, the number of bits to ignore, and a process identifier when the level specified in the ENM corresponds to a user level. The ETN identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore when determining a group of virtual processor threads that may be potentially interrupted. In response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, an escalate message that includes an escalate event number is transmitted. The escalate event number is used to generate a subsequent ENM.

Abstract: A novel hash range lookup command is disclosed. In an exemplary embodiment, a method includes (a) providing access to a hash table that includes hash buckets having hash entry fields; (b) receiving a novel hash lookup command; (c) using the hash lookup command to determine hash command parameters, a hashed index value, and a flow key value; (d) using the hash command parameters and the hashed index value to generate hash values (addresses) to access entry fields in a selectable number of hash buckets; (e) comparing bits of the entry value in the entry field to bits of the flow key value; (f) repeating (d) through (e) until a match is determined or until the selectable number of hash buckets and entries have been accessed; and (g) returning either an address of the entry field containing the match or a result associated with the entry field containing the match.

Abstract: An apparatus including: an input interface configured to enable user configuration of a future time window; and a report interface configured to produce a report relating to a first sub-set of a plurality of active timers that expire at programmed future points in time, wherein the first sub-set of the plurality of active timers expire during the user-configured future time window.

Abstract: Information processing device includes: a first storage unit for storing processing information indicative of predetermined processing and for sequentially outputting the stored processing information; a second storage unit for storing the processing information; a request management unit operative to receive and to store the received processing information in the first storage unit when available, and to store the received processing information in the second storage unit when the first storage unit is unavailable; a request acquisition unit operative to sequentially acquire the processing information output by the first storage unit when the processing information is present in the first storage unit, and search the second storage unit so as to detect and acquire the processing information when the processing information is absent in the first storage unit; and a processing execution unit to perform the predetermined processing according to the acquired processing information.

Abstract: A sensor data collecting device includes a first circuit and a controller. The controller has a first state and a second state and acquires data of one or a plurality of sensors in the second state. The first circuit includes a first register and causes the controller to transit from the first state to the second state. The controller sets the first register based on a minimal data generation period among data generation periods.

Abstract: A method and system for permitting a guest to program a message-signaled interrupt-based device is disclosed. A hypervisor of a host detects a request by a guest to map an address range of memory of the guest to a message signaled-interrupt capability table associated with a device. The hypervisor maps the message signaled-interrupt capability table from a message signaled-interrupt capability register of a programmable interrupt controller associated with the host to the address range of memory of the guest. The hypervisor detects an attempt by the guest to program the device with the message-signaled interrupt configuration located in the address range of memory of the guest. The hypervisor programs the device with the message-signaled interrupt configuration specified by the guest in the address range of memory of the guest.

Abstract: System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step, applicant's invention significantly enhances the efficiency of the conversion process. In one embodiment, a file system or storage system provides indirections to locations of data elements stored on a persistent storage media. A source virtual machine file includes hypervisor metadata (HM) data elements in one hypervisor file format, and virtual machine payload (VMP) data elements.

Abstract: A method for bridging between virtual applications and an operating system of a host computer. The method comprises retrieving virtual applications and settings of the virtual applications assigned to a user logged onto the host computer, wherein each of the virtual applications includes the following files: a virtual engine, a user data file, and an application-on-demand (AOD) file; downloading shadow files of the virtual applications assigned to the user; integrating each of the virtual applications with an operating system shell of the host computer; and causing a virtual application to be executed over the host computer when the virtual application is launched by the user.

Abstract: A collaboration environment provides a generic event distributing framework that can distribute both synchronous and asynchronous events. The distributed events may be pre-defined or dynamically defined. Further, the framework can support multiple data formats for the event payload. The collaboration environment relies on two separate APIs to separate event producers from event consumers.

Abstract: Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In one embodiment, a method for activating one or more processors comprises reducing a frequency of a clock signal from a first clock frequency to a second clock frequency, wherein the clock signal is output to a plurality of processors including the one or more processors. The method also comprises activating the one or more processors after the frequency of the clock signal is reduced, and increasing the clock signal from the second clock frequency to the first clock frequency after the one or more processors are activated.

Abstract: An instruction sequencing unit in an out-of-order (OOO) processor includes a Most Favored Instruction (MFI) mechanism that designates an instruction as an MFI. The processing queues in the processor identify when they contain the MFI, and assures processing the MFI. The MFI remains the MFI until it is completed or is flushed, and which time the MFI mechanism selects the next MFI.

Abstract: An electronic computer includes a processor that executes a thread and an interrupt handler, and monitors load of the processor; and an interrupt controller that is configured to determine a notification timing for an interrupt request to call the interrupt handler, the notification timing being determined based on the load and an effect of execution of the interrupt handler on user performance of the thread under execution by the processor; and notify the processor of the interrupt request, based on the notification timing. When the load is higher than a threshold, the interrupt controller sets the notification timing for an interrupt request that does not affect the user performance, to be later than the notification timing for an interrupt request that affects the user performance. Based on notification of the interrupt request, the processor calls and executes the interrupt handler that corresponds to the interrupt request.

Abstract: A system and method are described for conveying to a user the value it would receive by implementing an integrated system to protect and manage its data. An integrated system can combine archiving, backup, snapshot management, reporting, secure data access, eDiscovery and data analytics, among other functions, thus simplifying data protection and data management for an organization. The system generates a value dashboard, exhibiting value data, including data and graphics portraying the benefits to a user of implementing an integrated data management and protection system. Value may be evaluated with reference to simplification and efficiency, risk reduction, and unlocking data value.

Abstract: An information processing apparatus capable of notifying a user of a state of data transmission via short-range wireless communication. An NFC tag controller of an MFP as an information processing apparatus holds communication setting information for wireless LAN communication, and transmits the communication setting information to a mobile terminal as an external apparatus, via NFC communication by dividing the information. An interrupt signal generated by the NFC tag controller for notifying completion of transmission of a divided information item to the mobile terminal is detected, and when the number of times of detection of the interrupt signal reaches a predetermined number of times, the user is notified that the transmission of the communication setting information is completed.

Abstract: Techniques for conditional name resolution and configuration are provided. Calls made by applications to resolve hostnames through name resolution services are intercepted and processed unbeknownst to the applications. The calls are inspected for hostnames and the hostnames are lookup in a policy store for IP addresses. The IP addresses are supplied back to the applications as if IP addresses were provided by the name resolution services.

Abstract: A method and apparatus are used for detecting a radio link (RL) failure and a post verification process. A quality of a downlink fractional dedicated physical channel (F-DPCH) is monitored once a transmission on an enhanced dedicated channel (E-DCH) has begun. It is determined whether the quality of the downlink F-DPCH is below a predefined threshold. If the quality is below the predefined threshold, then an occurrence of an RL failure is declared and a transmission over the E-DCH in a cell forward access channel (CELL_FACH) state is terminated. In a case of the post verification failure, E-DCH resources are released.

Abstract: Example embodiments disclosed herein relate to distributing information. A set of information about components of a computing device is retrieved from a low-level system of the computing device. Programs are determined to be sent data based on the set of information.

Abstract: A system and method including: determining, by a manager module, a need to determine a primary software component of a client device; identifying a first software component and a second software component of the client device; identifying a set of characteristics of the first software component and the second software component; determining that the first software component is the primary software component based on the set of characteristics of each software component, where determining the primary software component further includes comparing the set of characteristics of each software component and selecting the primary software component based on the set of characteristics with a highest priority; and instructing, by the manager module, the one or more processors to cause functionality associated with the second software component to be at least partially suspended.