Abstract: A system and method dynamically assign interrupts to a virtual machine from an input/output (I/O) adapter based on I/O metrics of the I/O adapter. An interrupt manager monitors I/O adapter traffic flow metrics such as latency of data transfers, usage levels, and transfers per unit of time. The interrupt manager determines when a traffic flow metric for a virtual machine meets a predetermined performance threshold and updates virtual interrupt assignments in a logical interrupt table to improve performance of the system.

Abstract: An electronic device includes a universal serial bus (USB) port configured to be wiredly attached to an external audio device, a processor operatively connected to the USB port, and a memory operatively connected to the processor. The memory stores a media application to play audio data, and stores instructions that when executed, cause the processor to play the audio data through the media application, sense an event associated with detachment from the external audio device while the audio data is being played, pause playing the audio data, in response to that the event is sensed, identify whether a device the same as the external audio device is attached within a specified time after the event is sensed, and play the audio data, which is paused, through the media application, when the device the same as the external audio device is attached within the specified time.

Abstract: An electronic device configures the electronic device to operate in a first mode, when the current time is with a first scheduled sleep time period, and user input selecting an affordance using a first input mechanism is disabled in the first mode. While in the first mode, detecting first user input. The electronic device transitions the electronic device into a second mode different from the first mode if the first user input meets predefined criteria, and remains in the first mode and forgoes transitioning to the second mode if the first user input does not meet the predefined criteria.

Abstract: Interrupt messages are sent from an interrupt controller to respective processor cores and data synchronization is managed among the processor cores. Each processor core includes a pipeline that includes a plurality of stages through which instructions of a program are executed, where stored order information indicates whether a state of the pipeline is in-order or out-of-order; and circuitry for receiving interrupt messages from the interrupt controller and performing an interrupt action in response to a corresponding interrupt message after ensuring that the order information indicates that the state of the pipeline is in-order when each interrupt action is performed. Managing the data synchronization includes generating a first interrupt message at an issuing processor core in response to a synchronization related instruction executed at the issuing processor core; and receiving the first interrupt message at each receiving processor core in a set of one or more receiving processor cores.

Abstract: An application processor includes a system bus, as well as a host processor, a voice trigger system, and an audio subsystem that are electrically connected to the system bus. The voice trigger system performs a voice trigger operation and issues a trigger event based on a trigger input signal that is provided through a trigger interface. The audio subsystem processes audio streams that are replayed or recorded through an audio interface, and receives an interrupt signal through the audio interface while an audio replay operation is performed through the audio interface.

Abstract: In one embodiment, an apparatus includes an interconnect to couple a plurality of processing circuits. The interconnect may include a pipe stage circuit coupled between a first processing circuit and a second processing circuit. This pipe stage circuit may include: a pipe stage component having a first input to receive a signal via the interconnect and a first output to output the signal; and a selection circuit having a first input to receive the signal from the first output of the pipe stage component and a second input to receive the signal via a bypass path, where the selection circuit is dynamically controllable to output the signal received from the first output of the pipe stage component or the signal received via the bypass path. Other embodiments are described and claimed.

Abstract: An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus and a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using a mapping table comprised by the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Abstract: The present invention discloses an interrupt controller, including: a sampling unit adapted to receive interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts; and a priority arbitration unit adapted to classify the received various interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, segment by segment an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as an to-be-responded-to interrupt. The present invention further discloses a processor including the interrupt controller, and a system-on-chip.

Abstract: Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may process a sequence of Graphics Processing Unit (GPU) commands including an instruction carrying a flag that indicates a workload characteristic corresponding with the sequence of GPU commands. The second circuitry may initiate a power-directed parameter adjustment based upon the flag.

Abstract: A method for operating an apparatus that includes a program memory, a data memory and a status register that holds a status, wherein the status has fields including: a program memory address at which a most recent instruction is fetched from the program memory, a data memory access address at which data has most recently been accessed in the data memory by the apparatus and a repeat count indicating a number of times an operation specified in a current program instruction remains to be performed, the apparatus further including a condition register having condition fields corresponding to the status fields held in the status register, the method including: writing the condition register with a condition including the condition fields; and generating an interrupt request to a processing core in response to detecting that the status held in the status register satisfies the condition specified in the condition register.

Abstract: A programmable apparatus includes a program memory that holds instructions of a program fetched and executed by the apparatus, a data memory that holds data processed by the instructions, a status register that holds a status having fields: a program memory address at which a most recent instruction is fetched from the program memory, a data memory access address at which data has most recently been accessed in the data memory by the apparatus and a repeat count that indicates a number of times an operation specified in a current program instruction remains to be performed. A condition register has condition fields corresponding to the status register fields. Control logic generates an interrupt request to a processing core in response to detecting that the status held in the status register satisfies the condition specified in the condition register.

Abstract: Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

Abstract: A system and method dynamically assign interrupts to a virtual machine from an input/output (I/O) adapter based on I/O metrics of the I/O adapter. An interrupt manager monitors I/O adapter traffic flow metrics such as latency of data transfers, usage levels, and transfers per unit of time. The interrupt manager determines when a traffic flow metric for a virtual machine meets a predetermined performance threshold and updates virtual interrupt assignments in a logical interrupt table to improve performance of the system.

Abstract: An interrupt control device between clock domains is provided. An interrupt sharing logic is configured to receive one or more original interrupt signals and generate a combined interrupt signal. An interrupt processing logic is configured to output a processed interrupt signal to a processor according to the combined interrupt signal, so that the processor executes an interrupt service routine. When the interrupt service routine is executed, the processed interrupt signal changes to be disabled; before the interrupt service routine is completed, the processor outputs an interrupt clear signal to change the respective interrupt signal to be negated. After the interrupt processing logic detects that interrupt signal has been cleared successfully, the interrupt processing logic will generate the processed interrupt signal according to the combined interrupt signal again.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communica

Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

Abstract: A computer-implemented system for eliminating perpetual application programming interface (API) calls to minimize resource drain. The system may comprise: at least one non-transitory computer-readable medium configured to store instructions; and at least one processor configured to execute the instructions to perform operations. The operations may comprise: monitoring a dynamic list of one or more API calls, wherein the dynamic list is configured to vary in length; identifying a subset of the API calls that remain in the dynamic list through a number of the process cycles over a first threshold; querying one or more network databases to verify that the subset of the API calls have not been resolved; determining costs of dismissing the subset of the API calls; dismissing the API calls with costs less than a second threshold; and transmitting a notification API call to one or more user devices corresponding to the dismissed API calls.

Abstract: According to one embodiment, a memory system is capable of being connected to a host. The memory system includes a nonvolatile memory and a controller that receives information regarding an operating state of the host. The controller controls the nonvolatile memory according to commands from the host and selects a parameter for interrupt coalescing for transmissions to the host of interrupts related to command completion notices for the commands from the host based on the information regarding the operating state of the host.

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

Abstract: Data processing apparatus comprises a processing element configured to access an architectural register representing a given system register; mapping circuitry to map the architectural register representing the given system register to a physical register selected from a set of physical registers; a register bank having a set of two or more respective banked versions of the given system register, in which a respective one of the banked versions of the system register is associated with each of a plurality of current operating states of the processing element; in which, when the processing element changes operating state from a first operating state associated with a first one of the banked versions of the system register to a second operating state associated with a second, different, one of the banked versions of the system register, the processing element is configured to store the current contents of the architectural register representing the given system register to the first one of the banked versions o

Abstract: An information processing apparatus includes a storage unit configured to store information related to an activation of the information processing apparatus, a control unit configured to perform a control such that, in a case where the information stored in the storage unit relates to a first activation, the information processing apparatus is shifted into a standby state when power is supplied to the information processing apparatus, and in a case where the stored information relates to a second activation, the information processing apparatus is shifted into the standby state when the power is supplied to the information processing apparatus and also a signal input to the control unit is put into a particular state, and a power supply control unit configured to put the signal input to the control unit into the particular state when the information processing apparatus is not shifted into the standby state even when the power is supplied.

Abstract: Disclosed herein is a technique for managing I/O requests transmitted between a computing device and a storage device. According to some embodiments, the technique can be implemented by the computing device, and include providing at least one I/O request to a submission queue configured to store a plurality of I/O requests. In conjunction with providing the at least one I/O request, the computing device can identify that at least one condition associated with the submission queue—and/or a completion queue—is satisfied, where efficiency gains can be achieved. In turn, the computing device can (1) update an operating mode of the storage device to cause the storage device to cease interrupt issuances to the computing device when I/O requests are completed by the storage device, and (2) update an operating mode of the computing device to cause the computing device to periodically check the completion queue for completed I/O requests.

Abstract: Various embodiments of methods and systems for a power and performance-optimized secure image load boot flow in a specialty metering device (“SMD”) are disclosed. An exemplary method includes a CPU that transitions into an idle state, such as a WFI state, for durations of time during a boot sequence that coincide with processing by a DMA engine. That is, the CPU may “sleep” while the DMA engine processes workloads in response to instructions it received from the CPU.

Abstract: According to an example aspect of the present invention, there is provided an apparatus comprising a first processing core configured to generate first control signals and to control a display by providing the first control signals to the display via a first display interface, a second processing core configured to generate second control signals and to control the display by providing the second control signals to the display via a second display interface, and the first processing core being further configured to cause the second processing core to enter and leave a hibernation state based at least partly on a determination, by the first processing core, concerning an instruction from outside the apparatus.

Abstract: An information handling system includes a device, a processor, and a runtime agent. the device provides a System Management Interrupt (SMI) in response to an error on the device. The processor receives the SMI, enters a System Management Mode (SMM), and executes first interrupt handler code in SMM to provide interrupt information associated with the SMI when the SMI is associated with a non-critical error on the device, and exit SMM to a runtime mode. The runtime agent receives the interrupt information during the runtime mode to execute second interrupt handler code to service the non-critical error on the device.

Abstract: Systems and methods are disclosed to perform a function level reset in a memory controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a storage controller circuit configured to receive a function reset indicator from a host device, the function reset indicator identifying a selected storage controller function executing at a storage controller of the apparatus. The circuit may abort each command associated with the selected function and pending at the apparatus based on the function reset indicator, verify that no commands associated with the selected function remain pending at the apparatus, and clear registers associated with the selected function based on the determination that no commands associated with the selected function remain.

Abstract: A system and method dynamically assign interrupts to a virtual machine from an input/output (I/O) adapter based on I/O metrics of the I/O adapter. An interrupt manager monitors I/O adapter traffic flow metrics such as latency of data transfers, usage levels, and transfers per unit of time. The interrupt manager determines when a traffic flow metric for a virtual machine meets a predetermined performance threshold and updates virtual interrupt assignments in a logical interrupt table to improve performance of the system.

Abstract: An electronic device which schedules a plurality of tasks, and an operating method thereof. The electronic device includes a processor and a memory operatively connected to the processor, and when being executed, the memory stores instructions that cause the processor to: detect occurrence of an interrupt requesting performance of a second task while performing a first task; obtain reference values according to a time of the first task, and reference values according to a time of the second task; schedule the first task and the second task based on a reference value of the first task and a reference value of the second task which correspond to a time at which the interrupt occurs; and process the first task and the second task based on a result of the scheduling. Other embodiments are possible.

Abstract: A multi-processor system handles interrupts using a power and performance status of each processor and a usage scenario of each processor. The power and performance status is indicated by factors that affect power consumption and processor performance. The system identifies one of the processors for handling an interrupt based on a weighted combination of the factors. Each factor is weighted based on a usage scenario for which the interrupt was generated. The system then dispatches the interrupt to the identified one of the processors.

Abstract: A computing device implemented method for building a mutable type is disclosed. A data structure is generated in a contiguous section of memory. The data structure includes an element portion and an over-allocation portion. The element portion stores elements accessible with an index. A gap object is inserted into the over-allocation portion. The gap object is garbage collected.

Abstract: A computing device includes a processor, a volatile memory, and a non-volatile memory. The computing device receives a firmware update that includes updated firmware runtime components, such as updated runtime interrupt handlers (e.g. SMI handlers). The computing device stores the updated firmware runtime components in the volatile memory (e.g. RAM) of the device. The computing device also causes the updated firmware runtime components stored in the volatile memory to be used during the runtime of the computing device instead of one or more other firmware runtime components previously stored in the volatile memory. For example, the contents of one or more interrupt routing tables can be adjusted such that updated runtime interrupt handlers stored in volatile memory are used instead of previously installed and potentially insecure runtime interrupt handlers. On a subsequent reboot of the computing device, updated firmware runtime components stored in the non-volatile memory will be utilized.

Abstract: An image processing apparatus includes a block output unit, an arithmetic processing circuit, a data reading circuit, and a block descriptor generation unit. The block output unit outputs a block image based on an input block descriptor. The data reading circuit reads the block image after image processing from the arithmetic processing circuit based on an output block descriptor and outputs the block image after the image processing. The arithmetic processing circuit executes the image processing on block images for one band in accordance with an input band request. The data reading circuit outputs block images for one band in accordance with an output band request. The block descriptor generation unit stores input block descriptors and output block descriptors for at least one band in the predetermined memory in line with timing of the input band request or the output band request.

Abstract: A method for restricting write access to a non-volatile memory. The method includes receiving a request to write to a protected location in the non-volatile memory and determining whether the protected location is in a write-protected state. If the protected location is not in a write-protected state, the method includes writing data indicated by the request to the protected location. If the protected location is in a write-protected state, the method includes rejecting the request. The protected location stores a validation key to validate the contents of another portion of the non-volatile memory.

Abstract: One embodiment includes hardware logic to: receive first and second communications corresponding to an intellectual property (IP) core and begin a timed session in response to receiving the second communication; determine the firmware has completed processing the second communication before expiration of the timed session and increase a latency state corresponding to a resource in response to determining the firmware has completed processing the second communication before expiration of the timed session; receive a third communication corresponding to the IP core and begin an additional timed session in response to receiving the third communication; determine the firmware failed to complete processing the third communication before expiration of the additional timed session and decrease the latency state corresponding to the resource in response to determining the firmware failed to complete processing the third communication before expiration of the additional timed session.

Abstract: A processor includes cores to execute instructions, and circuitry to detect a system management interrupt (SMI) event on the processor, direct an indication of the SMI event to an arbiter on a controller hub, and receive an interrupt signal from the arbiter. The processor also includes an SMI handler to take action in response to the interrupt, and circuitry to communicate the interrupt signal to the cores. The cores include circuitry to pause while the SMI handler responds to the interrupt. The interrupt handler includes circuitry to determine that a second SMI event detected on the processor or controller hub is pending, and to take action in response. The interrupt handler includes circuitry to set an end-of-SMI bit to indicate that the interrupt handler has completed its actions. The controller includes circuitry to prevent the arbiter from issuing another interrupt to the processor while this bit is false.

Abstract: Described herein are embodiments that adaptively reduce the number of interrupts that occur between a device controller and a computer system. Device commands are submitted to the controller by an operating system on behalf of an application. The device performs the received commands and indicates command completions to the controller. A counter counts completions, and if the count exceeds a threshold number, the controller generates an interrupt to the computer system. If the count is greater than zero and the timeout interval has expired, then the controller generates an interrupt to the computer system. In some embodiments, the application attaches flags to one of the commands indicating that an interrupt relating to completion of the flagged command should be generated as soon as possible or that an interrupt relating to completion of all commands prior to and including the flagged command should be generated as soon as possible.

Abstract: A reporting device communicates with a master device by a first component and a daisy-chained second component. The reporting device receives a signal from the master device via the first component. The signal triggers the reporting device to transmit synchronously a telemetry data packet on the daisy-chained second component when a downstream device is coupled to the second component. The reporting device receives a first header packet having an address of the reporting device, transmits the telemetry data packet to the downstream device, and transmits a second header packet having an address of the downstream device.

Abstract: A data acquisition method of acquiring and latching data with a timing based on an input signal supplied to an input port, the method including: acquiring and retaining the data with a timing of when an edge of the input signal is detected, and starting a timer; and at the time of expiration of the timer, if the level of the input signal is a first level that is unchanged from start of the timer, latching the retained data and if the level of the input signal is a second level that is changed from the start of the timer, discarding the retained data.

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

Abstract: This disclosure generally relates to enabling a hypervisor of a host machine to provide virtual interrupts to select virtual processors or a set of virtual processors. More specifically, the present disclosure describes how a hypervisor of a host machine may monitor the status of one or more virtual processors that are executing on the host machine and deliver interrupts to the virtual processors based on a number of factors including, but not limited to, a priority of the interrupt, a priority of the virtual processor, a current workload of the virtual processor and so on.

Abstract: A computer system comprising a plurality of processor units, resources for executing a harmonic set of tasks, and a task interrupt switch device having inputs for receiving a common time base and the task interrupts, outputs each connected to a respective one of the processor units, registers each corresponding a to respective one of the outputs, reinitializable counters each corresponding to a respective one of the outputs, and a control unit arranged to distribute the task interrupts between the outputs as a function of the values of the registers and of the counters.

Abstract: An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is blocked from receiving interrupt signals using an interrupt blocking indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor unblocked, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

Abstract: Methods, systems, and devices for wireless communications are described. In some wireless systems, a base station centralized unit (CU) may communicate with a user equipment (UE) through a multi-hop backhaul architecture. This multi-hop backhaul connection may include a donor base station and any number of relay base stations connected via backhaul links. In some cases, the relay base stations or the UE may experience data congestion in a logical channel-specific buffer. The relay base stations or UE may implement backpressure signaling (e.g., in the medium access control (MAC) layer) to mitigate the congestion. A wireless device operating as a mobile termination (MT) endpoint may transmit a backpressure report message to a wireless device operating as a base station distributed unit (DU) endpoint for the logical channel. The base station DU may adjust a scheduling rate for data unit transmissions over the indicated logical channel based on the backpressure report.

Abstract: Storage virtualization techniques allow directories to be stored remotely, for example, by a cloud storage provider, but in a manner that appears to a user or application running on a local computing device as if the directories are stored locally—even though the data of those directories may not be resident on the local computing device. That is, the contents of directories that may exist in the cloud look and behave as if they were stored locally on a computing device.

Abstract: Approaches, techniques, and mechanisms are disclosed for reutilizing discarded link data in a buffer space for buffering data units in a network device. Rather than wasting resources on garbage collection of such link data when a data unit is dropped, the link data is used as a free list that indicates buffer entries in which new data may be stored. In an embodiment, operations of the buffer may further be enhanced by re-using the discarded link data as link data for a new data unit. The link data for a formerly buffered data unit may be assigned exclusively to a new data unit, which uses the discarded link data to determine where to store its constituent data. As a consequence, the discarded link data actually serves as valid link data for the new data unit, and new link data need not be generated for the new data unit.

Abstract: Techniques are disclosed for enabling an integrated sensor hub of a main computer to access a detachable peripheral device. In an embodiment, a system includes a main unit having a peripheral interface, an embedded controller, and a device controller. The peripheral interface is configured to be detachably coupled to a peripheral. The peripheral includes a control unit and an input/output device. The embedded controller is configured to communicate with the control unit of the peripheral via the peripheral interface while the peripheral is attached to the peripheral interface. The embedded controller includes at least one data register, and in some embodiments, a set of data registers, configured to store data relating to the peripheral and to the corresponding input/output device. The device controller is configured to read data from the data register(s) of the embedded controller, write data to the data register(s) of the embedded controller, or both.

Abstract: A security system dynamically, depending on processor core execution flow, controls fault injection countermeasure circuitry protect processor core from fault injection attacks.

Abstract: Methods, apparatus, and systems for facilitating effective power management through dynamic reconfiguration of interrupts. Interrupt vectors are mapped to various processor cores in a multi-core processor, and interrupt workloads on the processor cores are monitored. When an interrupt workload for a given processor core is detected to fall below a threshold, the interrupt vectors are dynamically reconfigured by remapping interrupt vectors that are currently mapped to the processor core to at least one other processor core, such that there are no interrupt vectors mapped to the processor core after reconfiguration. The core is then enabled to be put in a deeper idle state. Similar operations can be applied to additional processor cores, effecting a collapsing of interrupt vectors onto fewer processor cores.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.