Abstract: A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.

Abstract: Technologies are provided for dynamically changing a size of a cache region of a storage device. A storage device controller writes data to the cache region of the storage device using a particular storage format. The storage device controller then migrates the cached data to a storage region of the device, where the data is written using a different storage format. A dynamic cache manager monitors input and output activity for the storage device and dynamically adjusts a size of the cache region to adapt to changes in the input and/or output activity. The dynamic cache manager can also adjust a size of the storage region. The storage device controller can automatically detect that the storage device has dynamic cache support and configure the storage device by creating the cache region and the storage region on the device.

Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.

Abstract: Dynamic block optimization for space and performance is disclosed, including: determining that a data pattern associated with a data block included in a write request matches a promoted data pattern; and performing the write request by associating the data block with a previously stored copy of the data block without updating an associated reference count. Dynamic block optimization for space and performance further includes determining that a data pattern associated with a data block included in a write request matches a predetermined data pattern; and performing the write request by storing a static representation associated with the data block and not storing the data block, wherein the static representation is usable to generate the data block.

Abstract: Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.

Abstract: Deploying client-specific applications in a storage system utilizing redundant system resources, including: identifying a redundant controller in the storage system, wherein the storage system includes at least a first controller and the redundant controller; and executing one or more applications on the redundant controller, wherein the one or more applications are executed in a container.

Abstract: A method for accessing an extended memory, a device, and a system are disclosed. According to the method, after receiving a first memory access requests from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

Abstract: Methods and systems for reclaiming disk space via consolidation and deletion of expired snapshots are described. The expired snapshots may comprise snapshots of a virtual machine that are no longer required to be stored within a data storage domain (e.g., a cluster of data storage nodes or a cloud-based data store). In some cases, rather than storing an incremental file corresponding with a particular snapshot of the virtual machine, a full image of the particular snapshot may be generated and stored within the data storage domain. The generation of the full image may allow a chain of dependencies supporting the expired snapshots to be broken and for the expired snapshots to be deleted or consolidated. The full image of the particular snapshot may be generated using compute capacity in the cloud or may be generated locally by a storage appliance and uploaded to the data storage domain.

Abstract: Systems and methods are described for handling requests to execute idempotent code in an on-demand code execution system or other distributed code execution environment. Idempotent code can generally include code that produces the same outcome even when executed multiple times, so long as dependencies for the code are in the same state as during a prior execution. Due to this feature, multiple executions of idempotent code may inefficiently use computing resources, particularly in on-demand code execution system (which may require, for example, generation and provisioning of an appropriate execution environment for the code). Aspects of the present disclosure enable the on-demand code execution system to process requests to execute code by verifying whether dependency states associated with the code have changed since a prior execution. If dependency states have not changed, no execution need occur, and the overall computing resource us of the on-demand code execution system is decreased.

Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

Abstract: A microcontroller (1) comprises a processor (2), a memory (3), a bus (15) connecting the processor (2) and the memory (3) and a memory watch unit (14), comprising one or more memory-watch event registers and one or more configuration registers. The memory watch unit (14) is arranged to monitor memory access instructions on the bus (15), and can be configured, using the one or more configuration registers, to (i) detect a memory access instruction for a memory address in a configurable watch region of the memory (3), and (ii) change the contents of one or more memory-watch event registers in response to such a detection.

Abstract: An apparatus comprises a first storage system comprising a plurality of storage devices. The first storage system is configured to participate in a replication process with a second storage system. The first storage system is further configured to identify data to be replicated to the second storage system as part of the replication process, to obtain information characterizing network behavior of at least one network connecting the first storage system to the second storage system, to select a compression method from a set of available compression methods based on the obtained information characterizing the network behavior of said at least one network, to compress the data to be replicated to the second storage system utilizing the selected compression method, and to provide the compressed data to the second storage system.

Abstract: One or more techniques and/or computing devices are provided for implementing synchronous replication. For example, a synchronous replication relationship may be established between a first storage controller hosting local storage and a second storage controller hosting remote storage (e.g., replication may be specified at a file, logical unit number (LUN), or any other level of granularity). Data operations and offloaded operations may be implemented in parallel upon the local storage and the remote storage. Error handling operations may be implemented upon the local storage and implement in parallel as a best effort on the remote storage, and a reconciliation may be performed to identify any data divergence from the best effort parallel implementation. Storage area network (SAN) operations may be implemented upon the local storage, and upon local completion may be remotely implemented upon the remote storage.

Abstract: A method for managing volumes in a scratch pool of a virtual tape system is disclosed. In one embodiment, such a method provides a scratch pool containing volumes for use in a virtual tape system. The method further enables a user to predefine an external pool of volumes residing outside of the scratch pool. This external pool may be hidden to a host system accessing the virtual tape system. The method monitors current and/or past usage of the volumes in the scratch pool and, based on the usage, predicts a future need for volumes in the scratch pool. The method automatically moves volumes between the external pool and the scratch pool in accordance with the future need. A corresponding system and computer program product are also disclosed.

Abstract: A buffer controller includes a pointer generator, a code converter, a synchronizer, a code restorer, and a comparator. The pointer generator operates according to a first clock signal, and generates a first pointer by encoding a first address of a buffer with a first code. The code converter generates a first transmission pointer by converting the first pointer with a second code or a third code according to an amount of data stored in or read from the first address. The synchronizer synchronizes the first transmission pointer with a second clock signal. The code restorer generates a first comparison pointer by restoring the first transmission pointer, synchronized with the second clock signal, with the first code. The comparator compares the first comparison pointer with a second pointer. The second pointer defines a second address of the buffer with the first code.

Abstract: A method for validating data is disclosed. In one embodiment, such a method includes reading a data element from a volume. The method determines a location of the data element within the volume. This location is mapped to a particular data set stored on the volume, such as by mapping the location to the particular data set using a volume table of contents (VTOC) associated with the volume. The method further determines a first identifier (e.g., a creation date) associated with the particular data set and compares this first identifier to a second identifier (e.g., a creation date) appended to the data. If the first identifier matches the second identifier, the method validates the data. A corresponding system and computer program product are also disclosed.

Abstract: There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of pages arranged in a vertical direction on a substrate. The peripheral circuits may perform a program operation on a selected page. The control logic may control the peripheral circuits to perform a first partial program operation of sequentially programming some of the pages up to a first page. The control logic may perform a first partial erase operation of erasing the other non-programmed pages. The control logic may perform a second partial program operation of partially programming the pages on which the first partial erase operation has been performed.

Abstract: In a general aspect, a method for sharing a memory between two functional entities can include assigning, to the first functional entity, a first data transformation function and a first inverse transformation function, and assigning, to the second functional entity a second data transformation function and a second inverse transformation function. The second inverse data transformation function can be incompatible with the first data transformation function and the first inverse data transformation function can be incompatible with the second data transformation function.

Abstract: A computer implemented method, system, and computer program product for enabling strong consistency of unique objects between zones comprising enabling consistency of an unique data object between in zones by switching between consistency techniques to keep the unique data object consistent between the zones; wherein read and write access is enabled to the unique object in the zones.

Abstract: Certain aspects of the present disclosure provide techniques for increasing processor caching efficiency by cache data pattern optimization. One embodiment includes a method for managing data in a cache, including: receiving data to be cached at the cache; determining that the data to be cached matches a predefined data pattern; and updating a tag RAM associated with the cache with a pattern tag comprising tag bits and pattern bits, wherein the pattern bits match the predefined data pattern.

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

Abstract: The data transfer device receives file data through a network and writes the file data to a storage device on a block basis, in which the communication processor receives a receiving instruction for the file data from an external host CPU and receives the file data via one or more packets from the network according to the receiving instruction, the receiving buffer stores data received in the communication processor therein upon receiving each packet, and the command issuance controller acquires, from the external host CPU, map information indicating a position to write the file data in a storage area of the storage device, specifies data in the receiving buffer for writing according to a data storing status of the receiving buffer, issues a write command for writing a specified data to the storage device and sends it to the storage device.

Abstract: Processing an I/O operation may include the host selecting one of the available paths over which to send each I/O operation to the data storage system. The selected path may be to a particular director that has responsibility for cache slot allocation and locally accessing the cache slot predicted to include the data of the I/O operation. The host may understand the cache slot allocation algorithm used on the data storage system and how cache slots are allocated for particular logical devices and tracks or locations on the logical devices. The host may direct I/Os down a path to a particular director that has, or will allocate, the cache slot used for the I/Os. There may be multiple directors in a data storage system including a distributed global memory. Each director may locally access a group of cache slots and communicate over a fabric to access the distributed global memory.

Abstract: Exemplary methods, apparatuses, and systems include a recovery manager receiving selection of a storage profile to be protected. The storage profile is an abstraction of a set of one or more logical storage devices that are treated as a single entity based upon common storage capabilities. In response to the selection of the storage profile to be protected, a set of virtual datacenter entities associated with the storage profile is added to a disaster recovery plan to automate a failover of the set of virtual datacenter entities from a protection site to a recovery site. The set of one or more virtual datacenter entities includes one or more virtual machines, one or more logical storage devices, or a combination of virtual machines and logical storage devices. The set of virtual datacenter entities is expandable and interchangeable with other virtual datacenter entities.

Abstract: According to certain aspects, a memory module is coupled to a memory controller of a host computer system via an interface. The memory module is operable in at least a second mode and a first mode. The memory module in the second mode is configured to perform training related to one or more training sequences initiated by the memory controller while the memory module is not accessed by the memory controller for memory read or write operations. The memory module in the first mode is configured to perform one or more memory read or write operations not associated with the one or more training sequences by communicating data signals with the memory module. The memory module has an open-drain output pin via which the memory module output a signal indicating a parity error having occurred while the memory module is performing a normal memory read or write operation, and via which the memory module output a signal related to the one or more training sequences.

Abstract: A processor includes a front end to decode an instruction and an allocator to assign the instruction to an execution unit to execute the instruction to permute vector data into a destination register for storing elements. The execution unit includes logic to compute an element count, logic to compute an index size, logic to compute a byte count, a temporary destination, an index from an index vector, an offset, logic to determine a subset of the temporary destination, and logic to store the subset in one element in the destination register.

Abstract: The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from a first digit of the mask that is set; and convert, in response to a second control signal, a digit position in the indicator mask of the first digit that is set to an identifier value as an index.

Abstract: The performance of a computer system which distributes and stores user data and a redundant code is improved. Each computer generates group information indicating positions of a user data region and a redundant code region in each of a plurality of computers; when a write request for write data is received, each computer writes the write data to a local storage device, selects a transmission destination computer on the basis of the group information, and transmits transmission data to the transmission destination computer; when a plurality of pieces of transmission data are respectively received, each computer generates a redundant code by using the plurality of pieces of transmission data on the basis of the group information, and writes the redundant code to the local storage device; and when configurations of the plurality of computers are changed, each computer changes the group information on the basis of the changed configurations.

Abstract: A method of decoding may include performing fewer than ? 2 k - 1 k ? number of sensing operations of multilevel cells within a nonvolatile memory device, decoding pages corresponding to each of the sensing operations while correcting a channel error using an RIO code, and extracting user data from the decoded pages.

Abstract: A multi-node data storage system comprises a first data storage system having an owner node and a backup node in a first location coupled to a second data storage system having an owner node and a backup node in a second location. Each storage system includes a copy of the same data volume. A failure of a node of the multi-node storage system is detected. An outstanding write request to the first storage system is identified. If the owner node in the first storage system fails, it is determined whether the outstanding write corresponds to a host write to the backup node of the first storage system. If so, a retransmission message is sent to the second storage system. Otherwise, the data region associated with the outstanding write request is read from the first storage system, and a resynchronization message is sent to the second storage system.

Abstract: A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured receive data streams from multiple different host systems and keep data for the separate streams in separate sub-drives. The method may include dynamically changing overprovisioning of the sub-drives in response to changes in relative workload measurements of data writes coming from the different host systems.

Abstract: Execution state information corresponding to an instantiated virtual machine are retrieved. A score to indicate a target memory location is able to be determined based at least in part on a source memory location is computed based at least in part on the execution state information. The score and the target memory location are indicated.

Abstract: A method, computer system, and a computer program product for soft fencing is provided. The present invention may include identifying a logical device swap occurred. The present invention may also include, in response to a logical device swap, creating a soft fence command. The present invention may then include issuing the created soft fence command.

Abstract: A data backup method and a data recovery method are provided. The data backup method includes: updating a main information table and a sub information table and generating physical unit information according to an erase count and a physical unit status of a physical unit; writing the physical unit information into the physical unit before writing data into the empty physical unit; writing the main information table and the sub information table into a rewritable non-volatile memory module according to corresponding conditions. The data recovery method includes: writing a latest main information table stored in a rewritable non-volatile memory module into a memory; updating the main information table in the memory according to a sub information table which is newer than the main information table; and updating the main information table in the memory according to physical unit information which is newer than the sub information table.

Abstract: A high-performance on-module caching architecture for hybrid memory modules is provided. A hybrid memory module includes a cache controller, a first volatile memory coupled to the cache controller, a first multiplexing data buffer coupled to the first volatile memory and the cache controller, and a first non-volatile memory coupled to the first multiplexing data buffer and the cache controller, wherein the first multiplexing data buffer multiplexes data between the first volatile memory and the first non-volatile memory and wherein the cache controller enables a tag checking operation to occur in parallel with a data movement operation. The hybrid memory module includes a volatile memory tag unit coupled to the cache controller, wherein the volatile memory tag unit includes a line connection that allows the cache controller to store a plurality of tags in the volatile memory tag unit and retrieve the plurality of tags from the volatile memory tag unit.

Abstract: A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task, storing the task-relating branch prediction data of the second task in the branch prediction history table, and ensuring that task-independent branch prediction data is maintained.

Abstract: An integrated circuit is disclosed for data retention with data migration. In an example aspect, the integrated circuit includes a logic block, a memory block, and retention control circuitry coupled to the logic and memory blocks. The logic block includes multiple retention-relevant storage devices to store first data and second data. The multiple retention-relevant storage devices include a first group of retention-relevant storage devices to store the first data and a second group of retention-relevant storage devices to store the second data. The memory block maintains memory data in the memory block during a retention operational mode. The retention control circuitry causes the retention-relevant storage devices of the second group to be activated into multiple scan chains and also migrates the second data between the second group and the memory block using the multiple scan chains to accommodate transitions between the retention operational mode and a regular operational mode.

Abstract: Storage devices, and methods for use therewith, are described herein. Such storage devices can include flash memory, random access memory (RAM), and a memory controller in communication therewith. To improve write performance, the memory controller is configured to store first and second data, corresponding to consecutive unaligned first and second write commands received within a threshold amount of time of one another from a host, sequentially relative to one another within the flash memory. This can involve temporarily storing a tail portion of the first data in the RAM until after a front portion of the first data is stored in the flash memory, and thereafter (after the second write command is received) using the tail portion of the first data to pre-pad a front portion of the second data when the second data is being stored in the flash memory.

Abstract: A computer system accesses a multiplatform firmware image to obtain a GUID identifying a platform for the computer system. The multiplatform firmware image includes a core firmware volume and a plurality of platform-specific firmware volumes. The computer system installs a platform identifier interface including the GUID. The computer system executes files within a platform-specific firmware volume including the GUID and a file of the core firmware volume including the GUID based at least in part on dependency expressions of the executed files and the platform identifier interface.

Abstract: The present disclosure includes apparatuses and methods related to memory alignment. An example method comprises performing an alignment operation on a first byte-based memory element and a second byte-based memory element such that a padding bit of the first byte-based memory element is logically adjacent to a padding bit of the second byte-based memory element and a data bit of the first byte-based memory element is logically adjacent to a data bit of the second byte-based memory element.

Abstract: Embodiments of the present invention provide a method, system and computer program product for assertion management in a dynamically assembled programmatic environment. In an embodiment of the invention, a method for assertion management in a dynamically assembled programmatic environment can include dynamically assembling different execution units into a dynamically assembled computer program, applying an assertion to at least one of the different execution units through an introspection of the one of the different execution units, and generating an assertion result reporting a failure of the assertion responsive to the failure of the assertion.

Abstract: Embodiments of the present disclosure provide a disk capacity predicting method, apparatus, equipment and non-volatile computer storage medium. On the one hand, the change data of the disk capacity is obtained according to the historical capacity data of the disk; then the target inflection point in the historical capacity data is obtained according to the change data of the disk capacity; and then the linear relationship between the time and disk capacity is obtained according to the historical capacity data after the target inflection point. Therefore, technical solutions provided by embodiments of the present disclosure may achieve improvement of accuracy of prediction of disk capacity trend and reduce the cost needed in disk capacity prediction.

Abstract: Methods and systems for allocating disk space and other limited resources (e.g., network bandwidth) for a cluster of data storage nodes using distributed semaphores with atomic updates are described. The distributed semaphores may be built on top of a distributed key-value store and used to reserve disk space, global disk streams for writing data to disks, and per node network bandwidth settings. A distributed semaphore comprising two or more semaphores that are accessed with different keys may be used to reduce contention and allow a globally accessible semaphore to scale as the number of data storage nodes within the cluster increases over time. In some cases, the number of semaphores within the distributed semaphore may be dynamically adjusted over time and may be set based on the total amount of disk space within the cluster and/or the number of contention fails that have occurred to the distributed semaphore.

Abstract: A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task, storing the task-relating branch prediction data of the second task in the branch prediction history table, and ensuring that task-independent branch prediction data is maintained.

Abstract: An image processing apparatus includes a hardware processor that is capable of performing mode control of causing the image processing apparatus to transition from a first operation mode to a second operation mode at a time when a plurality of services is not being executed, obtains service operation history information and manages service operation status in the past for each of time zones, and determines whether an operation target service is to be executed by the image processing apparatus or to be executed by an external resource in place of the image processing apparatus, wherein the plurality of services is classified into a substitute execution viable service and a substitute execution unviable service, and the hardware processor makes a determination to the effect that the operation target service is to be processed by substitute execution by the external resource.

Abstract: Example multi-device storage systems and methods provide disaggregated read/write operations. Read and/or write data requests are received from a host system at a storage controller for a plurality of storage devices. A target service host storage device is identified that hosts a target portion of a logical map of storage locations distributed among the plurality of storage devices. The target service host storage device identifies a destination storage device corresponding to a target location for the request. A data transfer from the host system to the destination storage device is processed for the request and the logical map of the target service host device is updated. The target service host storage device and the destination storage device may be different storage devices among the plurality of storage devices.

Abstract: A method for execution by a computing device includes obtaining utilization information of a pair of adjacent dispersed storage and task (DST) execution units of a common pillar. The utilization information of the pair of adjacent DST execution units is verified based on companion utilization information. Slices to migrate are selected in response to verifying the utilization information, and migration of the slices to migrate is facilitated. An updated storage map is generated based on the slices to migrate. A storage map modification package that includes a previous storage map and the updated storage map is generated. Attaching a signature from each DST execution unit of the pair of adjacent DST execution units to the storage map modification package is facilitated to produce a fully signed storage map modification package. The fully signed storage map modification package is published.

Abstract: In one aspect, a system for pre-fetching performance data in a monitored environment is disclosed. The system can include a processor; a memory; and one or more modules stored in the memory. The one or more modules are executable by the processor to perform operations including: record queries that request for application performance data with latencies longer than a threshold; learn access patterns in the recorded queries with latencies longer than the threshold; pre-fetch and cache the application performance data requested by the recorded queries before the same recorded queries are requested next time; and provide the pre-fetched application performance data from the cache when the same recorded queries are requested next time.

Abstract: In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter picks the memory access requests from the command queue based on a plurality of criteria, and provides picked memory access requests to a memory channel. The arbiter includes a streak counter for counting a number of consecutive memory access requests of a first type that the arbiter picks from the command queue. When the streak counter reaches a threshold, the arbiter suspends picking requests of the first type and picks at least one memory access request of a second type. The arbiter provides the at least one memory access request of the second type to the memory channel.