Abstract: In an example embodiment, a hypervisor exposes a virtual input-output memory management unit (IOMMU) to a first virtual machine. The first virtual machine includes a first guest operating system (OS). The hypervisor exposes a first virtual device to the first virtual machine. The hypervisor exposes a shared memory device to a second virtual machine. The second virtual machine includes a second guest OS. The hypervisor detects that the first guest OS modified the virtual IOMMU to provide access to a memory page of the first virtual machine. The hypervisor receives a base address from the second virtual machine. The base address is programmed into the shared memory device by the second virtual machine. The hypervisor maps the memory page into the second virtual machine at a page address, which is determined from the base address and a bus address.

Abstract: A communication system coupled to a data-acquisition circuit and to a data-processing circuit is provided, including at least one shift register, an addressing circuit and a multiplexer. The shift register includes a serial input for inputting and storing data in series, a serial output for outputting data in series, and parallel outputs for outputting data stored in the shift register in parallel. The addressing circuit is coupled to the shift register in order to identify the positions of stored data, and the multiplexer is coupled to the parallel outputs of the shift register in order to output the stored data to the data-processing circuit in series. Methods for communication between a data-acquisition circuit and a data-processing circuit are also provided.

Abstract: The apparatus and method for calculating and retaining a bound on error during floating point operations inserts an additional bounding field into the standard floating-point format that records the retained significant bits of the calculation with notification upon insufficient retention. The bounding field, which accounts for both rounding and cancellation errors, has two parts, the lost bits D Field and the accumulated rounding error R Field. The D Field states the number of bits in the floating point representation that are no longer meaningful. The bounds on the real value represented are determined from the truncated floating point value (first bound) and the addition of the error determined by the number of lost bits (second bound). The true, real value is absolutely contained by the first and second bounds. The allowed loss (optionally programmable) of significant bits provides a fail-safe, real-time notification of loss of significant bits.

Abstract: A cache memory system has a first cache memory comprising one or more levels, to store data corresponding to addresses, a second cache memory comprising a plurality of non-volatile memory cells, which has higher speed capability than a main memory, has a larger capacity than the first cache memory and stores data corresponding to addresses, and a first storage to store address conversion information from a virtual address issued by a processor to a physical address and to store flag information indicating whether data is stored in the second cache memory by a page having a larger data amount than a cache line, the first cache memory being accessed by the cache line.

Abstract: After acquiring a network address, a computing device accesses a shared data store and writes the network address to the shared data store. The computing device additionally reads a plurality of network addresses from the shared data store, wherein the plurality of network addresses are for a plurality of nodes that are members of a peer-to-peer system. The computing device then joins the peer-to-peer system based on communicating with the plurality of nodes using the plurality of network addresses.

Abstract: The subject technology addresses the need in the art for improving utilization of network bandwidth in a multicast network environment. More specifically, the disclosed technology addresses the need in the art for extending multipathing to tenant multicast traffic in an IP overlay network, which enables the network to fully utilize available bandwidth for multicast traffic. In some examples, nodes in the overlay network may be connected by virtual or logical links, each of which corresponds to a path, perhaps through many physical links, in the underlying network.

Abstract: A memory storage system is that includes a memory element having a memory address for a physical memory. A memory controller receives a command for accessing the memory element using a program-generated address and dynamically transforms the program-generated address into the memory address for the physical memory using a rotation module and configuration information. A data word accessed by the physical address is then provided to a set of arithmetic logic units (ALUs) where multiple computations are performed simultaneously so as top reduce program execution time and energy. The configuration information provided to the rotation unit configures the set of ALUs.

Abstract: The present disclosure provides a device comprising a memory translation buffer configured to manage (i) a first request for a first search in a page table, wherein the first request is responsive to a first null result of a search for a first address translation in a translation look-aside buffer (“TLB”) and (ii) a second request for a second search in the page table, wherein the second request is responsive to a second null result of a search for a second address translation in the TLB. The memory translation buffer is also configured to compare a virtual memory address of the first request to a virtual memory address of the second request and, based on a result of the comparing the virtual memory address of the first request to the virtual memory address of the second request, access the page table to perform the second search.

Abstract: First logical cores supported on physical processor cores in a computing system can be designated for execution of message-passing workers of a plurality of message workers while at least second logical cores supported on the physical processor cores can be designated for execution of procedural code such that resources of a physical processor core supporting the first logical core and the second logical core are shared between a first logical core and a second logical core. A database object in a repository can be assigned to one message-passing worker, which can execute operations on the database object while procedurally coded operations are processed using the second logical core on one or more of the plurality of physical processor cores while the first logical core executes the message-passing worker.

Abstract: A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing.

Abstract: An apparatus and method for multidimensional resource allocation and management are provided. The method includes receiving a request for allocation of a block of a multidimensional memory resource, selecting a grid for tracking spaces of the multidimensional memory resource according to the allocation request, determining whether a block of the multidimensional memory resource corresponding to the request for the allocation of the block of the multidimensional memory resource is unallocated, and allocating the unallocated block of the multidimensional memory resource.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: A method and circuit arrangement selectively source and/or write data from/to extended registers of an extended register file based in part on whether an operand address of an instruction references a primary register of primary register file configured to store a pointer to the extended register. Control logic connected to the primary register file and the extended register file determines whether the operand address references a primary register configured to store a pointer, and responsive to the determination, the control logic causes execution logic to selectively source and/or write data from/to the extended register pointed to by the pointer stored in the referenced primary register.

Abstract: Two-dimensional compressed data sets can be re-aligned while preserving compression of the data. A set of one or more shifts and a corresponding set of one or more first dimension indices into a two-dimensional compressed data set for re-aligning the two-dimensional compressed data set are determined. Impact of re-aligning upon each vector in the second dimension of the two-dimensional compressed data set is determined while the two-dimensional compressed data set remains compressed. New compressed vectors are created in the second dimension resulting from re-aligning. Compression information is modified for each of the original vectors of the two-dimensional compressed data set that remain after re-aligning based, at least in part, on the new compressed vectors. A re-aligned version of the two-dimensional compressed data set is created with the new compressed vectors, and the remaining original vectors with their modified compression information.

Abstract: Provided is an image forming apparatus that speeds up starting. The image forming apparatus is provided with a main storage part and an auxiliary storage part. A boot loader that is stored in the auxiliary storage part is expanded to the main storage part. The boot loader that has been expanded is executed to generate a defective area table for the auxiliary storage part. When a kernel of an OS that is stored in the auxiliary storage part is expanded, the kernel is caused to be referred the defective area table that has been generated. When the kernel is executed, the defective area table is not generated. Thereby, the defective area table generated by the boot loader can be used by the OS, which allows the boot time to be shortened.

Abstract: Disclosed herein are systems and methods for paging to a direct segment maintained by a multiplexed TLB. The multiplexed TLB defines a direct segment to directly map a virtual address range to a physical address range, which increases the reach of the multiplexed TLB. A partition code is maintained in the multiplexed TLB to indicate usage of the direct segment by an associated process. A management process, such as a system pager, uses the unused part of the direct segment for storing paged data. As the process continues to use more of the direct segment, paged data stored in the previously unused part of the direct segment can be evicted from memory or moved elsewhere in memory so that the process can continue to use the direct segment.

Abstract: Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n?1, the value of si corresponds to a range of the ith partition.

Abstract: Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.

Abstract: A method for managing, by device, a matrix of keys, including at least one line and at least two columns, each key making short circuiting a line and a column when pressed. The method includes a sweeping phase, including, for each line: writing a predetermined logic value in the line; and for each column, reading a logic value in the column and comparing the read logic value and the predetermined logic value. For each line processed: the writing step is carried out during a predetermined time interval. For each column, the reading step is carried out during a first portion of the time interval. The sweeping phase further includes, for each column, writing the predetermined logic value in the column during a second portion of the predetermined time interval. The predetermined time interval is equal to the sum of the durations of the first and second portions.

Abstract: Memory pages that are allocated to a memory consumer and continue to be accessed by the memory consumer are included in a free list, so that they may be immediately allocated to another memory consumer as needed during the course of normal operation without preserving the original contents of the memory page. When a memory page in the free list is accessed to perform a read, a generation number associated with the memory page is compared with a stored copy. If the two match, the read is performed on the memory page. If the two do not match, the read is not performed on the memory page.

Abstract: Disclosed herein are data storage device embodiments for accelerating database operations and associated methods. In one embodiment, the data storage device includes a controller; an array of one or more solid-state memory storage devices; a first memory for storing processor executable instructions associated with database operations; and a second memory for storing data related to the database operations; wherein the controller is configured to execute the instructions to: cause data to be read from the solid-state memory storage devices into the second memory; determine whether the data match a query specified by the instructions; and perform a database operation based on the query match determination.

Abstract: A system and method for providing access to an object over a network may comprise hosting an object on a distributed data processing system accessible over the network, the object contained within a cell; generating, by a cell access provider, a unique and random address for the cell containing the object, utilizing an address resolution module and providing, by the cell access provider, the unique and random address to a computing device of a unique consumer; and upon receipt of the unique and random address from the unique user, matching the unique and random address with the cell to facilitate access by the unique user to the object. The object may comprise a virtual object acting as a cell for facilitating access to one or more additional objects. The virtual object cell may contain one or more unique and random addresses facilitating access to one or more additional objects.

Abstract: A parallel arithmetic device includes a status management section, a plurality of processor elements, and a plurality of switch elements for determining the relation of coupling of each of the processor elements. Each of the processor elements includes an instruction memory for memorizing a plurality of operation instructions corresponding respectively to a plurality of contexts so that an operation instruction corresponding to the context selected by the status management section is read out, and a plurality of arithmetic units for performing arithmetic processes in parallel on a plurality of sets of input data in a manner compliant with the operation instruction read out from the instruction memory.

Abstract: A method for avoiding signal interference between a first RF circuit and a second RF circuit is provided. The first and second RF circuits are co-located and the first RF circuit is configured to operate in a first frequency range. The second RF circuit is configured to operate in a second frequency range, where the first frequency range overlaps, at least in part, the first frequency range. The method initiates with a controller that is coupled to the first RF circuit and the second RF circuit. Then, the second RF circuit is configured to avoid RF signal collisions with the first RF circuit. An apparatus where two RF devices are co-located without causing interference for each other is also provided.

Abstract: Some embodiments of a system and a method to dynamically allocate memory on program stack are presented. A memory allocator executable on a processing device may create a data structure on a stack to hold data for a program running on the processing device. The memory allocator can dynamically change the size of the data structure on the stack in response to data need of the program while the program is running.

Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.

Abstract: Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n?1, the value of si corresponds to a range of the ith partition.

Abstract: A container database may contain multiple database dictionaries, each database dictionary defining a pluggable database. When database sessions are established on a container DBMS, each database session is given access to a pluggable database by establishing the respective database dictionary of the pluggable database as the database dictionary for that database session. Database commands issued through database session can only access the database objects defined in the database dictionary established for the database session.

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Abstract: In one embodiment, methods are described to provide a binary translation and randomization system. Relocation metadata is received, which comprises, for each of a plurality of execution units in an executable file, a mapping from the executable file into an address space range. For at least one of the plurality of execution units, the mapping is modified to replace instructions within the address space range with a relocated copy of the instructions at a randomly located address space range. An order of the plurality of execution units may thus be modified. An image is generated from the executable file using the relocation metadata, and an execution of the image is caused. The randomization may be carried out in two passes to provide executable files that are uniquely randomized for each computer and for each execution.

Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package is configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface, where the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.

Abstract: An instruction is provided that includes an opcode field to identify a store instruction to store in a designated location current values of operational parameters of an adapter function of an adapter; a first field to identify a location, the contents of which include a function handle identifying a handle of the adapter function for which the store instruction is being performed, and an indication of an address space associated with the adapter function identified by the function handle to which the store instruction applies; and a second field to identify the designated location of where a result of the store instruction is to be stored. Execution of the instruction includes obtaining information from a function information block associated with the adapter function; and copying the information from the function information block into the designated location, based on completion of one or more validity checks with one or more predefined results.

Abstract: A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The microprocessor unit comprises a register that contains particular bit fields for defining selectable power modes. The particular bit fields in the register define pointers to a power mode defining register. Each pointer selects a corresponding bit field in the power mode defining register. The bits in the bit fields of the power mode defining register either directly control a power mode of at least one functional or peripheral blocks of the unit; or they are pointers to a further power mode defining register and the bits in the bit fields of the further power mode defining register directly control a power mode of at least one functional or peripheral blocks of the unit.

Abstract: Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.

Abstract: A block storage system includes a host and comprises a block storage module that is coupled to the host. The block storage module includes a MRAM array and a bridge controller buffer coupled to communicate with the MRAM array. The MRAM array includes a buffer widow that is moveable within the MRAM array to allow contents of the MRAM array to be read by the host through the bridge controller buffer even when the capacity of the bridge controller buffer is less than the size of the data being read from the MRAM array.

Abstract: Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory device. The temperature measurement device measures the internal temperature of the memory device. Memory throttling can therefore be implemented based on more accurate measurements and with a much shorter response time.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: An electronic apparatus is disclosed. The electronic apparatus comprises a random access memory (RAM), a read-only memory (ROM) and a processing unit. The RAM stores a call transfer table, wherein the call transfer table comprising at least one transferred address in the RAM. The ROM stores at least one code to call one address of the call transfer table. The processing unit executes the code in the ROM and reads the transfer table accordingly, then transfers to run the data in the transferred address of the RAM.

Abstract: Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The SAS expander also includes a Content Addressable Memory (CAM) including entries that each associate a SAS address with an entry in the routing memory. Further, the SAS expander includes a controller that receives a request for a SAS address, uses the CAM to determine a corresponding routing memory entry for the requested SAS address, and selects the port indicated by the corresponding routing memory entry.

Abstract: Methods and structure are provided for representing ports of a Serial Attached SCSI (SAS) expander circuit within routing memory. The SAS expander includes a plurality of PHYs and a routing memory. The routing memory includes entries that each indicate a set of PHYs available for initiating a connection with a SAS address, and also includes an entry that represents a SAS port with a start tag indicating a first PHY of the port and a length tag indicating a number of PHYs in the port. The SAS expander also includes a Content Addressable Memory (CAM) including entries that each associate a SAS address with an entry in the routing memory. Further, the SAS expander includes a controller that receives a request for a SAS address, uses the CAM to determine a corresponding routing memory entry for the requested SAS address, and selects the port indicated by the corresponding routing memory entry.

Abstract: A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: A method and apparatus are described for processing video data. In one embodiment, a processor is provided with a video compression engine (VCE) that has a memory having a plurality of rows and a plurality of columns of addresses. Video data, (luma data or chroma data), is written in row (i.e., raster) order into the addresses of the memory, and then the data is read out of the addresses in column order. Data is written into the addresses of the columns of the memory as they are read out, which is subsequently read out in row order. This process of switching back and forth between reading and writing data in row and column order continues as the data is read and processed by an encoder to generate a compressed video stream.

Abstract: A method, a computer readable medium and a memory controller. The method for writing information to a K-level memory unit, includes: receiving a sequence of information bits; generating an information value that represents the sequence of information bits; applying a first function to the information value, to provide a first function result; selecting a first cell of the K-level memory unit as a current cell; wherein K is a positive integer that is greater than 1; writing the first function result to the first cell; and repeating the stages of: (a) reading a current cell to provide a current read result; (b) applying a second function to the current read result and to a function result that was written to the current cell, to provide a second function result; (c) selecting another cell as a current cell; and (d) writing the second function result to the current cell.

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract: A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with address allocation flag information being that no address information is allocated output an address contention signal. When outputting the address contention signal, each device requiring address allocation determines whether the currently allocated address information is available according to whether the other devices requiring address allocation with address allocation flag information being that no address information is allocated already output address contention signals.

Abstract: The present invention is directed to a method and software for managing the host-to-volume mappings of a SAN storage system. The host-to-volume mappings of the SAN storage system are represented in mapping configuration components. The active mapping configuration component represents the current host-to-volume mapping for the SAN storage system. Only one mapping configuration component is active at a time. The host-to-volume mappings of the SAN storage system are changed by deactivating the active mapping configuration component and activating an inactive mapping configuration component that represents a different mapping configuration, effecting a repartition, repurpose, disaster recovery, or other business activity. This can be a scheduled task or performed in an on-demand manner. The mapping configuration components are managed and controlled through the management component of the SAN storage system.

Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating, a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to hypervisor, allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.

Abstract: There are provided a storage system and a method of operating thereof. The method comprises: a) representing to a plurality of hosts an available logical address space divided into one or more logical groups (e.g. logical volumes, virtual partitions, snapshots, combinations of a given logical volume and its respective snapshot(s), etc.), and b) mapping between one or more contiguous ranges of addresses related to the logical address space and one or more contiguous ranges of addresses related to the physical address space, wherein said mapping is provided with the help of one or more mapping trees, each tree assigned to a separate logical group in the logical address space.