Abstract: Serial number based storage device allocation is disclosed. A serial number associated with the storage device is mapped to a device file associated with the storage device on a host having a connection to the storage device. The serial number is mapped to a device address by which the storage device is known to a library with which the storage device is associated. A request requiring that an available storage device be allocated to service the request is received. The storage device is allocated, based at least in part on the serial number to device file and serial number to device address mappings, to service the request.

Abstract: A conventional serial communications protocol that is limited to supporting only host-to-slave communications, such as SATA or SAS, is extended to support peer-to-peer communications, e.g., by adding a memory-map layer into the conventional protocol stack between the link layer and the protocol layer. The addition of the memory-map layer enables two (or more) non-host devices (i.e., peer devices) to communicate with one another without using a host computer and without relying on conventional protocol-bridging techniques.

Abstract: A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a set of garbage collection instructions configured to perform one or more garbage collection barrier operations and a subsequent instruction that immediately follows the garbage collection instruction; wherein the processor is configured to execute the set of garbage collection instructions, including by: evaluating a memory reference to determine a condition associated with the set of garbage collection instructions; and in the event that the condition is met, while maintaining the same privilege level, saving information that is based at least in part on the current value of a program counter, and setting the program counter to correspond to a target location that is other than the location of the subsequent instruction.

Abstract: A performance monitoring device and method are disclosed. The device monitors performance events of a processor. A counter is adjusted in response to the occurrence of a particular performance event. The counter can be associated with a particular instruction address range, or a data address range, so that the counter is adjusted only when the performance event occurs at the instruction address range or the data address range. Accordingly, the information stored in the counter can be analyzed to determine if a particular instruction address range or data address range results in a particular performance event. Multiple counters, each associated with a different performance event, instruction address range, or data address range, can be employed to allow for a detailed analysis of which portions of a program lead to particular performance events.

Abstract: A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.

Abstract: A serial in random out memory circuit has a number of memory cells integrated with write control circuitry for writing a sequence of data inputs to sequential locations in the memory cells. Read control circuitry is integrated to receive address signals from an external device and provide a random access read output from the memory cells, mapped into an address range of the external device. Compared to circuits using discrete components and conventional RAM chips, the integrated SIRO can enable some of the circuitry or external software to be dispensed with and so reduce costs or increase performance. The memory cells can be arranged in a number of blocks, selectable one at a time for mapping to the external device address range.

Abstract: Provided are a computer program product, system and method for managing Input/Output (I/O) requests to a storage device. A write request is received having write data for a logical address in the storage device. A determination is made as to whether preserve mode is enabled. A first entry is located in a volume control table for the logical address indicating a version number of the data in the storage device for the logical address and a first physical location in the storage device having the data for the logical address. The write data is written to a second physical location in the storage device. A second entry is added to the volume control table for the logical address to write in response to determining that the preserve mode is enabled.

Abstract: A controller of a storage device having a user area storing an operating system, the storage device developing the operating system stored in the user area on a host device in accordance with an access from the host device. The controller includes a user authentication routine storage controlling unit that stores a user authentication routine for executing user authentication before startup of the operating system, in a predetermined area inside the user area, and an access controlling unit that permits access to the predetermined area from the host device when the user authentication routine is used, while prohibiting access to the predetermined area from the host device when the user authentication routine is not used.

Abstract: A storage device for storing data, while compressing same value of input data, includes an input processing unit, a data storage, a first-in-first-out memory, and an output processing unit. The input processing unit is configured to, upon receiving an input value, determine whether a data value stored in the data storage at an address location corresponding to the input value is valid. If the data value is invalid, the input processing unit stores an initial value at the address location and stores the input value in the first-in-first-out memory. If the data value is valid, the input processing unit performs an arithmetic operation on the data value and stores the operation result in the address location corresponding to the input value.

Abstract: A disk formatter (DF) for a rotating storage medium includes a target sector identification module that determines a block of target sectors of the rotating storage medium based on a read/write command signal. A current sector identification module determines a current sector of a read/write head. A DF control module begins a read/write operation at a command start sector that is different than a first sector of the block of target sectors. The command start sector is located within the block of target sectors.

Abstract: A host interface module includes a millimeter wave transceiver that is coupled to wirelessly communicate read commands, write commands, read data and write data between a flash memory device and a host device over a millimeter wave communication path in accordance with a host interface protocol. A protocol conversion module is coupled to convert the read commands, the write commands and the write data from the host interface protocol and to convert the read data to the host interface protocol. A host module is coupled to decode the read commands and the write commands from the host device, to process the read commands to retrieve the read data from the flash memory and to process the write commands to write the write data to the flash memory.

Abstract: A system is provided to ensure a timely secure data erase by determining whether allocating an additional tape drive would improve secure data erase performance by evaluating a quantity of physical volumes to be secure data erased, a maximum queued threshold, an average time to an erasure deadline and a minimum expiration threshold. An additional tape drive is allocated for the secure data erase process when it is determined that allocating an additional tape drive would improve secure data erase performance.

Abstract: A method and computer program product are provided to ensure a timely secure data erase by determining whether allocating an additional tape drive would improve secure data erase performance by evaluating a quantity of physical volumes to be secure data erased, a maximum queued threshold, an average time to an erasure deadline and a minimum expiration threshold. An additional tape drive is allocated for the secure data erase process when it is determined that allocating an additional tape drive would improve secure data erase performance.

Abstract: A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part.

Abstract: Provided are an apparatus and method for partially accessing a DRAM. The apparatus for partially accessing a DRAM includes a memory controller. The memory controller includes a first sub-controller which controls a first DRAM and a second sub-controller which controls a second DRAM. Accordingly, a garbage cycle, i.e., an operation which wastes data transfer bandwidth, that may generate when a related art DRAM accessing apparatus is used, is removed.

Abstract: A method and apparatus for distributed parallel messaging in a parallel computing system. The apparatus includes, at each node of a multiprocessor network, multiple injection messaging engine units and reception messaging engine units, each implementing a DMA engine and each supporting both multiple packet injection into and multiple reception from a network, in parallel. The reception side of the messaging unit (MU) includes a switch interface enabling writing of data of a packet received from the network to the memory system. The transmission side of the messaging unit, includes switch interface for reading from the memory system when injecting packets into the network.

Abstract: A multi-protocol serial interface (MPSI) apparatus can include a controller circuit that is configured to receive information about a type of MPSI utilized for data transfer and that is configured to control a format of the data transfer and input/output timing associated with the data transfer. A data generation and processing circuit is coupled to the controller circuit and is configured to extract information from a buffer memory to generate data for the data transfer according to the format based on the information and is configured to generate the data in a packet format or a bit format based on the information.

Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract: Information handling system network addresses are managed to support a consistent MAC address for iSCSI and fiber channel host bus adapter. For example, a management controller retrieves a MAC address from persistent memory, such as a network location, and assigns the MAC address to a non-persistent memory of a predetermined information handling system network component so that the MAC address remains consistent even if the network component is replaced. For example, an offload engine that supports network communications with iSCSI receives a MAC address from a network location and applies the MAC address for use by a host bus adapter. Alternatively, an offload engine supports Fiber Channel with World Wide Name or World Wide Identifier address assignments.

Abstract: A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute only on a single computer. The local memory of each computer is maintained substantially the same by updating all computers with every change made to addressed memory locations. Contention can arise when the same memory location is substantially simultaneously updated by two or more machines because of transmission delays and latency of the communications network interconnecting all the computers. In particular a method of detecting contention is disclosed which utilizes a count value indicative of the number of the sequence of occasions on which each memory location has been updated. Contention is indicated if the currently stored count value and the incoming updating count value are the same.

Abstract: A method for protecting digital information includes: converting a protected address range into a plurality of address blocks based on a preset conversion unit, and generating an address block rearranging rule using the address blocks as a parameter; when it is desired to load data into an address batch of the protected address range, converting the address batch into a plurality address blocks based on the conversion unit; and locating rearranged addresses of the address blocks in the protected address range according to the address block rearranging rule, and loading the data into the rearranged addresses. Thus, the data can be stored in the address batch scatteredly, and the protected data cannot be recomposed into the original correct data when stolen.

Abstract: A system and method to reduce external access to hypervisor interfaces in a computer system, thereby reducing the possibility of attacks. In a preferred embodiment, addresses for calls are used to fill a table, where the addresses are specifically selected for a requesting computer. For example, in one embodiment, a routine searches for the adapter type of a requesting computer and populates the table with calls specific to that type of adapter. Other types of calls are not put in the table. Instead, those calls are replaced by routines that will return an error. In other embodiments, the operating system type is used to determine what addresses are used to populate the table. These and other embodiments are explained more fully below.

Abstract: A method (and system) for emulating a target system's memory addressing using a virtual-to-real memory mapping mechanism of a host multiprocessor system's operating system, includes inputting a target virtual memory address into a simulated page table to obtain a host virtual memory address. The target system is oblivious to the software it is running on.

Abstract: A memory controller includes a memory capacity setting circuit and an address selecting circuit. The memory capacity setting circuit is configured to set a valid memory capacity of a memory device based on a defective cell information signal, and generate a valid memory capacity signal based on the valid memory capacity. The address selecting circuit is configured to disable an address signal corresponding to a memory block having a defective cell, and generate a selection address signal based on the valid memory capacity signal and the disabled address signal. A non-defective cell in a memory cell array is activated based on the selection address signal and a command signal.

Abstract: According to an example embodiment, a method of changing a block size in a flash memory device having a multi-plane scheme may include decoding an external input address and changing the block size of the flash memory device from a first block size to a second block size. The external input address may be decoded into a block address and a page address. The block size of the flash memory device may be changed from the first block size to the second block size by shifting at least one bit of the block address to the page address or shifting at least one bit of the page address to the block address.

Abstract: A portable storage device including a microprocessor and a secure user data area, the microprocessor operable to perform on-the-fly encryption/decryption of secure data stored on the storage device under a user password, the microprocessor also operable to exclude access to the secure user data area unless the user password is provided.

Abstract: A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.

Abstract: A device comprising a file management system that includes a plurality of first entries and second entries. The first entries are configured function as a logical block address mapping table for data searching operations on data files stored in data blocks of the device, and the second entries are configured to organize the plurality of data blocks into separate logical groups.

Abstract: Methods, systems, and products for computer processing. In one general embodiment, the method comprises running an inner process in the context of an executing thread wherein the thread has an original address space in memory and hiding at least a portion of the memory from the inner process. The inner process may run on the same credentials as the thread. Running the inner process may include creating a new address space for the inner process in the memory and assigning the new address space to the thread, so that the inner process comprises its own address space. The inner process may he allowed to access only the new address space. The kernel may maintain the thread's original address space along with the new address space, so that multiple address spaces exist for a particular thread. The kernel may pass selected data from the thread to the inner process.

Abstract: A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits whereby these address bits are transformed by transforming logic. This transforming logic may include adders. Transforming logic may alternately include comparators or exclusive-or circuits. Transforming logic comprising adders may include overflow carry bits that are discarded, ignored, or otherwise not used or the overflow logic may be omitted altogether.

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract: A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.

Abstract: A system and method for sending a cache line of data in a single message is described. An instruction issued by a processor in a multiprocessor system includes an address of a message payload and an address of a destination. Each address is translated to a physical address and sent to a scalability interface associated with the processor and in communication with a system interconnect. Upon translation the payload of the instruction is written to the scalability interface and thereafter communicated to the destination. According to one embodiment, the translation of the payload address is accomplished by the processor while in another embodiment the translation occurs at the scalability interface.

Abstract: In the described embodiments, a computer constructs a dispatch data structure for a holder by first determining a set of member holders from which the holder inherits. The computer then constructs an “i-table” that includes holder addressor regions that each contains addressors for an associated set of members. Each of the holder addressor regions is associated with an i-table index. The computer next collects a set of identification numbers for the set of member holders and, from these, constructs an “m-table.” The size of the m-table is selected to perfectly hash the set of identification numbers by the m-table size. The computer then computes an m-table index for each of the set of identification numbers modulo the m-table size and uses the m-table index to populate the m-table. The computer next stores the i-table index in the m-table in accordance with the m-table index.

Abstract: A computer addressing mode and memory access method rely on a memory segment identifier and a memory segment mask for indicating memory locations. In this addressing mode, a processor receives an instruction comprising the memory segment identifier and memory segment mask. The processor employs a two-level address decoding scheme to access individual memory locations. Under this decoding scheme, the processor decodes the memory segment identifier to select a particular memory segment. Each memory segment includes a predefined number of memory locations. The processor selects memory locations within the memory segment based on mask bits set in the memory segment mask. The disclosed addressing mode is advantageous because it allows non-consecutive memory locations to be efficiently accessed.

Abstract: Methods and apparatus relating to dynamic selection of execution stage are described. In some embodiments, logic may determine whether to execute an instruction at one of a plurality of stages in a processor. In some embodiments, the plurality of stages are to at least correspond to an address generation stage or an execution stage of the instruction. Other embodiments are also described and claimed.

Abstract: A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.

Abstract: Techniques for writing to memory using shared address buses. A memory device that includes a plurality of memory arrays connected to a common address bus, the common address bus used to broadcast memory addresses simultaneously to the plurality of memory arrays. Each memory array includes a plurality of memory locations and circuitry for: receiving the broadcasted memory addresses from the address bus; selecting a memory address in the memory array from a list of most recent memory addresses received from the address bus; and performing a memory access at the selected memory address, such that at a given point in time at least two of the memory arrays perform the memory access at a different broadcasted address when the memory access is a write.

Abstract: In a virtual computer system, the invention virtualizes a primary protection mechanism, which restricts memory accesses based on the type of access attempted and a current hardware privilege level, using a secondary protection mechanism, which is independent of the hardware privilege level. The invention may be used to virtualize the protection mechanisms of the Intel IA-64 architecture. In this embodiment, virtual access rights settings in a virtual TLB are translated into shadow access rights settings in a hardware TLB, while virtual protection key settings in a virtual PKR cache are translated into shadow protection key settings in a hardware PKR cache, based in part on the virtual access rights settings. The shadow protection key settings are dependent on the guest privilege level, but the shadow access rights settings are not.

Abstract: A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are redistributed among the extended set so as to cause some logical addresses to be transferred from the devices in the initial set to the additional device. There is substantially no transfer of the logical addresses among the initial set. If a surplus device is removed from the initial set, forming a depleted set, the logical addresses oldie surplus device are redistributed among the depleted set. There is substantially no transfer of the logical addresses among the depleted set. In both cases the balanced access is maintained.

Abstract: Disclosed is a method implementable by a computer system for maintaining consistency between mirrors of a mirrored data volume. In one embodiment, the method includes the computer system generating first and second write transactions in response to the generation of transaction to write data to a mirrored data volume. The first and second write transactions comprise first and second tags, respectively. The first and second tags relate the first write transaction to the second write transaction. In one embodiment, the first and second tags are identical. After the first and second write transactions are generated, the computer system transmits the first and second write transactions to first and second storage subsystems, respectively. In one embodiment, the first and second storage subsystems store or are configured to store respective mirrors of the data volume.

Abstract: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

Abstract: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.

Abstract: A method of modifying data sequences in a memory system comprises receiving program data having a first data sequence, and determining whether the received first data sequence matches one of “m” predefined sequences stored in the memory system. The method further comprises replacing the received first data sequence with a replacement sequence upon determining that the received first data sequence matches one of the “m” predefined sequences, and outputting the replacement sequence from the memory system. The replacement sequence typically comprises pattern bits indicating a pattern of the first data sequence and location bits indicating a start location of the first data sequence.

Abstract: The present invention is directed to a method and apparatus for updating running processes. In particular, a jump instruction is injected into the first instruction line of a function that has been updated. The jump instruction redirects the program to a location within a jump table containing the address of the first instruction of an updated function. Injection of the jump instruction can be made without stopping execution of the application, thereby allowing a patch to be installed without interrupting application services.

Abstract: Verifying operation of a data processing system. A first sequence of addressing ranges is generated for multiple requesters. Each addressing range includes a start and an end address and a respective identifying number. A second sequence of verification ranges is generated corresponding the addressing ranges of the first sequence. Each verification range includes a start and an end address and specifies at least one allowed value including each respective identifying number of all of the addressing ranges that overlap the verification range. A respective accessing activity executing on each requestor accesses each addressing range in the first sequence. The accesses include writing the respective identifying number of the addressing range to at least one address of the addressing range. A verification activity executing on a requestor reads a value from each address of each verification range of the second sequence and outputs an error message in response to the value not matching the allowed value.

Abstract: A dispersed storage network utilizes a virtual address space to store data. The dispersed storage network includes a processing unit operable to slice a data segment of a data object into data slices and create a slice name for each of the data slices. The slice name includes an identifier of the data object and a virtual memory address of a virtual memory associated with the dispersed storage network. The processing unit further outputs each of the data slices and the respective slice names to a corresponding storage unit for storage of the data slices therein.

Abstract: In computer system simulations, previous translations of simulation virtual addresses to physical host addresses can be remembered in a cache. During execution of a simulation program, the simulated computer system generates a simulation virtual address. The simulation virtual address may be translated to a host address. Information associated with the translation can be cached, and subsequent accesses to the simulation virtual address can use the cached information to compute the host address.

Abstract: A method and system where a hardware platform such as a disk drive is formatted to the largest block length it is desired to read from or write to. Using commands, data can be accessed from the drive in any block length that is equal to or less than the formatted block length.