Abstract: Dynamic logical mapping (“DLM”) provides a virtual layer interposed between a host and a data storage library. Residing on the library, DLM creates a data storage map that records and manages the relationship between a storage cartridge's physical address and that cartridge's mapping to a logical address. During runtime of the data storage library, DLM manages the physical to logical address mapping of each storage cartridge so as to optimize efficiency and speed of the data storage library.

Abstract: A method and apparatus for performing a burst access operation for a memory device. The method includes receiving a burst access command for the burst access operation and receiving a burst length modifying value for the burst access operation. A modified burst length is generated from a pre-programmed burst length using the burst length modifying value. The modified burst length is used for the burst access operation without changing the pre-programmed burst length. The burst access operation is performed with the modified burst length.

Abstract: A flash memory information read/write method in which an external resource such as host, external memory, EEPROM, or external controller is used to read and update new flash memory information after fabrication of a flash memory device, enabling the new flash memory information to be written in a predetermined address in a flash memory module of the flash device by a controller of the flash memory device, so that every flash memory device that has an erroneous or damaged factory data or information is still usable, and the flash memory controller provider needs not to continuously develop new firmware controllers for different flash memories.

Abstract: Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The random access memory device may include a local memory address space and a global memory address space. The local memory address space may be accessible to the one or more CPUs of the node that comprises the random access memory device. The global memory address space may be accessible to CPUs of all the nodes. The parallel link input/output port may be configured to send data frames to, and receive data frames from, the global memory address space comprised by the random access memory device(s) of the other nodes.

Abstract: The present invention discloses a computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code including: program code for interleaving fast-reading data and filler data in fast pages and slow pages, respectively. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code including: program code for reconstructing a data object from data stored only in designated pages. Preferably, the designated pages are fast pages or slow pages. A computer-readable storage medium having computer-readable code embodied on the computer-readable storage medium, the computer-readable code including: program code for at least one data object configured to be stored in fast pages and slow pages, wherein initial pages of at least one data object are stored only in primary pages, and the subsequent pages of at least one data object are stored only in secondary pages.

Abstract: Data transfer is performed to and from a host computer using a first block as the minimum unit. Data transfer is performed to and from a storage area using a second block as the minimum unit. A second block set of the storage area stores data obtained from performing data conversion processes that change the size of the data itself, with a first block set as the unit. Here a correspondence relationship is generated between the first block set and the second block set. In response to a read request from the host computer, a second block set, which corresponds to the first block set that includes the first block that is requested, is read, a reverse-conversion process is performed, and the data is sent to the host computer.

Abstract: The invention relates to a method for generating an identification data block (ID) for a data carrier (41), which data carrier (41) has a multiplicity of logical data blocks (300) continuously numbered with respective block numbers in a data block size, a reading of the data of the logical data blocks is carried out and the generating of the identification data block (ID) is carried out by means of a combining function from read first data of a logical first data block (301) defined by a first block number and from read second data of a logical second data block (302) defined by a second block number, wherein the logical second data block defined by the second block number is determined in dependence on the read third data of a logical third data block (303) defined by a third block number.

Abstract: A computer-implemented method for performing structure layout optimization of a data structure in a multi-threaded environment is provided. The method includes determining a set of code concurrency values. The method also includes calculating a set of cycle gain values. The method further includes employing the set of cycle gain values and the set of code concurrency values to create a field layout graph, which is configured to illustrate relationship between a set of data fields of the data structure. The method yet also includes employing a cluster algorithm to the field layout graph to create a set of clusters. Each cluster of the set of clusters is employed to generate a cache line.

Abstract: A method for accessing a memory is provided. The method includes entering a memory accessing mode for updating a top of low memory (TOLM) value stored in a TOLM register in a chipset of a system with a highest memory address when a memory accessing command is received. The memory accessing command requests the utilization of a memory block in a memory of the system corresponding to an address space occupied by a memory-mapped input output (MMIO) function. The system then accesses the corresponding memory block in the memory according to the address space recorded in the memory accessing command. After the access is completed, the memory accessing mode is closed and the original TOLM value is written back to the TOLM register. Therefore, the present invention can access the “MMIO memory block” to prevent a waste of the memory.

Abstract: An edge router (Broadband Remote Access Server) and a method are described herein that obtain a Media Access Control (MAC) address of an end device (consumer premises equipment). Once, the edge router obtains the MAC address of the end device then it can use Ethernet Operation, Administration and Maintenance (OAM) tools to troubleshoot the end device.

Abstract: User data are stored in a memory that includes one or more blocks of pages by, for one of the blocks, and optionally for all of the blocks, whenever writing any of the user data to that block, writing the block according to a predefined plan for specifying, with respect to each page of that block, a portion of the user data that is to be written to that page. Alternatively or additionally, each page that stores user data has associated therewith a metadatum related to the age of the user data stored therein; and, for one of the blocks, at any time that two or more of the pages of that block store user data, a common value of the metadatum is associated with all such pages.

Abstract: The present invention discloses systems for managing files according to application. A digital storage system including: a storage memory having program code configured: to identify an application identity of an application issuing a storage command to access a file; and to adjust a storage mode of the file according to the application identity; and a processor for executing the program code. Preferably, the identifying is performed using a PID that is an indicator of the application identity. Preferably, the adjusting includes adjusting the storage mode according to the storage command. Preferably, the adjusting is performed using an SAT and/or an AST. A digital storage system including: a storage memory having program code configured: to identify an application scenario associated with a storage command to access a file; and to adjust a storage mode of the file according to the application scenario; and a processor for executing the program code.

Abstract: A non-volatile memory may include a plurality of map blocks for storing a plurality of map units, the map units representing mapping information between physical addresses and logical addresses. A storage device may include such a non-volatile memory. A method of mapping such a non-volatile memory may include writing historical information regarding locations of valid map units among the map units included in map blocks previously allocated among the map blocks when a new map block among the map blocks is allocated, the valid map units representing valid mapping information, and constructing a map table including all of the valid mapping information based on the historical information and a result of searching a map block recently allocated among the map blocks.

Abstract: The correspondence between logical addresses and physical addresses is determined so that the logical addresses in ascending order may be assigned to the physical addresses in ascending order with the physical addresses of defective blocks in a memory skipped. Then, the physical addresses of the defective blocks in ascending order are sequentially stored into the second blocks in ascending order of the physical addresses of the second blocks, respectively. To obtain a physical address from a logical address, a target block is retrieved out of a plurality of second blocks on the basis of the logical address, and the physical address of the target block is added to the logical address to obtain the physical address. Thus, it is possible to reduce the required capacity of a reserve storage region used for conversion of logical addresses into physical addresses without deteriorating the access speed.

Abstract: A storage controller of the present invention writes data to a storage device, in which the storage unit is fixed, at a size that is larger than this storage unit, and curbs response performance degradation. A host sends write-data in a prescribed number of logical blocks in accordance with a basic I/O size defined at initialization. A controller respectively creates a guarantee code for each logical block, and appends same to the write-data. Write-data, to which a guarantee code has been appended, is stored in another prescribed number of logical blocks in accordance with a basic disk access size which is set at a value corresponding to the basic I/O size, and sent to a storage device. When an unused part is also stored in the storage device, the utilization efficiency of the storage area decreases, but the need to read out data located before and after data targeted for updating at data write is eliminated, thereby curbing the degradation of response performance.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address.

Abstract: Data files are assigned addresses within one or more logical blocks of a continuous logical address space interface (LBA interface) of a usual type of flash memory system with physical memory cell blocks. This assignment may be done by the host device which typically, but not necessarily, generates the data files. The number of logical blocks containing data of any one file is controlled in a manner that reduces the amount of fragmentation of file data within the physical memory blocks, thereby to maintain good memory performance. The host may configure the logical blocks of the address space in response to learning the physical characteristics of a memory to which it is connected.

Abstract: Data files are assigned addresses within one or more logical blocks of a continuous logical address space interface (LBA interface) of a usual type of flash memory system with physical memory cell blocks. This assignment may be done by the host device which typically, but not necessarily, generates the data files. The number of logical blocks containing data of any one file is controlled in a manner that reduces the amount of fragmentation of file data within the physical memory blocks, thereby to maintain good memory performance. The host may configure the logical blocks of the address space in response to learning the physical characteristics of a memory to which it is connected.

Abstract: Data files are assigned addresses within one or more logical blocks of a continuous logical address space interface (LBA interface) of a usual type of flash memory system with physical memory cell blocks. This assignment may be done by the host device which typically, but not necessarily, generates the data files. The number of logical blocks containing data of any one file is controlled in a manner that reduces the amount of fragmentation of file data within the physical memory blocks, thereby to maintain good memory performance. The host may configure the logical blocks of the address space in response to learning the physical characteristics of a memory to which it is connected.

Abstract: Data files are assigned addresses within one or more logical blocks of a continuous logical address space interface (LBA interface) of a usual type of flash memory system with physical memory cell blocks. This assignment may be done by the host device which typically, but not necessarily, generates the data files. The number of logical blocks containing data of any one file is controlled in a manner that reduces the amount of fragmentation of file data within the physical memory blocks, thereby to maintain good memory performance. The host may configure the logical blocks of the address space in response to learning the physical characteristics of a memory to which it is connected.

Abstract: A data storage device comprises storage media including physical data blocks. The data storage device comprises a storage circuit. The storage circuit compresses a user data block into a compressed user data block before storing the compressed user data in one of the physical data blocks, leaving an unused block portion of the physical data block. The data storage device comprises a remapping circuit that remaps the unused block portion to an opportunistic block address. The data storage device comprises a circuit that stores data in the unused block portion.

Abstract: A system architecture for storing and retrieving data includes a storage device organized in a plurality of blocks. There is provided at least one classifying circuit for organizing the data to be stored in classes according to their content, associating to the data thus organized class-of-content identifiers. The input information can hence be stored, according to the class-of-content identifiers, in memory blocks having appropriately set addresses. The data, with associated thereto a given class-of-content identifier, are stored in at least one corresponding block.

Abstract: A system and method for context-independent coding using frequency-based mapping schemes, sequence-based mapping schemes, memory trace-based mapping schemes, and/or transition statistics-based mapping schemes in order to reduce off-chip interconnect power consumption. State-of-the-art context-dependent, double-ended codes for processor-SDRAM off-chip interfaces require the transmitter and receiver (memory controller and SDRAM) to collaborate using the current and previously transmitted values to encode and decode data. In contrast, the memory controller can use a context-independent code to encode data stored in SDRAM and subsequently decode that data when it is retrieved, allowing the use of commodity memories. A single-ended, context-independent code is realized by assigning limited-weight codes using a frequency-based mapping technique. Experimental results show that such a code can reduce the power consumption of an uncoded off-chip interconnect by an average of 30% with less than a 0.

Abstract: A compiler includes a register allocator for allocating registers for instructions in a program to be compiled, and a code generator for generating object code based on the register allocation results performed by the register allocator. The register allocator allocates logical registers for instructions in the program to be compiled. The register allocation further allocates, to physical registers, the logical registers that are allocated to the instructions of the program, so that the physical registers that are live at a procedure call in the program to be compiled are allocated from the bottom of the register stack.

Abstract: A method is disclosed for accessing a target register of a plurality of registers. The method includes: receiving an instruction containing a register index field; and mapping the register index field to the target register access index for accessing the target register. A data accessing apparatus corresponding to this method is also disclosed.

Abstract: A system to locate a storage device. The system receives a request for a data item stored on a first and second storage device. The request includes a data identifier for the data item. Next, the system generates a start value and a step value based on the data identifier. Next, the system locates the first storage device utilizing the start value and identifies the first storage device is unavailable. Next, the system locates a second storage device utilizing a backup value that is generated based on the step value and the start value.

Abstract: A method and system for allocating storage space on a storage device to a requesting entity. The storage device includes a set of extents. An allocation map is maintained in computer memory. The allocation map has a plurality of map blocks, the map blocks each having a plurality of map entries. The map entries include respective logical extent identifiers, physical extent information and obsolete indicators. An invalid extent logical identifier represents a free extent and a valid extent identifier represents a prior allocated extent. An obsolete indicator marks a map entry as either current or obsolete. In one technique an extent allocation request is received from the requesting entity. A first map block is selected having a first map entry marked as obsolete. A second map block is selected having a second map entry not marked as obsolete. Physical extent information is copied from the second map entry to the first map entry. The logical extent identifier is assigned to the first map entry.

Abstract: An apparatus for aligning input data in a semiconductor device includes at least one alignment block and a decision block. The at least one alignment block is for aligning serial input data into groups of parallel data synchronized to at least one divided data strobe signal for increasing margin between the maximum and minimum tDQSS values. The decision block is for selecting one of the groups of parallel data as valid data in response to synchronization information generated for removing any invalid data in the serial input data resulting from a write gap.

Abstract: In one aspect, an apparatus for driving display data includes an address mapping unit which generates second address units by dividing gradation data displayed on a plurality of pixels in a display panel into a plurality of first address units that are in the form of an a×b matrix, and mapping addresses of the gradation data in each of the first address units into the form of a b×a matrix, wherein the plurality of the first and second address units are arranged in the form of an M×N matrix, wherein a, b, M and N are natural numbers, and a is greater than b. The apparatus further includes a memory unit which stores the second address units having the mapped addresses in the form of a b×a matrix as units in the form of an M×N matrix, a data output unit which receives the data in a×N columns output from the memory unit and outputs the data as data in b×N columns, and a source driver block which receives the data in the b×N columns and transmitting the data to the display panel.

Abstract: The present invention provides a method of establishing a hard disk physical partition. First of all, it selects a sector in which the head of the hard disk physical partition is located, and establishes a user available partition of the hard disk within the range of the hard disk physical volume from the sector, the other portion of the hard disk becomes a protected partition of the hard disk, finally constitutes one hard disk physical partition. After entering into the hard disk physical partition, only the user available partition can be accessed, the protected partition is invisible to the user. It can establish the different hard disk physical partition in the different position of the hard disk through selecting the sector where the head of the hard disk is located.

Abstract: A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

Abstract: A recording system records blocks of information on a record carrier according to a file management system. Data space on a partly and fragmented recorded record carrier (60-68) is managed as follows. The information includes a first type of information, such as video, and a second type, such a general purpose data. The first type has extent allocation requirements that include requiring an extent to accommodate a multitude of information blocks in a consecutive range of addresses and the extent to have at least a predetermined extent size. Data space is managed by selecting at least one partly recorded data area (67,63,68) of at least the extent size which data area contains information blocks (63) at recorded addresses, and subsequently creating a free data area (74) on the record carrier by moving the information blocks from the recorded addresses in the partly recorded data area to different addresses (73) outside the free data area (74) and correspondingly adapting the file management data.

Abstract: A system and method include receiving a telephone number corresponding to a unique pair of first and second parameters in which the first parameter corresponds to a device having a plurality of ports and the second parameter corresponds to one of the ports of the device. A storage includes units respectively corresponding to different first parameters with each unit respectively having a physical location in the storage. Each unit has members respectively corresponding to different second parameters with each of the second parameters respectively corresponding to a member of each unit. The parameters are determined using the telephone number. A physical location in storage of a unit corresponding to the first parameter is determined. The member corresponding to the second parameter of the unit which corresponds to the first parameter is then identified.

Abstract: A memory access apparatus for accessing a first memory and a second memory, includes: an address outputting unit configured to output a read address to at least one of the first and the second memories; an access request outputting unit configured to output a read request to at least one of the first and the second memories; a data information outputting unit configured to output an information on the data size, and an information on the address, of the read data; and a read data outputting unit configured to generate the read data to be output, from the data output from at least one of the first and the second memories in response to the read address and the read request.

Abstract: According to one embodiment, an information processing apparatus, a discrimination unit for discriminating whether a power supply mode is a battery or a AC power supply, a stop unit for stopping supply of power to each of a physical drives, a storing unit for storing a history of stopping the power supply, a canceling unit for temporarily canceling a duplexing state of the disk array if it is discriminated by the discrimination unit that the power supply mode is the battery, and a determination unit for determining a physical drive whose power supply is to be stopped, to average power supply stop counts of the respective physical drives in accordance with the power supply stop history information stored in the storing unit, wherein the supply of power to the physical drive determined by the determination unit is stopped by the stop unit.

Abstract: A network switching device includes multiple ports, multiple switching processors, and a table manager. The switching processors respectively have an address table, a output port specification module, an update requirement determination module, and a table update module. The output port specification module refers to a destination address in received data and the address table and specifies a output port for sending the data among the multiple ports. The update requirement determination module determines requirement for update of the address table with regard to a source address in the data. The table manager has an update detail acquisition module and an update request module. Upon determination of the requirement for update of the address table, the update detail acquisition module obtains an update detail of the address table from one of the switching processors. The update request module sends an update request to the switching processors, based on the update detail.

Abstract: The invention discloses a memory card control chip. The memory card control chip comprises a clock generator, a first memory card interface, and a control circuit. The clock generator generates a first clock signal and a second clock signal. The second clock signal is a spread spectrum clock signal. The first memory card interface is coupled to the clock generator and comprises a first clock signal pin and a plurality of first data signal pins. The first memory card interface is connected to a first memory card to be a data transmission interface of the first memory card. The first clock signal pin transmits the second clock signal. The control circuit is coupled to the first memory card interface and receives the first clock signal for performing the data accessing of the first memory card.

Abstract: A memory management apparatus and a related method thereof for accessing digital versatile disc(DVD)data stored in a memory device are disclosed. The memory management apparatus includes an address mapping module, coupled to a bus, for receiving a logic address from the bus and for generating a physical address according to the logic address, and an access control module, coupled to the address mapping module and the memory device, for accessing the digital versatile disc data according to the physical address.

Abstract: A memory system including a first and second of set of socket pads adapted for connection to memory module continuity pins. The memory system also includes a first indicator corresponding to the first set of socket pads. The memory system also includes a second indicator corresponding to the second set of socket pads. The first indicator is active and the second indicator is inactive when the first and second set of socket pads are empty. The first indicator is inactive and the second indicator is inactive when then first and second set of socket pads contain the continuity pins. The first indicator is inactive and the second indicator is active when the first set of socket pads contain the continuity pins and the second set of socket pads is empty.

Abstract: A method for providing synchronized updates to a data record in a data store, the data record including a plurality of data fields, each of the plurality of data fields having an initial field value, the method includes reading the data record from the data store into a data record in memory, each of the plurality of data fields of the data record in the data store having a corresponding data field in the data record in memory, the data fields in the data record in memory having inspectable and modifiable field values; identifying a set of relevant fields comprising at least one of an inspected field and a modified field of the data record in memory; in response to a determination that fields of the data record in the data store corresponding to each of the fields in the set of relevant fields has a value of its initial field value, updating the data record in the data store with the value of modified fields in the data record in memory.

Abstract: Times at which requests for a data read or data write from/to a logical volume are received are stored in memory as access times of a RAID group making up the logical volume. When a predetermined time has elapsed after the access time, a number of the hard disk drives according to the redundancy of the RAID group are set to a power saving mode. Assume there are first hard disk drives and second hard disk drives having shorter lifes and the RAID group exceeds a predetermined time after the access time. When the RAID group consists of only the first drives, a number of the first drives according to the redundancy of the RAID group are set to a power saving mode and when it consists of only the second drives, an arbitrary number of second drives are set to a power saving mode.

Abstract: A programmable system-on-chip (SOC) apparatus is disclosed. After connecting with a computer host, the apparatus temporarily stored boot loader codes into a volatile memory originally installed in the apparatus. Further, during the whole updating firmware procedure, no burner is required. Accordingly, the invention not only saves the hardware cost of both a non-volatile memory and the burner, but also simplifies the operation procedure.

Abstract: An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.

Abstract: A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.

Abstract: The contents of a RAM disk are copied to an image file in nonvolatile memory on power-down and copied back on reboot to provide an appearance of persistence. A locking method can use in-use tables to limit access to the same blocks of data in a RAM disk.

Abstract: Systems and associated methods provide a level of indirection between multiple host computers and multiple data storage resources, such as removable media data storage devices. At least one of the hosts is not provided with direct access to some of the removable media data storage devices. Instead, logical addresses are provided to the host computers, where the logical addresses can relate to physical addresses associated with the data storage resources. A data storage resource handle or logical proxy may be presented to a host, and a management layer determines whether the host receives access to physical data storage resources, or virtual resources that emulate the physical resources.

Abstract: The present invention is to provide a semiconductor memory card which enables continuation of processing, even when processing execution is interrupted due to interruption of voltage supply.

Abstract: Embodiments of the invention provide a falsification detection method which is capable of recognizing the substance of a falsification, applicable to not only a specific file system, but any arbitrary application writing data with a logical structure, usable in a standalone environment and able to prevent its performance from deteriorating even for a very large data size. In one embodiment, data stored in the storage medium employed in a disk drive is divided into meta information expressing a data structure and contents. At a step, time transients of the meta information are analyzed whereas, at other steps, time transients of the contents are analyzed. By analyzing the data at two stages in this way, replacement of a file and replacement of contents of the file can be detected whereas the substance of a falsification can be recognized in the case of a file system.

Abstract: A portable data storage device (1) comprising means (2, 4) for searching for data stored on an other device that match with a user set profile (3) of the data storage device (1) and means (5) for storing data matching with said profile (3) in the data storage device (1). Also a technical realization on the level of self organizing content entities is provided.