Abstract: A method for operating a memory (24) includes storing data in analog memory cells (32) of the memory by writing respective analog values to the analog memory cells. A set of the analog memory cells is identified, including an interfered cell having a distortion that is statistically correlated with the respective analog values of the analog memory cells in the set. A mapping is determined between combinations of possible analog values of the analog memory cells in the set and statistical characteristics of composite distortion levels present in the interfered memory cell. The mapping is applied so as to compensate for the distortion in the interfered memory cell.

Abstract: A memory device and a method for managing the memory device is provided. The memory device includes a flash memory including a plurality of pages, a non-volatile RAM storing a first mapping table between a physical page address and a logical page address for each page of the plurality of pages, and a volatile RAM storing a second mapping table between the physical page address and the logical page address for each page of the plurality of pages.

Abstract: Disclosed is a storage apparatus that extends endurance and reduces bit cost. A storage apparatus includes a controller and a semiconductor storage media that has a plurality of storage devices. The plurality of storage devices include a first storage device and a second storage device having an upper limit of an erase count of data smaller than that of the first storage device. Area conversion information includes correspondence of a first address to be specified as a data storage destination and a second address of an area in which data is to be stored. A rewrite frequency of stored data is recorded for each area.

Abstract: The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.

Abstract: A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.

Abstract: A method for establishing and maintaining a differential snapshot of a set of files stored on a volume is disclosed. The invention achieves processing time and disk space optimizations by avoiding copy-on-write operations for logically insignificant moves of blocks, such as the block rearrangements characteristic of defragmentation utilities. A file system enhancement enabling the passing of a block copy command from the file system to lower-level drivers, is used to inform the snapshotter that a block move operation is not logically meaningful. When the logically insignificant move is of a block whose data forms part of the data captured in the snapshot virtual volume, and when the move is to a block location that is functioning as logical free space, the snapshotter can simply modify its block bitmap and update translation table entries without needing to perform a copy-on-write.

Abstract: A storage system architecture comprises one or more volumes distributed across the plurality of nodes interconnected as a cluster. The volumes are organized as a striped volume set (SVS) and configured to store content of data containers served by the cluster in response to data access requests issued by clients. The content of each data container is apportioned among the volumes of the SVS to thereby improve efficiency and storage service provided by the cluster. Each data container is implemented on each of the volumes of the SVS as a sparse data container which stores data amongst sections of sparseness within the data container.

Abstract: In a memory module 100, an address generating circuit 120, using the highest order bit of a row address output by a memory controller 12, will generate a highest order bit BA2 of a bank address insufficient for the purpose of identification of a memory cell targeted for access, and will output the bit to SDRAM 110. An operating mode detector 130 detects the operating mode of the memory controller 12. A switch controller 40 will switch a switch 128 on the basis of the detected operating mode.

Abstract: A solid state storage system is disclosed including a memory area having a plurality of chips. The solid state storage system includes a micro controller unit (MCU) configured to utilize the number of deletions for logical blocks corresponding to logical block addresses when performing wear leveling on the memory area. The allocation of the logical block addresses can be performed using an interleaving process and a multi-plane method. The solid state storage system performs global wear leveling by which the lifespan of the cells of the chips can be uniformly managed.

Abstract: A distributed shared memory multiprocessor that includes a first processing element, a first memory which is a local memory of the first processing element, a second processing element connected to the first processing element via a bus, a second memory which is a local memory of the second processing element, a virtual shared memory region, where physical addresses of the first memory and the second memory are associated for one logical address in a logical address space of a shared memory having the first memory and the second memory, and an arbiter which suspends an access of the first processing element, if there is a write access request from the first processing element to the virtual shared memory region, according to a state of a write access request from the second processing element to the virtual shared memory region.

Abstract: An address space expansion method implemented by the electronic device which includes a storage unit, wherein the storage unit includes a first storage unit and a second storage unit, comprising: responding to the user operation to generate a target address; determining whether a address range of the target address is less than or equal to a predetermined address range, and generating a corresponding control signal; enabling the first storage unit or the second storage unit according to the generated corresponding control signal; acquiring a physical address corresponding to the target address and providing the physical address to the enabled storage unit according to the corresponding control signal and a predetermined converting rule; accessing and performing a reading/writing operation for data corresponding to the physical address of the enabled storage unit.

Abstract: An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.

Abstract: A wireless Universal Serial Bus (USB) host that optimizes the data transfer between the Wireless Host Controller Driver (WHCD) and the Wireless Host Controller (WHC). The data transfer between the WHCD and the WHC is optimized by reducing the overhead of data fragmentation. Higher performance without sacrificing memory and computation power is achieved with the optimization of the data transfer.

Abstract: Techniques for managing inodes of a file system are described herein. According to one embodiment, in response to a request received at the file system for committing a file to a storage, an inode data structure from a first inode pool of the file system is assigned to be associated with the file, where the first inode pool includes multiple inode data structures. A block pointer as a data member of the inode data structure is configured to link with a first block map, where the first block map includes multiple entries having one or more pointers linked with one or more data blocks for storing content of the file.

Abstract: A recording medium, such as a high-density and/or optical recording medium including segment information recorded thereon, and apparatus and methods for recording to and reproducing from the recording medium, in order to improve data protection, data management and/or reproduction compatibility. The recording medium may contain at least one segment area which is an area on the disc controlled by a plurality of valid PACs and if the designated segment areas overlap with one another, control information of the respective PACs which control the overlapped area may be applied to control the overlapped area.

Abstract: A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.

Abstract: Exploit nonspecific host intrusion prevention/detection methods, systems and smart filters are described. Portion of network traffic is captured and searched for a network traffic pattern, comprising: searching for a branch instruction transferring control to a first address in the memory; provided the first instruction is found, searching for a subroutine call instruction within a first predetermined interval in the memory starting from the first address and pointing to a second address in the memory; provided the second instruction is found, searching for a third instruction at a third address in the memory, located at a second predetermined interval from the second address; provided the third instruction is a fetch instruction, indicating the presence of the exploit; provided the third instruction is a branch instruction, transferring control to a fourth address in the memory, and provided a fetch instruction is located at the fourth address, indicating the presence of the exploit.

Abstract: A solid state storage device includes a main memory cell array and a sub-memory area. The main memory cell array stores data in a flash memory, whereas the sub-memory includes a non-volatile random access memory for storing data. The data storage speed of the non-volatile random access memory of the sub-memory area is faster than the data storage speed of the flash memory of the main memory cell area. The sub-memory area of the solid state storage device also stores address mapping information therein, so that the address mapping information does not have to be transferred to the main memory cell area and a portion of the main memory cell area does not have to be designated for a non-volatile memory for storing the address mapping information.

Abstract: A storage subsystem capable of processing time-critical control commands while suppressing deterioration of the system performance to a minimum. When various commands are received in a multiplex manner via the same port from plural host devices, the channel adapter of the storage subsystem extracts commands of a first kind from the received commands. Then, the adapter executes the extracted commands of the first kind with high priority within a given unit time until a given number of guaranteed activations is reached. At the same time, commands of a second kind are enqueued in a queue of commands. After the commands of the first kind are executed as many as the number of guaranteed activations, the commands of the second kind are executed in the unit time.

Abstract: A solid state storage system that evenly allocates data writing/erasing operations among blocks is presented. The solid state storage system includes a controller. The controller is configured to set a representative value that becomes a block allocation reference in accordance with predetermined information of blocks in a flash memory area. The controller is also configured to calculate a data value that becomes life time information according to the predetermined information in a current state for each block. The controller is also configured to determine a block where a deviation is generated between the representative value and the data value. The controller is also configured to allocate block where the deviation is generated as a new block where data is written.

Abstract: A method, apparatus, and system for maintaining corresponding relationships between at least one chat transcript and related chat content in an instant messaging system may include establishing a chat session in the instant messaging system. Corresponding chat content may be displayed synchronously according to a changed address of the chat content. The changed address of the chat content may be inserted into a chat transcript, and the chat transcript may be segmented into at least two segments to create a segmented chat transcript. The segmented chat transcript and corresponding relationship between the changed address of the chat content and corresponding chat transcript segments may be stored.

Abstract: A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.

Abstract: A size storage unit stores therein a block size of a memory element. A buffering unit executes buffer processing configured to store data received from a RAID (Redundant Arrays of Inexpensive/Independent Disks) controller into a buffer, and to write the data stored in the buffer into the memory element. A stripe-size receiving unit receives a stripe size that indicates a size of a unit of access at time of access to the memory element by the RAID controller. Writing processing is configured to write data received from the RAID controller into the memory element without executing the buffer processing by the buffering unit, when the stripe size is n times of the block size (n is a positive integer).

Abstract: The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.

Abstract: A switch connects and disconnects an input and output control device to and from an input and output device. The switch includes a storage unit that stores therein a translation table for use in translating a physical address used on a virtual machine that a guest operating system specifies as a direct memory access transfer destination to the input and output device, into a physical address used on a real machine; and an address translating unit that translates an address contained in a direct memory access request issued by the input and output device into a physical address used on the real machine by referring to the translation table.

Abstract: Provided are a method, system, and article of manufacture for managing metadata for data blocks used in a deduplication system. File metadata is maintained for files having data blocks in a computer readable device. Data block metadata is maintained for each data block in the computer readable device. The data block metadata for one data block includes a data block reference and content identifier identifying content of the data block. The file metadata for each file includes the data block reference to each data block in the file. A determination is made of an unreferenced data block in the computer readable device that has become unreferenced. Indication is made that the data block metadata for the determined unreferenced data block as unreferenced metadata. The data block reference of the unreferenced metadata is maintained in the computer readable device in response to determining that a includes the data block indicated in the unreferenced metadata.

Abstract: A device comprises a processor configured to execute a sequence of program instructions, a first storage configured to store a first memory address, a second storage configured to store a second memory address, a program counter configured to determine a memory address of program instructions to be executed, and a program counter manipulator configured to set the program counter to a value corresponding to a content of the second storage in response to the program counter reaching a value corresponding to a content of the first storage.

Abstract: A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.

Abstract: The present invention provides a data processing apparatus realizing reduced load on a host CPU and improved performance. An arithmetic unit includes an SIMD processor for processing a plurality of pieces of data by a single instruction, and a second CPU coupled to the SIMD processor via an arithmetic unit bus and controlling the SIMD processor. A host system includes a host CPU for controlling the entire data processing apparatus, a built-in memory and a peripheral circuit coupled to the host CPU via a first bus, and a peripheral circuit coupled to a second bus. The second CPU accesses an external flash/ROM via the arithmetic unit bus and the first bus, and the SIMD processor accesses an external memory via the second bus. Therefore, the load on the host CPU can be reduced, and the performance of the entire apparatus can be improved.

Abstract: A method, computer program product and computer system for virtualizing an SAS storage adapter, so as to allow logical partitions of a computer system to share a storage device. The method, computer program product and computer system includes assigning a logical storage adapter to an operating system of each of the logical partitions; creating a mapping from each of the logical partitions to a set of logical blocks in the storage device; and configuring the logical storage adapter using a hypervisor, so that a select partition can access a select set of logical blocks that the select partition is allowed to access.

Abstract: A data processing system is provided with a memory controller (130) converting memory addresses (170) into selecting signals (120) for a memory device (100). The mapping between memory addresses and selecting signals is provided by mapping logic (140) within the memory device. The configuration of the mapping logic, also known as a mapping scheme, is defined by data stored in mapping specifying data storage (150), which may be altered by operating system software or application software (160) running on the system. Altering this configuration may be as a result of signals received from a monitoring unit (135) which monitors the efficiency with which the current mapping scheme is accessing data stored in the memory device. More than one mapping scheme may be used within a single memory device.

Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

Abstract: A method for data management in a flash memory medium is provided in the present invention, The method comprises the following steps: dividing a plurality of blocks of the flash memory medium into two or more sections; generating a section-address-mapping table by scanning logic addresses in the blocks in each section; storing the section-address-mapping table into a backup block in each section; and performing an operation of writing/reading by reading the section-address-mapping table, storing the section-address-mapping table to a RAM, and performing a conversion between a physical address and a logic address based on the section-address-mapping table stored in the RAM.

Abstract: A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space.

Abstract: A memory controller and a method for improved computer system performance invalidates (i.e., cancels or does not allow for execution of) speculative or unnecessary scrub write commands as part of the periodic execution of the overall scrub command upon the occurrence of certain events, such as if the error checking and correction (ECC) operation indicates that the data were received without error or if the ECC operation indicates that the data received have an uncorrectable error.

Abstract: A method and apparatus for digital forensics are provided. The apparatus for digital forensics includes a page file extractor for extracting a page file stored in a target storage medium, a stored-page feature extractor for extracting features of pages stored in the extracted page file, a page classifier for comparing the extracted features of the pages with at least one predetermined classification criterion and classifying the pages according to the comparison results, and a digital forensics unit for performing digital forensics according to the classified pages. According to the method and apparatus, it is possible to perform digital forensics using only information of a page file.

Abstract: A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank address and operative to supply the first bank address to one of the first and second ports and supply the second bank address to the other of the first and second ports; and a write data conversion circuit operative to convert input data fed from external into write data different from the input data and operative to supply the input data to one of the first and second ports and supply the converted write data to the other of the first and second ports.

Abstract: A method for reading and writing a memory having n rows and A columns includes a first step of writing data in 0th to (n?2)th rows by a first technique; a second step of writing data in (n?1)th row per column and reading data in the 0th section by a second technique; a third step of writing data in 0th to (n?2)th sections by a third technique and reading data in 1st to (n?1)th sections by the second technique, a fourth step of writing data in the (n?1)th section by the third technique and reading data in 0th row by a fourth technique; a fifth step of writing data in 0th to (n?2)th rows by the first technique and reading data in 1st to (n?1)th rows by the fourth technique; and a sixth step of returning to the second step.

Abstract: A distributed computing system that incorporates enhanced distributed storage and a universal address system and method are provided.

Abstract: A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system without a loss of memory space in the second memory system. Advantageously, the memory mapping system can be applied to hardware emulator memory systems to more efficiently map design memory systems into an emulation memory system during compilation.

Abstract: A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.

Abstract: The present invention relates to a digital audio layer and an audio content file management method of a digital audio player. This method writes address of an recording area containing descriptive information such as title of a song and a singer's name for each stored audio file in a file management information area for a corresponding audio file. Then, descriptive information can be directly searched and displayed more quickly using the written address if an audio file is selected.

Abstract: Current BD specification prescribes the following format for the ADIP: 24 bits, 3 of which to indicate the layer number, 19 for the RUB number, and 2 to be set to 00, 01 and 10 consecutively in the 3 successive ADIP words corresponding to one RUB that is the smallest partition of data that can be written on the disc. From this it derives that at most 32.2 GB of storage space can be addressed. Due to recent developments however, a storage capacity of 35 GB per layer could be achieved. A slight modification of the ADIP format is proposed, so as to allow an extension of the addressing space: the setting 11 for the two least significant bits is allowed, while the 19 bits no longer represent the RUB number. A drive will nevertheless convert the ADIP into a RUB number and vice versa, in a way which is transparent to a host device or application program.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.

Abstract: A method and system for processing generic formatted data, including first data describing a sequence of generic operations without any loops, in view of providing specific formatted data, for a determined platform including Q processor(s) and at least one memory, the platform configured to process, according, directly or indirectly, to specific formatted data, an object made up of elementary information of same type, each elementary information being represented by at least one numerical value.

Abstract: A mapping definition system for creating a mapping definition between a structured data definition of a conversion source and a structured data definition of a conversion target comprises: mapping information extraction means for extracting mapping information from an existing mapping definition and storing the same in a mapping information storage table; and mapping information application means acquiring mapping information necessary for conversion from the mapping information storage table and mapping information stored in the mapping information storage table for creating a mapping definition for the structured data definition of the conversion source and the structured data definition of the conversion target by using the acquired mapping information.

Abstract: Disclosed is a multi-channel flash memory system formed by flash memories having pages divided into sectors and accessed by corresponding channels. An interface device is configured to access the flash memories via the channels by a unit of at least one sector, wherein the interface device divides an address into a plurality of addresses of sector unit and controls the divided addresses so as to be jumped by a given size.

Abstract: Methods and apparatuses are provided that enable software designed to be operated with an embedded system to be tested in the absence of a physical embodiment of the embedded system. A simulation of the embedded system may be employed to operate the software. Various implementations of the invention provide for the processing of requests by the software to access memory within the embedded system. Still, various implementations of the invention provide for the identification of these memory access request and for the mapping of the desired memory location to a valid memory location.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.