Abstract: Systems, apparatuses, and methods for executing an instruction. The instruction includes fields for a first source operand, a second source operand, and a destination operand. A decoded instruction causes a reduction of broadcasted packed data elements of a first packed data source with a reduction operation and store a result of each of the reductions in a packed data destination, wherein the packed data elements of the first packed data source to be used in the reduction are dictated by a result of a comparison of broadcasted values of packed data elements stored in a second packed data source to the packed data elements stored in the second packed data source without broadcasting.

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

Abstract: A method for controlling a pipeline-based processor. The method includes determining a change in a workload. The method also includes activating or shutting down, by at least one controller circuit, one or more of the plurality of enhanced pipeline stages based on at least one corresponding enhanced stage priority level of the one or more of the plurality of enhanced pipeline stages and requirements for performance of the workload. The method additionally includes activating or shutting down, by the at least one controller circuit, one or more of the plurality of enhanced modules of the particular pipeline stage based on at least one corresponding priority level of the one or more of the plurality of enhanced modules of the particular pipeline stage and the requirements for the performance of the workload.

Abstract: A device may provide a user interface element for display in association with a displayed document that contains code. The user interface element may be associated with at least one adjustable state. The device may determine, based on a user interaction with the user interface element, a selected state of the at least one adjustable state of the user interface element. The device may generate information based on the selected state of the user interface element. The device may store the user interface element, the selected state of the user interface element, and the information in association with the document.

Abstract: In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.

Abstract: It is provided an information processing system. A first processing unit instructs a second processing unit to update the state management information regarding first data managed by the second processing unit when the first processing unit accesses the first data and detects an error regarding the first data, the second processing unit issues a command for discarding the first data acquired by a processing unit other than the second processing unit to the processing unit other than the second processing unit, when the processing unit which acquires the first data receives the command, the processing unit which acquires the first data discards the first data and transmits a result of the discarding of the first data to the second processing unit, and the second processing unit updates the state management information regarding the first data based on the result received from the processing unit which acquires the first data.

Abstract: In some aspects, a quantum computing system includes a control system and a quantum processor cell. The control system generates quantum processor control information for a group of devices housed in the quantum processor cell, and each device in the group has a distinct operating frequency. In some cases, a waveform generator generates a multiplexed control signal based on the quantum processor control information, and the multiplexed control signal is communicated an input signal processing system. In some cases, the input signal processing system includes an input channel configured to receive the multiplexed control signal, a de-multiplexer configured to separate device control signals from the multiplexed control signal, and output channels configured to communicate the respective device control signals into the quantum processor cell.

Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.

Abstract: A method including fetching information regarding a group of instructions, where the group of instructions is configured to execute atomically by a processor, including an encoding format for the information regarding the group of instructions, is provided. The method further includes processing the encoding format to interpret the information regarding the group of instructions.

Abstract: Techniques and mechanisms for exchanging control signals in a data path module of a data stream processing engine. In an embodiment, the data path module may be configured to form a set of one or more data paths corresponding to an instruction which is to be executed. In another embodiment, data processing units of the data path module may be configured to exchange one or more control signals for elastic execution of the instruction.

Abstract: A relevant-information providing method comprising in response to update of an application carried out in a system, storing, in a storage, difference information that is a difference between information on the application that has not been updated and information on the application that has been updated and modification information on management of the system modified as a result of the update, in response to acquisition of update information on a first application, extracting, from the stored difference information, a piece of difference information that is in a predetermined similarity relation with first difference information that is a difference between information on the first application that has not been updated and information on the first application that has been updated, and outputting a piece of the modification information corresponding to the piece of difference information that has been extracted.

Abstract: Aspects include acquiring measurement data of a synchronous input/output (I/O) link between an operating system and a recipient. The acquiring measurement data can include monitoring operating system usage of synchronous I/O commands on the synchronous I/O link and storing the operating system usage in a measurement block as the measurement data. Further, the measurement block is accessible by the operating system to determine that the measurement data is acquired.

Abstract: Aspects include acquiring measurement data of a synchronous input/output (I/O) link between an operating system and a recipient. The acquiring measurement data can include monitoring operating system usage of synchronous I/O commands on the synchronous I/O link and storing the operating system usage in a measurement block as the measurement data. Further, the measurement block is accessible by the operating system to determine that the measurement data is acquired.

Abstract: A method, non-transitory computer readable medium, and computing device that receives metadata for a block associated with an object from a source storage node. The metadata comprises a source object identifier and the object is associated with a source volume of a source aggregate owned by the source storage node. A determination is made when another block associated with the object has been previously received. A destination object identifier is obtained based on the source object identifier, when the determining indicates that the other block associated with the object has been previously received. A new aggregate block number is assigned to the block based on the destination object identifier and another portion of the metadata. Ownership of the source volume is transferred upon receipt of an indication of a cutover from the source storage node in order to migrate the source volume to a destination volume of a destination aggregate.

Abstract: A method for performing natural language processing includes receiving a primary text file. The received primary text file is scanned to determine a set of statistics related to a frequency at which various words of the primary text file follow other words of the primary text file. A probabilistic word generator is created based on the determined set of statistics. The probabilistic word generator generates synthetic text exhibiting the determined set of statistics. Synthetic text exhibiting the determined set of statistics is generated using the created probabilistic word generator. Word vectorization is performed on the synthetic text. Results of the performed vectorization are used to perform machine learning tasks.

Abstract: Modular network switches and other computer systems are described herein. A modular network switch can include a latching device for installing and removing computer modules (e.g., line cards) from an associated cabinet or enclosure. The network switch can also include interconnected computer modules (e.g., line cards, fabric cards, control modules, etc.) that include circuit boards oriented parallel to the flow of cooling air through the cabinet in the absence of a backplane or midplane oriented perpendicular to the air flow. The absence of such backplanes and/or midplanes provides a more direct air flow path through the cabinet, thereby enabling a more efficient flow of cooling air and lower operating temperatures. Additionally, the network switch can include an orthogonal arrangement of data planes, control planes, and/or power planes that can be efficiently interconnected to increase operational speed and further facilitate the flow of cooling air through the computer cabinet.

Abstract: A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core. The processing system further comprises a supervisor component arranged to receive the sets of internal state signals output by the processor cores of the first and second processing domains, compare internal state signals output by the processor core of the first processing domain to corresponding internal state signals output by the processor core of the second processing domain, and upon detection of a mismatch between compared internal state signals to initiate a reset of a thread under the execution of which the detected mismatch of internal state signals occurred.

Abstract: A logical merge module is described herein for producing an output stream which is logically compatible with two or more physically divergent input streams. Representative applications of the logical merge module are also set forth herein.

Abstract: A method of executing an algorithm in a parallel manner using a plurality of concurrent threads includes generating a lock-free barrier that includes a variable that stores both a total participants count and a current participants count. The total participants count indicates a total number of threads in the plurality of concurrent threads that are participating in a current phase of the algorithm, and the current participants count indicates a total number of threads in the plurality of concurrent threads that have completed the current phase. The barrier blocks the threads that have completed the current phase. The total participants count is dynamically updated during execution of the current phase of the algorithm. The generating, blocking, and dynamically updating are performed by at least one processor.

Abstract: An apparatus includes a device having n input ports and n output ports. The n input ports are configured to receive n corresponding physical objects of a physically processed, quantum redundancy coded state. The n output ports are configured to output the n physical objects in the physically processed, quantum redundancy coded state. The device is configured to measure bits of a syndrome of the physically processed, quantum redundancy coded state by passing the n physical objects through the device. The device is configured to measure a parity check bit for the measured bits of the syndrome by the passing the n physical objects through the device.

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract: Disclosed methods and systems are directed to natural language understanding cache usage. The methods and systems may include receiving a first natural language input comprising a set of one or more terms, and parsing the first natural language input to determine a first pretag result comprising a first string comprising at least one term from the set of one or more terms. The methods and systems may also determine that if the first pretag result corresponds to a key stored in a cache, then retrieve one or more cached NLU results corresponding to the at least one key. The methods and systems may also determine that if the first pretag result does not correspond to a key stored in the cache, then determine, based on the set of one or more terms, a first NLU result corresponding to the first natural language input.

Abstract: A method, system and computer-usable medium are disclosed for dynamic load based resource sets that provide flexible assignment of resources to processes with nested resource sets. Resource sets include plural resource subsets so that processes that are assigned to a resource subset can have additional resources flexibly made available by providing additional resources from a parent resource set. A resource threshold is monitored to selectively adjust process resource subset assignments based upon utilization of resources within a resource subset, such as by comparing the number of threads assigned to a resource subset with the number processors available to run the threads.

Abstract: Modular network switches and other computer systems are described herein. A modular network switch can include a latching device for installing and removing computer modules (e.g., line cards) from an associated cabinet or enclosure. The network switch can also include interconnected computer modules (e.g., line cards, fabric cards, control modules, etc.) that include circuit boards oriented parallel to the flow of cooling air through the cabinet in the absence of a backplane or midplane oriented perpendicular to the air flow. The absence of such backplanes and/or midplanes provides a more direct air flow path through the cabinet, thereby enabling a more efficient flow of cooling air and lower operating temperatures. Additionally, the network switch can include an orthogonal arrangement of data planes, control planes, and/or power planes that can be efficiently interconnected to increase operational speed and further facilitate the flow of cooling air through the computer cabinet.

Abstract: A method, computer program product, and computing system for defining a storage space having a defined capacity within a storage system. The storage system includes a frontend system and a backend system. A first portion of the storage space is located within the frontend system. A second portion of the storage space is located within the backend system. Usage of a data item stored within the storage space is monitored to identify a usage pattern. The data item is migrated to either the first portion of the storage space or the second portion of the storage space based, at least in part, upon the usage pattern.

Abstract: Embodiments here include systems and methods for running an application via a microvisor processor in communication with a memory and a storage is disclosed. For example, one method includes installing an application. The method also includes identifying an operating system that the application is configured to execute within. The method also includes identifying a resource required by the application to execute, wherein the resource is part of the operating system. The method also includes identifying a location of the resource in the storage. The method also includes retrieving the resource from the storage. The method also includes bundling the application and the resource in the memory. The method also includes executing the application using the resource.

Abstract: Methods and systems for a networked storage environment are provided. One method includes scanning a first data structure by a processor executing instructions out of a memory for a storage operating system to determine whether any data chunk of a first object stored at a first storage tier is referenced by the storage operating; when the storage operating system references a certain number of data chunks, the processor using an object staging data structure to identify a second object that is in the process of being built with space for transferring the certain number of data chunks from the first object to the second object; and updating information regarding the second object at a transfer log with location information of the certain number of data chunks at the first storage tier.

Abstract: Methods and apparatuses relating to a common architectural state presentation for a processor having cores of different types are described. In one embodiment, a processor includes a first core, a second core, wherein the first core comprises a unique architectural state and a common architectural state with the second core, and circuitry to migrate a thread from said first core to said second core, said circuitry to migrate the common architectural state from the first core to the second core, and migrate the unique architectural state to a storage external from the second core.

Abstract: What is disclosed is a system and method for determining a subject's respiratory pattern from a video of that subject. One embodiment involves receiving a video comprising N?2 time-sequential image frames of a region of interest (ROI) of a subject where a signal corresponding to the subject's respiratory function can be registered by at least one imaging channel of a video imaging device. The ROI comprises P pixels. Time-series signals of duration N are generated from pixels isolated in the ROI. Features are extracted from the time-series signals and formed into P-number of M-dimensional vectors. The feature vectors are clustered into K clusters. The time-series signals corresponding to pixels represented by the feature vectors in each cluster are averaged along a temporal direction to obtain a representative signal for each cluster. One of the clusters is selected. A respiratory pattern is determined for the subject based on the representative signal.

Abstract: A method at a mobile device for creating a managed domain on the mobile device, the method initializing a container on the mobile device to house the managed domain; retrieving, from the mobile device, a management agent for the management domain; establishing policies to govern the creation of the managed domain; and configuring the container for the domain based on the established policies.

Abstract: A trusted threat-aware microvisor may be deployed as a module of a trusted computing base (TCB) that also includes a root task module configured to cooperate with the microvisor to load and initialize one or more other modules executing on a node of a network environment. The root task may cooperate with the microvisor to allocate one or more kernel resources of the node to those other modules. As a trusted module of the TCB, the microvisor may be configured to enforce a security policy of the TCB that, e.g., prevents alteration of a state related to security of the microvisor by a module of or external to the TCB. The security policy of the TCB may be implemented by a plurality of security properties of the microvisor. Trusted (or trustedness) may therefore denote a predetermined level of confidence that the security property is demonstrated by the microvisor.

Abstract: A pipeline-based processor and method. The method includes partitioning a particular pipeline into one or more base pipeline stages and a plurality of enhanced pipeline stages, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced pipeline stage has an enhanced stage priority level. The method also includes configuring each enhanced pipeline stage to be activated or shut down based at least on the enhanced stage priority level. The method additionally includes partitioning a particular pipeline stage into at least one base module and a plurality of enhanced modules, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced module has a particular priority level. The method further includes configuring each enhanced module to be activated or shut down based at least on the particular priority level.

Abstract: Embodiments are directed to providing an extensible platform that allows users to select from and implement different types of media processors and to providing a management portal that allows users to manage their media processors. In one scenario, a computer system receives from a user a workflow with various tasks that are to be processed using a user-specified media processor. The computer system schedules computer system resources including a virtual machine on which the user-specified media processor is to be installed. The user-specified media processor includes a corresponding media processor installer. The computer system instantiates the scheduled virtual machine on the computer system, initiates the media processor installer to install the user-specified media processor on the instantiated virtual machine, and implements the installed media processor on the instantiated virtual machine to process the workflow tasks.

Abstract: Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the content of the addressed message only when the target address matches an address assigned to that logic block.

Abstract: Described herein are systems, methods and apparatus for decoding in-band on-channel signals and extracting audio and data signals. Memory requirements are reduced by selectively filtering a bit stream of data in the signal so that services of interest which are encoded therein are processed. A single pool of memory may be shared between physical layer and data link layer processing. Memory in this pool may be allocated dynamically between processing of data at the physical and data link layers. When the available memory is not sufficient to support the required services, the dynamic allocation allows for graceful degradation.

Abstract: Provided are an apparatus and method for multicore emulation based on dynamic context switching. The apparatus for multicore emulation based on dynamic context switching includes a multicore emulation managing unit configured to transmit a signal for requesting determination of a core to be emulated among a plurality of cores, and a context switching managing unit configured to receive the signal for requesting determination of a core to be emulated from the multicore emulation managing unit, determine an ID of a core to be emulated according to the received signal, and executing emulation on a core corresponding to the determined core ID.

Abstract: The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality of permute operations to arrange vector operands in desired locations of a register prior to performing vector operation, for example, a cross product. The permute instructions may be dependent on one another and may require the use of temporary registers. Embodiments of the invention provide a permute instruction wherein a mask field may be used to specify a particular location of a target register in which to transfer data, thereby reducing the number of instructions for arranging data, reducing dependencies between instructions, and the usage of temporary registers.

Abstract: A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.

Abstract: An apparatus and method provide power to perform functions on a computing device. In one example, the apparatus contains multiple processors that may operate at different power levels to consume different amounts of power. Also, any of the multiple processors may perform different functions. For example, one processor may be a low power processor that may control or operate at least one peripheral device to perform a low capacity function. Control may also switch from the low power processor to a high capacity processor. In one example, the high capacity processor controls the low power processor and further controls the at least one peripheral device through the lower power processor.

Abstract: A method of providing tailored add-on applications to an underlying foundational software suite that frequently receives updated versions that would otherwise overwrite changes in the foundational software that are required by the tailored add-on. Instead of functional changes to the foundation, the tailored add-on makes a fairly uniform and simple change in the place of each needed change, by inserting a call to an add-in definition object. The add-in definition object then contains code for performing the functionality needed by the add-on application. The add-in definition object is down-ported to all supported versions of the foundational software. The calls of the add-in definition object are integrated into the foundational software in a way which minimizes conflicts, allows for concurrent implementation while maintaining a clear separation between foundational code and modified code, and minimizes ongoing maintenance development of the add-on application's conflicts with the foundational application.

Abstract: In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline and may be configured to schedule instruction operations (ops) for execution in the respective execution pipeline. The sets of reservation stations coupled to each dispatch buffer may be non-overlapping. Thus, if a given op is to be executed in a given execution pipeline, the op may be sent to the dispatch buffer which is coupled to the reservation station that provides ops to the given execution pipeline.

Abstract: A motion estimation engine may be implemented to include a skip checking module, an integer search module, a macroblock partitioning module, a fractional search module, a bidirectional motion estimation refinement module, and an intra search module. The motion estimation engine may perform fractional search/bidirectional motion estimation refinement and intra search in parallel. Additionally, modules in the motion estimation engine may be partially or fully turned on or off to accommodate different motion estimation requirements. Furthermore, the motion estimation engine may implement early exit strategy to further save computation.

Abstract: A three-dimensional (3D) permute unit for a single-instruction-multiple-data stacked processor includes a first vector permute subunit and a second vector permute subunit. The first and second vector permute subunits are arranged in different layers of a 3D chip package. The vector permute subunits are each configured to process a portion of at least two input vectors. A first contact sub-field of the first vector permute subunit is configured to connect output ports of a first crossbar of the first vector permute subunit, holding an intermediate result of the first vector permute subunit, to a second contact sub-field of the second vector permute subunit. A first contact sub-field of the second vector permute subunit is configured to connect output ports of a first crossbar of the second vector permute subunit, holding an intermediate result of the second vector permute subunit, to a second contact sub-field of the first vector permute subunit.

Abstract: The present disclosure includes, in a heterogeneous system, receiving a desired speedup of an application as input and performing a static analysis and a dynamic analysis of the application. The dynamic analysis of the application comprises, identifying a set of parameters including, an end-to-end execution time of the application, an execution time of data parallel loops in the application, an execution time of non-data parallel loops in the application, and an amount of physical memory used by each data structure in each data parallel loop. Dynamic analysis also includes calculating and providing the feasibility of achieving the desired speedup of the application based on the identified set of parameters, and satisfaction of each of, an initialization invariant, a data-parallel invariant and a data transfer invariant.

Abstract: A power management system permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off. The power management system supports asynchronous domains with common shared peripherals. The asynchronous domains operate as a single entity while in a full power mode with the peripheral and system resources being shared. The system can be used in automotive systems where most of the system is power-gated leaving just a power regulator controller, some counters and an input/output segment alive for wakeup purposes.

Abstract: A microprocessor supports an instruction set architecture that specifies: processor modes, architectural registers associated with each mode, and a load multiple instruction that instructs the microprocessor to load data from memory into specified ones of the registers. Direct storage holds data associated with a first portion of the registers and is coupled to an execution unit to provide the data thereto. Indirect storage holds data associated with a second portion of the registers and cannot directly provide the data to the execution unit. Which architectural registers are in the first and second portions varies dynamically based upon the current processor mode. If a specified register is currently in the first portion, the microprocessor loads data from memory into the direct storage, whereas if in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage.

Abstract: Compute client processes are currently limited to a small percentage of the data I/O bandwidth available from a parallel file system's total aggregate I/O bandwidth. I/O bandwidth is limited by the pathways linking the parallel file system's data storage servers to the clients process's computer system and the number of stops the data makes in route before arriving in the client's memory space. Both of these limitations are overcome by hosting the entire set of file system storage servers or object storage servers within the same common global shared memory, parallel computer system, as the requesting client process. The data moves once, in parallel, from the storage devices, directly to the storage servers memory, which is the same memory address space as the compute client. This provides the compute client with low-latency access to the “Entire Aggregate I/O Bandwidth” provided by all of the File System Data Storage Servers.

Abstract: The invention relates to systems, methods and computer-readable media for controlling access to compute resources in a compute environment such as a cluster or a grid. The method of providing conditional access to a compute environment comprises associating a required service level threshold with a compute environment, associating a service level with a requestor, receiving a request for access to the compute environment from the requestor; and, if the service level of the requestor meets the specified service level threshold, then allowing access to the compute resources. The threshold-based access may be enforced by reservations, policies or some other method.

Abstract: In one embodiment, a processor includes plural processing cores, and plural instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having a plurality of group execution masks and a store execution matrix comprising a plurality of store execution masks. The processor further includes a core selection unit that, for each instruction within each instruction store, selects a store execution mask from the store execution matrix. The core selection unit for each instruction within each instruction store selects at least one group execution mask from the group execution matrix. The core selection unit performs logic operations to create a core request mask.

Abstract: Embodiments relate to address generation in an active memory device that includes memory and a processing element. An aspect includes a method for address generation in the active memory device. The method includes reading a base address value and an offset address value from a register file group of the processing element. The processing element determines a virtual address based on the base address value and the offset address value. The processing element translates the virtual address into a physical address and accesses a location in the memory based on the physical address.