Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract: A computer implemented method, data processing system, and computer usable code are provided for generating code to perform scalar computations on a Single-Instruction Multiple-Data (SIMD) Reduced Instruction Set Computer (RISC) architecture. The illustrative embodiments generate code directed at loading at least one scalar value and generate code using at least one vector operation to generate a scalar result, wherein all scalar computation for integer and floating point data is performed in a SIMD vector execution unit.

Abstract: System, device, method, and computer program and computer program products for providing communicating between devices having similar or dissimilar characteristics and facilitating seamless interoperability between them. Computer program software and methods of and systems and devices for sharing of content, applications, resources and control across similar and dissimilar permanently or intermittently connected electronic devices. Devices, systems, appliances, and the like communicating and/or interoperating within the framework provided. Interoperability device, such as a DartDevice, provides a highly interoperable device by virtue of its running a compliant player such as a DartPlayer containing an engine such as a DartEngine and at least one communications protocol for connecting to other devices.

Abstract: Methods, parallel computers, and computer program products are disclosed for low latency, high bandwidth data communications between compute nodes in a parallel computer.

Abstract: Standalone software performance optimizer systems for hybrid systems include a hybrid system having a plurality of processors, memory operably connected to the processors, an operating system including a dispatcher loaded into the memory, a multithreaded application read into the memory, and a static performance analysis program loaded into the memory; wherein the static performance analysis program instructs at least one processor to perform static performance analysis on each of the threads, the static performance analysis program instructs at least one processor to assign each thread to a CPU class based on the static performance analysis, and the static performance analysis program instructs at least one processor to store each thread's CPU class.

Abstract: Software rendering and fine grained parallelism are utilized to reduce/ovoid memory latency in a multi-processor (MP) system. According to one embodiment, the management of the transfer of data from one processor to another in the MP environment is moved into a low overhead hardware system. The low overhead hardware system may be a FIFO (“First In First Out”) hardware control. Each FIFO may be real or virtual.

Abstract: An asymmetric multiprocessor capable of increasing a degree of freedom of distributed processing, minimizing a processing load on each processor (CPU), and achieving a large reduction in power consumption by reducing an operating frequency or lowering the power supply voltage. An asymmetric multiprocessor includes a hardware resource mediator that mediates request signals requesting permission to use arbitrary hardware accelerators from CPU cores. A signal processing content selector selects signal processing content of a dynamically reconfigurable signal processor that is connected as a slave A clock skew mediator arbitrarily shifts a clock phase relationship among groups, while clock delay generators delay a clock signal based on a clock skew selection enable signal.

Abstract: Sharable extended cell information is used by multidimensional data models to enable cell annotations and line item details. Annotations are notes stored with a cell in a multidimensional dataset. Line item details permit levels of numeric detail below the lowest dimensional granularity. When receiving a multidimensional dataset in response to a query, a client application receives indicator information at the cell level, indicating to the client application that extended cell information is retrievable.

Abstract: Subject program code is translated to target code in basic block units at run-time in a process wherein translation of basic blocks is interleaved with execution of those translations. A shared code cache mechanism is added to persistently store subject code translations, such that a translator may reuse translations that were generated and/or optimized by earlier translator instances.

Abstract: A method according to one embodiment may include generating, by subsystem voltage regulator circuitry, a subsystem power supply for subsystem circuitry based on, at least in part, a main power supply; detecting, by subsystem power management circuitry, the activity of the subsystem circuitry, and turning off the subsystem power supply, by the subsystem power management circuitry, if the subsystem circuitry is inactive.

Abstract: A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.

Abstract: A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.

Abstract: A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated with the tasks among the processing elements, and a main controller including a scheduler, a resource allocation module, and a power management module. The scheduler assigns the tasks on the processing and non-processing elements with reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements with reference to task assignments determined by the scheduler. The power management module performs dynamic voltage management upon the processing and non-processing elements according to the scheduled tasks.

Abstract: Quantum information processing device includes resonator incorporating material containing physical systems, each of physical systems having at least four energy states, transition between two energy states of at least four energy states, and transition energy between at least two energy states of at least four energy states, at least four energy states being non-degenerate when magnetic field fails to be applied to physical systems, transition resonating in resonator mode that is in common between physical systems, each of at least four energy states representing a quantum bit, transition energy being shifted when magnetic field is applied to physical systems, and magnetic-field application unit configured to apply magnetic field having direction and intensity to material, to eliminate linear transition energy shift between two energy states included in physical systems, each of two energy states included in physical systems being with excluding two energy states resonating in resonator mode.

Abstract: The invention relates to computer architecture technology in the computer field. More specifically, the invention relates to a novel driving method for driving computer program/instruction execution, and a computer processor architecture and computer processor using the method. As one of the features of the invention, even on condition that no interrupt process is involved, the processor of this type can execute multiple programs in parallel on a single processor of this type exactly at the same time. Herein, the single processor relates to a single processor comprised of an instruction control section, an operation control section, a program memory section, a data memory section, and a communicating section. As another feature of the invention, a program execution driver (PED) is provided for each of the programs, and the multiple PED can manage and control the execution of multiple programs in parallel on the above single processor at the same time, independently or cooperatively with each other.

Abstract: A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.

Abstract: A processor arrangement having a plurality of processor units and a control computer. Each of the processor units is connected to at least one adjacent processor unit and has one control element and at least one communications interface for providing a data communications link with an adjacent processor unit. The control computer is connected to one of the processor units, and is configured for exchanging information with the processor unit and for assigning one control element of the plurality of control elements to a device that is electrically connected to the processor arrangement for the control of the device.

Abstract: An apparatus and method for implementing a hash algorithm word buffer. In one embodiment, a cryptographic unit may include hash logic configured to compute a hash value of a data block according to a hash algorithm, where the hash algorithm includes a plurality of iterations, and where the data block includes a plurality of data words. The cryptographic unit may further include a word buffer comprising a plurality of data word positions and configured to store the data block during computing by the hash logic, where subsequent to the hash logic computing one of the iterations of the hash algorithm, the word buffer is further configured to linearly shift the data block by one or more data word positions according to the hash algorithm. The hash algorithm may be dynamically selectable from a plurality of hash algorithms.

Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: A mobile communication terminal and method for providing an RFID technique is provided. The terminal includes an RFID reader unit for receiving identification information from an RFID tag and a controller for detecting a pre-set theme corresponding to the identification information and outputting a control signal based on the detected theme.

Abstract: A method includes causing a common-resonator mode resonating with a transition between |2>i and |3>i that are coupled to each other by a transition having a homogenous broadening ?Ehomo greater than an energy difference between |0>i and |1>i, an energy difference between |2>i and |3>i being greater than ?Ehomo, transferring states of m quantum bits represented by |0>k and |1>k to |4>k and |5>k, respectively, when a quantum-bit-gate operation using the common-resonator mode is executed between the quantum bits represented by m physical systems k, |E(|u>k)?E(|v>k)|>?Ehomo, u, v?{2, 3, 4, 5}, u?v, executing adiabatic passage between the physical systems k, using light that resonates with a transition between |3>k and |4>k and a transition between |3>k and |5>k, executing the quantum-bit-gate operation between the quantum bits, and transferring, to |0>k and |1>k, the states represented by |4>k and |5>k, respectively.

Abstract: A Wide Register Set (WRS) is used in a packet processor to increase performance for certain packet processing operations. The registers in the WRS have wider bit lengths than the main registers used for primary packet processing operations. A wide logic unit is configured to conduct logic operations on the wide register set and in one implementation includes hardware primitives specifically configured for packet scheduling operations. A special interlocking mechanism is additionally used to coordinate accesses among multiple processors or threads to the same wide register address locations. The WRS produces a scheduling engine that is much cheaper than previous hardware solutions with higher performance than previous software solutions. The WRS provides a small, compact, flexible, and scalable scheduling sub-system and can tolerate long memory latencies by using cheaper memory while sharing memory with other uses.

Abstract: A system, apparatus and method of enhancing priority boosting of scheduled threads are provided. If, while being executed by a second CPU, a second thread determines that it has to wait for a lock on a shared resource held by a first thread that is scheduled to be executed by a first CPU, the second thread may boost the priority of the first thread by passing its priority to the first thread if its priority is higher than the first thread's priority. Further, to enhance the priority boost of the first thread, the second thread may reschedule the first thread to be processed by the second CPU. By having been rescheduled on the second CPU, the second thread may be dispatched for execution right thereafter.

Abstract: A single-instruction multiple-data processor comprises at least two multiply-accumulator units and associated coefficient memories and data memories. Coefficient memory addresses are formed from a base address and data samples stored in the data memories.

Abstract: A scalable and fully configurable computing architecture for a mobile multimedia architecture used in a vehicle includes a head unit having a processor, a field programmable gate array and a memory. The processor and the memory are configured to communicate over a first bus that is a dedicated memory bus, and the processor and the field programmable gate array are configured to communicate over a separate second bus. The field programmable gate array is configured to be loaded from memory with part of a multimedia vehicle-related application-specific functionality that is executable by the field programmable gate array, and the processor is cooperatively operable with the field programmable gate array to execute another portion of the multimedia vehicle-related application-specific functionality. The multimedia vehicle-related application-specific functionality in the field programmable gate array may be changed with software and downloaded to the field programmable gate array in the field.

Abstract: Systems and methods to define and store performance baselines. A baseline may be defined as a pair of snapshots, each snapshot containing the same set of statistics and having a timestamp value associated therewith. The present invention allows for the designation, automatically or manually, of statistics collected over a certain period of time to be stored and used for comparison. Baselines may be used, for example, to manually or automatically compare with current system performance, compare difference-difference values and set thresholds to monitor current system performance.

Abstract: A computer implemented method, apparatus, and computer program product for managing symmetric multiprocessor interconnects. The process identifies functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections. The process maps every functional communication connection between any two processors in the plurality of processors, based on the identified functional communication connections, to form an interconnect matrix. The process creates a path map using the interconnect matrix. The path map comprises a sequence of communication connections between the plurality of processors. The process initializes the plurality of processors using the path map.

Abstract: In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.

Abstract: A database system is able to receive a query that specifies an inequality join involving at least a first relation and a second relation. A plurality of segments of the first relation are sorted in the cache. Each sorted segment of the first relation in the cache is compared with the second relation.

Abstract: A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The processor distributes data on-ramps and data off-ramps across the data lanes of a data trunk of the primary interconnect trunk to enable communication with compute elements and other structures both on-chip and off-chip.

Abstract: A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation.

Abstract: A parallelism policy object provides a control parallelism interface whose implementation evaluates parallelism conditions that are left unspecified in the interface. User-defined and other parallelism policy procedures can make recommendations to a worker program for transitioning between sequential program execution and parallel execution. Parallelizing assistance values obtained at runtime can be used in the parallelism conditions on which the recommendations are based. A consistent parallelization policy can be employed across a range of parallel constructs, and inside recursive procedures.

Abstract: A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

Abstract: A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory is configured to store a b?tree of search prefixes (and possibly span prefix masks) at multiple levels therein. The pipelined tree maintenance engine, which is embedded within the search engine device, includes a plurality of node maintenance sub-engines that are distributed with the multiple levels of the hierarchical memory. The search engine device may also include pipeline control and search logic that is distributed with the multiple levels of the hierarchical memory.

Abstract: A serial data processing circuit that realizes the same performance as that of the pipeline processing with low power consumption. First to fourth latch units receive, in parallel, data sets supplied to a logic circuit. These latch units sequentially latch the data sets sequentially supplied to the logic circuit and output N data sets in parallel. A Selector sequentially selects the data sets supplied from these latch units and supplies the selected data sets to the logical circuit. For example, when the first latch unit latches data (a), the selector selects the data (a) and supplies it to the logic circuit. When the second latch unit latches data (b), the selector selects the data (b) and supplies it to the logic circuit. The logic circuit processes N serial data sets during each cycle.

Abstract: The processing apparatus in the present invention is a processing apparatus which executes a program and performs processes of the program, and includes the following: an execution circuit having a plurality of operation modes, each of which has a different effect on the processing performance and the power consumption of the processing apparatus; a measurement unit operable to measure at least one of a process execution performance and an execution power consumption of the processor circuit; and a control unit operable to compare a target value and a measurement result from the measurement unit, and to switch the operation modes in accordance to a result of the comparison.

Abstract: A system for selectively enabling a microprocessor-based system is disclosed. State information that describes the operating conditions or circumstances under which a user intends to operate the system is obtained. In the preferred embodiment of the invention, a valid hash value is determined, preferably based on the state information and preferably by locating the valid hash value within a table of valid hash values indexed by the state information. Candidate authorization information is obtained from the user, and a candidate hash value is generated by applying a hashing algorithm to the candidate authorization information, the state information, or a combination of the candidate authorization information and state information. The candidate hash value and the valid hash value are then compared, and the microprocessor-based system is enabled if the candidate hash value matches the valid hash value.

Abstract: An antenna control interface is integrated with common integrated circuit components, such as radio transceiver or baseband modem signal processing control logic. The antenna control interface controls the operation of an adaptive antenna array used with wireless communication system devices.

Abstract: A pipelined processor including one or more units having storage locations not directly accessible by software instructions. The processor includes a load-store unit (LSU) in direct communication with the one or more units for accessing the storage locations in response to special instructions. The processor also includes a requesting unit for receiving a special instruction from a requestor and a mechanism for performing a method. The method includes broadcasting storage location information from the special instruction to one or more of the units to determine a corresponding unit having the storage location specified by the special instruction. Execution of the special instruction is initiated at the corresponding unit. If the unit executing the special instruction is not the LSU, the data is sent to the LSU. The data is received from the LSU as a result of the execution of the special instruction. The data is provided to the requester.

Abstract: Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times. Separate processor cores may be morphed to appear differently for different applications. For example, two processor cores each capable of executing N-wide issue groups of instructions may be morphed to appear as a single processor core capable of executing 2N-wide issue groups.

Abstract: A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-write operation, each byte of the data value is read from the corresponding memory block, and is provided to the corresponding ALU. Similarly, each byte of a modify data value is provided to a corresponding ALU on a memory data bus. Each ALU combines the read byte with the modify byte to create a write byte. Because the write bytes are all generated locally within the ALUs, long signal delay paths are avoided. Each ALU also generates two possible carry bits in parallel, and then uses the actual received carry bit to select from the two possible carry bits.

Abstract: A deterministic microprocessor is disclosed in which a plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided.

Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency.

Abstract: Sub-socket partitioning is enabled using embodiments of the present invention. In one aspect, the memory mapping is performed to isolate memory access for each of the partitions by assigning a partition address and a generated physical address.

Abstract: Embodiments enable sub-socket partitioning that facilitates access among a plurality of partitions to a shared resource. A round robin arbitration policy is to allow each partition, within a socket, that may utilize a different operating system, access to the shared resource based at least in part on whether an assigned bandwidth parameter for each partition is consumed. Embodiments may further include support for virtual channels.

Abstract: Provided are a method, system, and program implemented by a device driver executing in a computer for handling interrupts from an associated device, wherein the device driver is capable of interfacing with the associated device. The device driver periodically monitors usage of the processors in the system and pins a processor to execute the interrupt handler of the device driver based upon the monitored usage. If the usage of the pinned processor exceeds that of one or more of the other processors, the device driver may pin the interrupt handlers to a different, lower utilized processor.

Abstract: In one embodiment, a computer system comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, at least one programmable trusted platform management device coupled to the processor via a hardware path which goes through at least one trusted platform management device controller which manages operations of the at least one programmable trusted platform device, and a routing device to couple the first and second computing cells.

Abstract: A processing unit includes a processing core and a wireless module directly connected to the processing core, wherein the wireless module is for providing wireless communications to the processing core. A multi-processor system includes a first processing unit having a first processing core and a first wireless module directly connected to the first processing core, the first wireless module for providing wireless communications to the first processing core; a second processing unit having a second processing core and a second wireless module directly connected to the second processing core, the second wireless module for providing wireless communications to the second processing core; and a wireless link between the first and second wireless modules; wherein the first processing unit is for communicating with the second processing unit via the wireless link.

Abstract: A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a processor integrated circuit including multiple processors with respective processor cache memories. The design structure may specify enhanced cache coherency protocols to achieve cache memory integrity in a multi-processor environment. The design structure may describe a processor bus controller manages cache coherency bus interfaces to master devices and slave devices. The design structure may also describe a master I/O device controller and a slave I/O device controller that couple directly to the processor bus controller while system memory couples to the processor bus controller via a memory controller.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.