Abstract: A method, system, and computer program product to test a semiconductor device are described. The system includes an input interface to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns. The system also includes a processor to process the subset of the set of test patterns to output test data to the semiconductor device.

Abstract: A method, system, and computer program product to test a semiconductor device are described. The method includes receiving a set of test patterns for testing the semiconductor device and a user selecting a subset of the set of test patterns. The method also includes cataloging a content of pattern files associated with the subset of the set of test patterns to generate a catalog, and processing the catalog to output test data to the semiconductor device.

Abstract: A method, apparatus and product for completion of partial coverage tasks. The method comprising obtaining a partial coverage task defining a test with respect to a functional coverage model of a System Under Test (SUT), wherein the functional coverage model defining functional attributes and respective domains thereof, wherein the functional coverage model further defining one or more restrictions on value combinations of the functional attributes; and enhancing the partial coverage task to include an assignment of a value to a functional attribute, wherein the functional attribute is unassigned in the partial coverage task, wherein the value is an only valid assignment to the functional attribute in view of assignments of other functional attributes and in view of the restrictions.

Abstract: Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract: Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, and the solid operating timing window used to determine a key timing index. A method for determining the solid operating timing window is disclosed. A plurality of sets of operating parameters is generated. For each of the plurality of sets of operating parameters, the respective set of operating parameters is applied to a test environment. The integrated circuit is then operated under the applied respective set of operating parameters. A determining a data valid window is determined for the integrated circuit. The solid operating timing window for the integrated circuit is then determined using the data valid windows for the plurality of sets of operating parameters, where the solid operating timing window is defined as the logical intersection of the determined data valid windows such that the integrated circuit will return valid sample.

Abstract: Provided are a digital broadcast transmitter, a digital broadcast receiver, a stream-processing method for the digital broadcasting transmitter, and a stream-processing method for the digital broadcast receiver. The stream-processing method for the digital broadcasting transmitter includes: configuring a stream in which slots including a plurality of blocks are continuously disposed; and encoding and interleaving the stream to be output as a transport stream, wherein the configuring the stream includes, if slots of a block extension mode 00 are continuously placed, connecting known data placed in predetermined locations of adjacent slots to each other in order to generate a long training sequence.

Abstract: A system for designing a circuit, which includes a module, uses a computer. A user may program or adapt the computer to perform computer-aided design functions. The computer obtains a description of the module from the user. The computer parses the description of the module to identify a port of the module, and to obtain information about the port. The computer presents to the user the information that it has obtained about the port.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: A data receiver device includes a logic unit configured to generate a test pattern signal, receive a test result signal in the test mode, and compare the test pattern signal with the test result signal to perform a test in the test mode. The data receiver further includes a system frequency control circuit configured to multiply a reference clock signal by a multiplication factor received from the logic unit and to output a test clock signal, an output terminal configured to serialize the test pattern signal based on the test clock signal and to output an output signal, and an input terminal configured to recover a data signal and a data clock signal from an input signal based on the output signal, to deserialize the data signal based on the data clock signal, and to output the test result signal to the logic unit.

Abstract: A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit is coupled to a logic block to be scan tested. The output from the logic block is coupled to a serial output pin on the integrated circuit during scan test mode. High performance integrated circuits can use SerDes pins in a scan test mode to be scan tested without impacting mission critical signals.

Abstract: Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a layout-aware diagnosis method. Based on the suspect information, potential root causes for the plurality of failing dies, and suspect feature weights and total feature weights for each of the potential root causes may then be determined. Next, the probability information of observing a particular suspect that is related to a particular root cause may be extracted. Finally, an expectation-maximization analysis may be conducted for generating the root cause distribution information based on the probability information and the suspect information. Heuristic information may be used to prevent the analysis from over-fitting.

Abstract: According to exemplary embodiments, a computer implemented method for functional testing of a processor design includes accessing a test template from a library of test templates, wherein the test template is configured to test a first selected function of the processor and inputting the test template to an automated test generation tool executed by a computer. The method further includes generating an instruction sequence based on the test template by the automated test generation tool and injecting an event instruction to the instruction sequence during the generating of the instruction sequence by the automated test generation tool, the injecting of the event instruction preserving testing of the first selected function of the processor and the event instruction being configured to test a second selected function of the processor. The method includes verifying a function of the processor by analyzing responses of the processor to the instruction sequence.

Abstract: A method of sensitizing a sequential circuit is described. This sensitizing generates stimuli to drive any circuit output to a predetermined value or transition. The method includes creating a directed graph of the sequential circuit. Nodes of the graphs can be topologically sorted. In one embodiment, feedback loops in the directed graph can be removed before topologically sorting the nodes. Final vectors for the sequential circuit can be generated based on the sorted nodes. Notably, the final vectors are expressed only by primary inputs to the sequential circuit. Using only primary inputs in the final vectors accurately replicates the sequential circuit under test, thereby ensuring accurate timing, power, and noise arcs are measured.

Abstract: Provided is a test apparatus that tests a device under test having a plurality of output terminals. The test apparatus comprises an executing section that executes a test command sequence for testing the device under test; a storage section that stores a plurality of pieces of setting data designating one or more output terminals among the plurality of output terminals; a detecting section that detects whether a value of an output signal from an output terminal designated by one of the pieces of setting data matches an expected value; and a selecting section that selects different pieces of setting data in the storage section when at least two detection commands, which change execution sequencing of the test command sequence according to the detection results of the detecting section, are executed, and supplies the selected pieces of setting data to the detecting section.

Abstract: Disclosed is a system and method for verifying a chip having a memory. Remanufacturers of imaging devices, such as inkjet printers or electrostatic printers, often have to use a replacement chip in order to reuse an imaging cartridge. It is desirable to have a system and method for determining if the replacement chip is suitable for use with a specific imaging cartridge. Also, it may be desirable to confirm that the chip was manufactured by a specific manufacturer. The disclosed system and method allow the remanufacturer a reliable and efficient way to verify chips.

Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Abstract: In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.

Abstract: A method for reordering a test pattern set for testing an integrated circuit is disclosed. A productivity index is computed for each test pattern in a test pattern set. The productivity index of a first test pattern and the productivity index of a second test pattern are compared. If the productivity index of the second test pattern is larger than the productivity index of the first test pattern, the location of the first test pattern and the second test pattern are swapped.

Abstract: An apparatus including a protocol engine and a built-in self test (BIST) engine. The built-in self test (BIST) engine is coupled to the protocol engine. The built-in self test (BIST) engine may be configured to directly control when to open and close rows of a synchronous dynamic random access memory (SDRAM) during double data rate (DDR) operations.

Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract: Exemplary method, system, and computer program product embodiments for an incremental modification of an error detection code operation are provided. In one embodiment, by way of example only, for a data block requiring a first error detection code (EDC) value to be calculated and verified and is undergoing modification for at least one randomly positioned sub-blocks that becomes available and modified in independent time intervals, a second EDC value is calculated for each of the randomly positioned sub-blocks. An incremental effect of the second EDC value is applied for calculating the first EDC value and for recalculating the first EDC value upon replacing at least one of the randomly positioned sub-blocks. The resource consumption is proportional to the size of at least one of the randomly positioned sub-blocks that are added and modified. Additional system and computer program product embodiments are disclosed and provide related advantages.

Abstract: A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: Provided is an information processing system that reflects a processing load of the virtual machine actually running in one server, and reproduces the processing load generated in the case where this virtual machine is run in the other server. An information processing system (1000) includes a server A(100) and a server B(200) that can communicate with each other through a network (500). The server A(100) runs a virtual machine (123), and transmits, to the server B(200), load information indicative of a processing load generated in the server A(100) as a result of running the virtual machine (123) when the virtual machine (123) is run. The server B(200) generates the processing load on the basis of the load information received from the server A(100).

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract: The disclosed device performs a control of generating a test pattern for the delay test of LSI. The input pattern control circuit counts a cycle number of an input pattern supplied to a test object circuit, and stops supply of the input pattern to the test object circuit when the cycle number of the input pattern coincides with a certain count number. The scan control circuit receives a control signal from the input pattern control circuit, and supplies a scan shift signal to the test object circuit to shift a scan chain in the test object circuit.

Abstract: A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.

Abstract: A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: Provided is a test apparatus comprising a plurality of pattern output sections. In a high-speed mode, each pattern output section outputs, as pattern data corresponding to at least one of a plurality of partial periods, the pattern data corresponding to an input pattern input to the pattern output section and the pattern data corresponding to input patterns input to other pattern output sections.

Abstract: Methods and systems for estimating cost for device testing are disclosed. In one embodiment, the method comprises reading a test file having a plurality of test vectors, determining a required memory needed to execute the plurality of test vectors, and using the required memory to estimate a cost to execute the test vectors.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: Systems, methods, and other embodiments associated with at-speed testing of static random access memory (SRAM) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (SRAM). The SRAM is tested by generating a test input that is based, at least in part, on the control pattern from the multi-stage pipeline of flip-flops. The test input is provided to the SRAM over a series of clock cycles that are at a core clock speed of the SRAM.

Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.

Abstract: A method for producing a LDPC encoded test pattern for media in a LDPC based drive system includes adding error detection code data to a predominantly zero bit test pattern and adding additional zero bits to produce a test pattern of a desirable length. The test pattern may then be scrambled to produce a desirable flaw detection test pattern. The flaw detection test pattern may then be encoding with an LDPC code, or other error correction code with minimal disturbance to the run length constraints of the data pattern, and written to a storage medium.

Abstract: A method of testing an interconnect between an electronic component and an external memory comprises receiving a data word having data bits and translating the data word into multiple cycles. The multiple cycles are transmitted through the interconnect to the external memory one after another such that a value of the data bit being transmitted is switched for each cycle. In another embodiment, an electronic component comprises an interface, a translation unit, and a test module. The translation module is configured to receive a burst from the external memory through the interface and is configured to translate the burst into a data word. The test module is configured to receive the data word from the translation module and is configured to compare the data word to a test pattern to detect an interconnect defect.

Abstract: A method of producing a mainly carbonate bonded article includes a step of providing an alkaline granular material having one or more alkaline earth metal silicate phases. The method includes a step of compacting the granular material to obtain a compact of the granular material. The porosity of the compact is smaller than or equal to 37% by volume. The intrinsic permeability of the compact is at least 1·10?12 cm2. The method also includes a reacting step arranged to form at least 5% by weight of carbonates (CO32?), by reacting the granular material with carbon dioxide in the presence of water, thus transforming the compact into the article. In the reacting step, the compact, being unsaturated with moisture at the beginning of the reacting step, is brought in an atmosphere having carbon dioxide. The atmosphere is at a temperature of at least 70° C. and at a pressure of at least 0.5 MPa. The pressure is also higher than the saturated vapor pressure of water at the temperature.

Abstract: Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.

Abstract: A system for testing electronic circuits is configured to receive a test signal and an ideal response signal and output a test result signal. The system for testing electronic circuits includes a circuit portion to be tested, a comparator and a comparison result recorder. The circuit portion to be tested receives a test signal from a test instrument, and outputs a system response signal. The comparator receives the system response signal from the circuit portion to be tested and receives an ideal response signal from the test instrument. Then, the comparator outputs a comparison result according to the system response signal and the ideal response signal. The comparison result recorder receives and records the comparison result. The comparison result recorder may record comparison results within a period of test time. The test instrument can obtain a record of the comparison results from the comparison result recorder.

Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.

Abstract: A semiconductor device comprises processing logic arranged to execute program instructions. The semiconductor device further comprises signature generation logic arranged to receive at least one value from at least one internal location of the semiconductor device, and to generate a current signature value, based on the at least one received value. Validation logic is arranged to validate the current signature value generated by the signature generation logic. The processing logic is further arranged, upon execution of a signature validation instruction, to enable the validation of the current signature value provided by the validation logic.

Abstract: The various embodiments of the present invention provide a method for automatically generating a unique set of test vectors for verifying design intent of integrated circuit chips. The method includes obtaining configuration parameters associated with a plurality of integrated circuit chips, generating an Executable Verification Plan pertaining to the configuration parameters of a plurality of integrated circuit chips in one or more execution PCs (EPs), creating a plurality of data structures corresponding to the configuration parameters, communicating the data structures created to a DCMS server, mapping the data structures of the Execution PCs with one or more data structures present in a database of the DCMS server, customizing the executable verification plan based on changes in the configurations of the integrated circuit chips, generating a unique set of test vectors based on mapping of the data structures and performing automatic design verification of the plurality of integrated circuit chips.

Abstract: A system and method for the execution of a program comprises a user-defined sequence of standard hardware and analysis module commands of an instrument, in the context of a tester comprising a plurality of VSAs and VSGs, or other hardware measurement modules types, where the coordination of command execution and resource availability is built into the system as an inherent part of its overall architecture. As such, the commands are the same as those ordinarily executed in piecemeal fashion, but are now automatically and sequentially executed in an atomic and deterministic manner through the coordinated interaction of embodiments of the invention.

Abstract: Signature circuits are used during testing of an integrated circuit. Test vectors are applied as inputs to a circuit under test. A signature circuit stores a “signature” for the circuit under test based on a combination of signals from the circuit under test in response to test vectors and a previous stored state of the signature register. The value contained in the signature register at the end of the test is the signature. A fault-free circuit generates a particular signature for the applied test vectors. Faults can be determined by detecting variances from the expected signature. In one embodiment, the signature circuit uses a combination of two error detection codes.