Abstract: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.

Abstract: A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in the shape of the pattern data for the modification target point caused by the modification based on the modification guides or a change in electric characteristics of a pattern formed in accordance with the pattern data, selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides, and modifying the modification target point in accordance with the selected modification guide.

Abstract: An automatic system for providing printed circuit board (PCB) layout of a PCB includes an input device, a data processing device, and a storage device. The data processing device includes an invoking module, a calculating module, and a determining module. The invoking module is to read a name and a thickness of each layer of the PCB from the storage device. The calculating module is to calculate an actual length of a via stub of each layer according to the name and thickness of each layer, and calculate an ideal length of the via stub of the PCB according to input information from the input device, and a preset formula. The determining module is to compare the ideal length and the actual length of the via stub of each layer to determine whether the layer can be used as a high-speed signal layout layer or not.

Abstract: A design tool for automatically identifying minimum timing violation corrections in an integrated circuit (IC) design includes program instructions executable by a processor to identify locations to add a delay along each circuit path having a minimum timing violation. The tool may also sequentially try each of a plurality of circuit changes that add the delay and to evaluate a result of each circuit change until an acceptable percentage of the minimum timing violation has been corrected. In response to each circuit change, the design tool may update an internal node report, which includes a listing of circuit nodes and a maximum timing slack available at each node, by reducing a maximum slack value of each affected node by an amount of the added delay. The design tool may generate an output report that includes a listing of the circuit changes which correct the minimum timing violations.

Abstract: A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.

Abstract: Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected, and a merged model is built that eliminates the candidate redundant gate. If the candidate redundant gate is within the merged constraint cone the pre-merge model is used to validate redundancy of the candidate redundant gate. However, if the candidate redundant gate is not within the merged constraint cone the merged model is instead used to validate redundancy of the candidate redundant gate.

Abstract: An apparatus for analyzing circuit specification description design has a circuit specification description inputting section that analyzes and obtains information of a related signal, information of the maximum number of cycles in the related signal, and a definite value in a site defined in the circuit specification description for the related signal contained in a circuit specification description, a data base generating section that generates signal variation data indicating time-series signal variation, wherein a definitive value is set in the site defined in the circuit specification description and a predetermined flag is set in a site where the value is not defined in the signal variation data, and a waveform diagram data outputting section that outputs waveform diagram data for displaying the time-series signal variation in a form of a waveform diagram on the basis of the definite value and the predetermined flag set in the data.

Abstract: According to the present invention, there is provided an apparatus for executing logic synthesis for a module having a plurality of clock domains, having: an input unit which inputs circuit description data about a circuit function and a constraint in logic synthesis; a path selection unit which selects a path included in the module using a result obtained by analyzing the circuit description data; a recognition unit which recognizes a start point and an end point of the selected path and recognizes clock domains to which the start point and the end point belong; and a technology library setting unit which sets a technology library for the selected path in accordance with the clock domains to which the start point and the end point belong.

Abstract: A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method.

Abstract: A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

Abstract: A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured.

Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.

Abstract: Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages.

Abstract: A design information generating equipment is provided. A control component of the design information generating equipment, when a basic function of the plurality of functions constitutes a requested function, and design information that corresponds to the basic function is stored in a second memory area, uses the stored design information, and, when the design information that corresponds to the basic function of the plurality of functions is not stored in the second memory area, uses a source program corresponding to the basic function of the plurality of functions stored in a first memory area, and performs control so as to generate design information corresponding to the basic function of the plurality of functions and stores the generated design information in the second memory area, and, using the generated design information, reconfigures a design configured to execute the requested function, and executes the requested function with the reconfigurable design information.

Abstract: The present invention relates to a monitor cell (200) for monitoring local variations in a process parameter of an integrated circuit. The monitor cell (200) comprises a first delay path (220) located in a first area (100, 110, 120) of the integrated circuit and a second delay path (230) located in a second area (100, 110, 120) of the integrated circuit. The first delay path (220) is faster than the second delay path (230) when the difference in the respective process parameter values of the first area and the second area is smaller than a predefined threshold. In contrast, the second delay path (230) is faster than the first delay path (220) when said difference is larger than the predefined threshold. The monitor cell further comprises an input (210) arranged to provide the first delay path (220) and the second delay path (230) with a test signal (260) and a signal detector (240) for detecting the order in which the delay paths (210; 220) output the test signal (260).