Abstract: Computer-implemented techniques are disclosed for defining an environment for formal verification of a design-under-test. Initially there is extraction of design inputs by a design analysis module, and presentation of the inputs on a graphical user interface. Behavior options for the design inputs are offered on the graphical user interface for selection by an operator. Environment code that is descriptive of the design inputs and selected behavior options is emitted, typically in a hardware description language, for submission to a formal verification tool. A meta-code file containing the assigned behavior options is generated to aid subsequent sessions.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: To provide a checking method that utilizes a test bench for a circuit model, which will serve as a fundamental for equivalence checking of a circuit to be newly developed for the fundamental circuit model. In order to check the equivalence of a model to be verified using a sample model a circuit of which has been described in a predetermined language and a test vector generation model for the sample model, a process for writing an output from the sample model test vector generation model into an input FIFO group for each signal of the sample model with the same timing as that of the sample model while the sample model is inputting/outputting a signal from/to the sample model test vector generation model with cycle accuracy and a process for reading data from the input FIFO group with the same operation timing as that of the model to be verified and outputting the data to the model to be verified are carried out.

Abstract: A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein.

Abstract: Local searches are provided for improving technology mapping for programmable logic integrated circuits. A local search algorithm is applied to a solution for mapping logic gates in a netlist to lookup tables (LUTs) on a programmable logic IC. The local search algorithm applies a series of local moves to the solution. At each move, a small change to the LUT mapping is proposed, and the change in cost for that LUT mapping change is computed. If the cost is improved, the change is accepted and the LUT mapping is replaced by the changed LUT mapping. Otherwise, the change in solution is either rejected, or accepted with a probability that depends on the cost change. The cost function can be chosen to represent one or more features of the LUT mapping, such as area, speed, power consumption, or a combination thereof.

Abstract: CMOS pixel sensor cells with spacer transfer gates and methods of manufacture are provided herein. The method includes forming a middle gate structure on a gate dielectric. The method further includes forming insulation sidewalls on the middle gate structure. The method further includes forming spacer transfer gates on the gate dielectric on opposing sides of the middle gate, adjacent to the insulation sidewalls which isolate the middle gate structure from the spacer transfer gates. The method further includes forming a photo-diode region in electrical contact with one of the spacer transfer gates and a floating diffusion in electrical contact with another of the spacer transfer gates.

Abstract: A behavioral synthesis unit generates an intermediate level description that describes a plurality of processes indicated by a behavioral level description and data passed over during the plurality of processes based oil a behavioral level description describing the behavior of an electronic circuit and synthesis constraint information constituting constraints to be satisfied while generating a register transfer level description based on the behavioral level description and the number and type of circuit configuration elements that can be described in the register transfer level description. The data flow path information analyzing unit acquires path information indicating a data path and at least one process executed on the path based on the intermediate level description. A synthesis constraint generating unit then generates new synthesis constraint information that improves prescribed circuit performance of the electronic circuit based on library information and path information.

Abstract: A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.

Abstract: A serialization construct is implemented within an environment of a number of parallel data flow graphs. A quiesce node is appended to every active data flow graph. The quiesce node prevents a token from passing to a next data flow graph within a chain before an execution of the active data flow graph has been finished. A serial data flow graph is implemented to provided for a serial execution while no other data flow graph is active. A serialize node is appended to a starting point of a serial data flow graph. A serialize end node is appended to an endpoint of the serial data flow graph. The serialize node is activated to start a serial operation. The serialize end node is activated after the serial operation has been terminated.

Abstract: A computer-implemented method of performing an equivalence check on a mixed-signal circuit is performed on a server system, and includes responding to a verification request. In the method, the following operations are performed. A static analysis is performed on a first netlist, and a synthesizable section and non-synthesizable section of the first netlist are identified. A functional equivalence is determined between the non-synthesizable section of the first netlist and a corresponding non-synthesizable section of a second netlist, and a logical equivalence is determined between the synthesizable section of the first netlist and a corresponding synthesizable section of a second netlist. An equivalence result is provided based on the determined functional equivalence and the determined logical equivalence.

Abstract: A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.

Abstract: Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints.

Abstract: A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical layout features of a proposed memory array in an integrated circuit. A first model of a memory instance derived from the first set of memory structural primitives supplied by the designer is compared to a second model of a memory instance derived from a memory layout file from a memory compiler under-test. The first model is verified against the second model to verify to an integrity of the first set of memory structural primitives supplied by the designer compared to the memory layout file derived from a second set of memory structural primitives configuring that memory instance from the memory compiler.

Abstract: A receiving unit receiving a description expressing a finite state machine comprising states 0, 1, 2, . . . , N?1; a dividing unit dividing the states 0, 1, 2, . . . , N?1 into groups 0, 1, 2, . . . , M?1, wherein the dividing unit allocates the states 0, 1, . . . , L[0]?1 to the group 0, allocates the states L[0], L[0]+1, . . . , L[1]?1 to the group 1, allocates the states L[1], L[1]+1, . . . , L[2]?1 to the group 2, . . . , and allocates the states L[M?2], L[M?2]+1, . . . , L[M?1]?1=N?1 to the group M?1; and a generating unit generating a register transfer level description so that decoders which acquire the current state are generated for each group are provided.

Abstract: Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.

Abstract: Methods are described for forming an integrated circuit having multiple devices, such as transistors, with respective element lengths. The methods include a new CAD flow for producing masks used for exposing sidewall spacers which are to be etched to a smaller base width than other sidewall spacers and which in turn are used as an etch mask to form gate structures with smaller element lengths than those formed from the other sidewall spacers.

Abstract: In an example embodiment, an EDA program receives input which includes a selection as to an FPGA die and its device package and a selection as to a structured ASIC die and its device package. If the I/O pins on the device package for the FPGA differ from the I/O pins on the device package for the structured ASIC, the EDA program determines a correspondence between the I/O pins on the two device packages (e.g., by identifying the location of the pads for I/O pins on the structured ASIC die and/or creating a virtual structured ASIC device package whose I/O pins are a superset of the I/O pins on the selected structured ASIC device package), which determination includes checking rules for resource assignments. The EDA program then stores the determined correspondence in a device database where the determined correspondence can be accessed by CAD algorithms.

Abstract: Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform in parallel and sends the task to be performed in parallel; and receives execution results or processing results from some of the plurality of slaves and updates one or more databases to incorporate the execution or processing results. In some embodiments, the method allows speeding up the applications without major rewrite without a need for design partition, and without memory penalty.

Abstract: A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.

Abstract: A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e.g., duplex multipliers with N values of 16 or more) are used.

Abstract: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.

Abstract: A minimal leakage power Standard Cell Library is provided. The minimal leakage power Standard Cell Library provides minimal leakage power cells with improved speed characteristics. The minimal leakage power Standard Cell Library includes cells from an existing Standard Cell Library and a set of minimal leakage power cells for a selected set of logic functions. The minimal leakage power Standard Cell Library is formed by identifying a set of logic functions. For each logic function in the identified set, a base case for an unfolded implementation of the logic function is determined. Widths for transistors in a transistor topology used in the unfolded implementation of the logic function are determined based on the non-linear leakage power characteristics for the transistor topology to achieve minimal leakage power. The determined widths are then assigned to the transistors and the minimal leakage cell is added to the library.

Abstract: Methods are provided for utilizing a process-independent schema library that contains all the devices and all the device parameters in each of various process-specific schema libraries that a user or a group of users is working with. A process-specific schematic based on a first process technology can be converted to a process-specific schematic based on a second process technology by being first converted to a process-independent schematic that is based on the process-independent schema library, which is then converted to the process-specific schematic based on the second process technology. Circuits can be also be stored as a process-independent schematic that is based on the process-independent schema library but designed using a user interface that displays process-specific devices and device parameters.

Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

Abstract: A design structure embodied in a non-transitory machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register.

Abstract: A system and method of managing interrupt requests from IP cores within an integrated circuit design can include capturing environmental constraints within constraint files for the integrated circuit design (where the constraints can include information regarding a board upon which an integrated circuit device is mounted, pin locations for interrupt signals, and the sensitivity of the interrupt signals), generating connections among interrupt sources, interrupt controllers, and interrupt request ports on microprocessor cores within a device environment, and automatically instantiating controller logic when interrupt controllers are lacking during compilation of the device design. The method and system can also identify within the design, processor and bus interconnections as well as each interrupt port on the IP cores and the sensitivity requirements for each port which can be stored within description files for a corresponding IP core instead of an HDL specification.

Abstract: Electronic design automation (EDA) libraries are delivered using a geographically distributed private cloud including EDA design centers and EDA library stores. EDA projects associated with an EDA library are determined by matching information describing the EDA library with information describing the projects. A set of design centers hosting the projects is determined. A data delivery model is determined for transmitting the EDA library to the design centers. The EDA library is scheduled for delivery to the design centers based on a deadline associated with a project stage that requires the EDA library. Network links with specialized hardware for transmitting data are determined in the private cloud by measuring their deterioration in performance on increase of data transmission load. These links are used for delivering EDA libraries expected to be used urgently for a stage of an EDA project.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: An enhanced turn-on time SCR based electrostatic discharge (ESD) protection circuit includes an integrated JFET, method of use and design structure. The enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit includes an integrated JFET in series with an NPN base.

Abstract: An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures.

Abstract: A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design.

Abstract: A plurality of third fixed potential lines are wired in parallel. A group of high-potential-side fixed potential lines containing a first fixed potential line and a second fixed potential line are wired in a plurality at predetermined intervals in a direction perpendicular to the third fixed potential line. In a layout region, surrounded by a pair of adjacent third fixed potential lines and a pair of groups of adjacent high-potential-side fixed potential lines, where a first element or a second element is arranged, either one of the first fixed potential line and the second fixed potential line is wired between the pair of third fixed potential lines. In a layout region used for second elements, a second fixed potential line connecting a pair of second fixed potential lines contained respectively in a pair of groups of high-potential-side fixed potential lines that form the layout region is wired between a pair of third fixed potential lines that form the layout region.

Abstract: A method is provided to use a Smith Chart technique to obtain frequency domain network performance information corresponding to a passive network including one or more passive devices comprising: receiving first data representing a first Smith Chart plot of coefficients representing measured mismatch between a source impedance of a network and a load impedance of the network for higher frequency components; and extrapolating a predicted substantially spiral shaped second Smith Chart plot of coefficients based upon the first data, which includes a coefficient representing predicted mismatch between the source impedance of the network and the load impedance of the network for lower frequency components.

Abstract: In a circuit simulation system, a storage section is configured to store a circuit data, an analysis condition data and an output data. An initial data setting section reads out the circuit data and the analysis condition data from the storage section and sets an initial data and a convergence condition for a solution calculating process based on the circuit data and the analysis condition data. A processing section generates a circuit equation to each of a voltage variable and a current variable based on the circuit data, and executes the solution calculating process based on the initial data to calculate a solution. A convergence determining section executes a convergence determining process of whether or not the solution meets the convergence condition, on the voltage variable. An output section stores the solution into the output data when it is determined to meet the convergence condition.

Abstract: A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions in which an ordering of dimensions for routing data is configurable.

Abstract: A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the interconnection network to input/output ports of one or more peripheral devices, each input/output port of the interconnection network being associated with one of the processor tiles such that each input/output port of the interconnection network sends input data to the corresponding processor tile and receives output data from the corresponding processor tile. The extension network is configurable such that a mapping between input/output ports of the interconnection network and input/output ports of the one or more peripheral devices is configurable.

Abstract: Systems and methods to enable a user to edit subMaster content of selected instances of an electronic layout design, including editing the contents of selected instances of an existing subMaster of an EDA design, generating a new subMaster to incorporate the modified contents of the selected instances, and binding the new subMaster to the selected instances without losing the design hierarchy of the layout design.

Abstract: Embodiments of the present invention provide for sorted data signature analysis for identifying outliers in datasets. Some embodiments disclose a nearest pattern smallest delta procedure to identify outliers in a dataset of vector patterns. Other embodiments disclose a nearest neighbor smallest delta procedure to identify outliers among values from dies in a wafer. Still other embodiments may be disclosed and claimed.

Abstract: A method of determining a factorization permutation for a natural number can include storing a canonical prime factor vector within memory of a system and storing a first basis vector within the memory. The method can include deriving a first count sequence, including a plurality of counts, from the first basis vector, wherein each count of the first count sequence is a child of the first basis vector. For each count of the first count sequence, a second basis vector can be output that is a child of the count, wherein each count of the first count sequence and child second basis vector specifies a factorization permutation of the natural number.

Abstract: The invention relates to multi-planar memory components in a three-dimensional integrated circuit system configuration. A multi-planar memory system consisting of a plurality of memory circuit planes in a three-dimensional system on a chip (3D SoC) comprised of a plurality of memory layers, at least one logic circuit layer and an interface configured to provide access to memory and logic circuit layers.

Abstract: A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.

Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Abstract: Embodiments of the present invention provide methods and apparatuses for verifying the functionality of a circuit. The system can determine a lower-bound-distance (LBD) value, such that the LBD value is associated with an LBD abstract model of the CUV which does not satisfy a property. The system can use an abstraction-refinement technique to determine whether the CUV satisfies the property. The system can determine an upper-bound-distance value for an abstract model which is being used in the abstraction-refinement technique, and can determine whether the LBD value is greater than or equal to the upper-bound-distance value. If so, the system can conclude that the abstract model does not satisfy the property, and hence, the system can decide not to perform reachability analysis on the abstract model that is currently being used in the abstraction-refinement technique.

Abstract: A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip.

Abstract: A system and method is disclosed for breaking a feedback loop by replacing at least one component in the feedback loop with a model containing two physically disconnected subnetworks that have terminals that are connected to ground with voltage controlled, voltage sources (VCVSs). Dependent source parameters of the VCVSs control lateral signal transfer though the model allowing the feedback loop to be opened or closed. The model maybe used in a software simulation in which a replicate circuit is used to set and maintain a closed-loop bias on the open-loop circuit. Small-signal analysis of the equivalent open-loop circuit allows extraction of transfer functions that yield a return ratio RR(s) corresponding to the modeled component.

Abstract: The present invention relates to an automata unit, a tool for designing circuitry and/or checker circuitry, and a method for manufacturing hardware circuitry. The automata unit includes an input unit for receiving assertions using Boolean expressions, an automata generator for translating the assertions into automata, and an automata adaptor. The automata generator uses a dual layer symbolic alphabet for representing the assertions, and the automata adaptor adapts automata algorithms so as to support the symbolic alphabet in the generated automata. The tools for designing circuitry and checker circuitry rely on the automata unit, and further include an assertion unit and either a circuit generator or a checker generator.

Abstract: A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. A signal-handling apparatus may include an isolating circuit coupled to a first conductor, a second conductor to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. A signal-handling circuit can perform a signal-handling function in response to the output of the isolating circuit. The signal-handling circuit and the first circuit may be isolated from the second conductor and the signal-handling circuit such that a communication signal may be conducted with less capacitance and be subject to less return loss.

Abstract: A Hardware Description Language (HDL) processing method is implemented in a computer and processes a HDL file which is written in HDL having a hierarchical structure including three or more hierarchical levels in a Computer-Aided Design (CAD) which supports hardware design. The HDL processing method analyzes the hierarchical structure of the HDL and obtaining an analysis result, and processes the HDL one at a time for each hierarchical level based on the analysis result or, process the HDL one at a time by a parallel distributed processing for each hierarchical level based on the analysis result.

Abstract: A minimal leakage power Standard Cell Library is provided. The minimal leakage power Standard Cell Library provides minimal leakage power cells with improved speed characteristics. The minimal leakage power Standard Cell Library includes cells from an existing Standard Cell Library and a set of minimal leakage power cells for a selected set of logic functions. The minimal leakage power Standard Cell Library is formed by identifying a set of logic functions. For each logic function in the identified set, a base case for an unfolded implementation of the logic function is determined. Widths for transistors in a transistor topology used in the unfolded implementation of the logic function are determined based on the non-linear leakage power characteristics for the transistor topology to achieve minimal leakage power. The determined widths are then assigned to the transistors and the minimal leakage cell is added to the library.

Abstract: Operating splitting methods for splitting a circuit into two sub circuits and analyzing the two sub circuits with improved computation efficiency and processing speed.