Abstract: Fixed outline shaped and modifiable outline shaped random logic macros of an electronic circuit design are manipulated by modifying an outline of a modifiable outline shape macro based on criteria consisting of any one of a macro port weight value, a macro port ordering; a macro rapport constraint or a macro logic depth and placing resulting macros at locations on an integrated circuit (chip).

Abstract: An integrated circuit using area reconfigurable cells of a standard cell library includes standard cells placed adjacent with one another in rows and columns. Each of the standard cells has a boundary type and each has a body having a first pair of opposite sides and a second pair of opposite sides orthogonal to the first pair of opposite sides. Each standard cell also has a spacer located adjacent to each of the first pair of opposite sides of the body. The spacer has a spacer type that corresponds to the boundary type of the standard cell. The spacer is removable from the standard cell when the spacer has a spacer type that matches another spacer of an adjacent standard cell.

Abstract: Methods and/or associated devices and/or systems for creating integrated circuits (IC's) that have multiple connected I/O regions that can be designed and implemented using commonly available standard I/O libraries in conjunction with standard IC design flows and tools and in combination with one or more novel standardized I/O region interconnect cells for interconnecting between or through otherwise separated I/O regions. Specific embodiments support a wide variety of IC's that can be developed using standard libraries and design flows including: application specific integrated circuits (ASIC's), programmable logic devices (PLDs), custom IC's, analog IC's, CPU's, GPU's, and other IC's that require large numbers of input/ouput (IO) circuits while having relatively small core circuitry areas. Specific embodiments may involve innovative I/O cell functions, innovative IC topologies, and innovative IC packaging solutions for single die packages and multiple die packages.

Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

Abstract: A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.

Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.

Abstract: An integrated circuit with standard cells with top and bottom metal-1 and metal-2 power rails and with lateral standard cell borders that lie between an outermost vertical dummy poly lead from one standard cell and an adjacent standard cell. A DPT compatible standard cell design rule set. A method of forming an integrated circuit with standard cells constructed using a DPT compatible standard cell design rule set. A method of forming DPT compatible standard cells.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.

Abstract: A method is provided for designing an integrated circuit device. The method includes placing four transistors of a first transistor type and four transistors of a second transistor type within a gate electrode level. Each of the transistors includes a respective linear-shaped gate electrode segment positioned to extend lengthwise in a first direction. The transistors of the first and second transistor types are placed according to a substantially equal centerline-to-centerline spacing as measured perpendicular to the first direction. A first linear conductive segment is placed to electrically connect the gate electrodes of the first transistors of the first and second transistor types. A second linear conductive segment is placed to electrically connect the gate electrodes of the fourth transistors of the first and second transistor types. A third linear conductive segment is placed beside either the first or second linear conductive segment.

Abstract: Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.

Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

Abstract: Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level.

Abstract: A layout method of a semiconductor integrated circuit according to the present invention includes selecting M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from the same clock route; and replacing the M pieces of sequential circuits that are selected with one multi-data input/output sequential circuit including M pieces of input terminals and output terminals and one clock terminal that receives the clock distributed from the clock route.

Abstract: A method of common-centroid IC layout generation includes the following steps of acquiring a netlist of one circuit-element set; summing up the numbers of the unit element of all elements of the circuit-element set to get the total number of the unit elements and then determine the unit element array, the aspect ratio of which is closest to 1, via a combination operation; generating multiple common-centroid placements according to the unit element array and applying global routing assignment to each of the common-centroid placements; proceeding with cost evaluation in such a way that a cost calculation is applied to each of the common-centroid placements to get a corresponsive value; and comparing all of the common-centroid placements according to the values got from the cost evaluation and selecting the common-centroid placement corresponding to one of the values according to a predetermined condition for detailed routing.

Abstract: A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.

Abstract: In one embodiment, creating a layout for a Printed Circuit Board (PCB) by creating n boundary lines at n locations, respectively, on the PCB and placing n sets of electronic components on the n boundary lines, respectively; and iteratively adjusting and evaluating the layout of the PCB until a set of layout requirements for the PCB has been satisfied.

Abstract: A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

Abstract: A planar spiral induction coil includes a strip-shaped coil having at least one turn. The at least one turn has a width that changes as a distance from a beginning of the strip-shaped increases in a length direction of the strip-shaped coil. each turn of the at least one turn has a respective width that causes an equal current to flow through each turn of the at least one turn.

Abstract: In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.

Abstract: Techniques for placement in highly constraint chip architectures are described herein. In an example embodiment, a computer system places a digital portion of an electronic design for a programmable chip. The programmable chip comprises multiple fixed-function blocks and a plurality of pins, where each one of the multiple fixed-function blocks can be coupled only to a respective subset of the plurality of pins. The electronic design comprises a particular fixed-function block (FFB) instance that is connected to a particular input-output (IO) instance. The computer system places (e.g., by using a backtracking search) the particular FFB instance on a particular fixed-function block and the particular IO instance on a particular pin from a particular subset of the plurality of pins, where in the programmable chip the particular fixed-function block can be coupled only to the particular subset of the plurality of pins.

Abstract: Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively.

Abstract: A technique for implementing an clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.

Abstract: A method comprises selecting a region from a layout pattern of an integrated circuit, wherein the region comprises a plurality of functional units, and wherein the functional units are not coupled to each other through a variety of connection components, identifying hot spots in the region using a first threshold and inserting a plurality of decoupling capacitors adjacent to the hot spots.

Abstract: Micro-electro-mechanical structure (MEMS) capacitor devices, capacitor trimming for MEMS capacitor devices, and design structures are disclosed. The method includes identifying a process variation related to a formation of micro-electro-mechanical structure (MEMS) capacitor devices across a substrate. The method further includes providing design offsets or process offsets in electrode areas of the MEMS capacitor devices across the substrate, based on the identified process variation.

Abstract: A computer aided design application modifies a CAD drawing having one or more electrical components by optimizing a plurality of circuits and associated panels, and assigning circuit and panel identifiers to each component for producing an engineering drawing. Further such identified components can be placed in home run groups, implementing shortest path calculations for various wire types and using neutral wires sharing options for producing an engineering drawing illustrating the home run grouping and identifiers, panel schedules and complete bills of materials.

Abstract: System and methods for forming an integrated circuit using a standard cell library are provided. In some aspects, a method includes arranging cells from the standard cell library into a row between upper and lower power rails. Each cell includes a plurality of lateral nodes, at least one boundary region, and at least one dummy transistor. The method includes identifying a connection pattern of adjacent ones of the cells. The connection pattern is between (i) the lateral nodes of the adjacent cells and (ii) the upper and lower power rails. The method includes removing adjacent boundary regions of the adjacent cells based on the identified connection pattern of the adjacent cells, and modifying an arrangement of adjacent dummy transistors of the adjacent cells based on the removal of the adjacent boundary regions.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell.

Abstract: A design system provides data structures to store parameters of physical structures that can be viewed and modified in a front-end process through a logical design interface. In this way, system behavior defined by component structure can be evaluated and modified through a schematic representation of the data, regardless of a state of data representing the physical layout of interconnected physical structures. In electric circuit applications, for example, high frequency circuits can be incrementally designed and evaluated through structural parameters defined in a schematic diagram data abstraction without modifying and evaluating a layout data abstraction of the circuit directly.

Abstract: An electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites.

Abstract: A floorplanning method for an analog integrated circuit layout is disclosed. A first-type block is defined as a movable and deformable block with rectangle constraint, and a second-type block is defined as a fixed-size block without rectangle constraint. Each block in the floorplan is classified to the first-type or the second-type block. In a shape determination stage, a target shape is determined among candidates of the first-type block, the first-type block accordingly being modified to the target shape, resulting in at least one overlap in the floorplan. In an overlap elimination stage, neighboring blocks of each said overlap are analyzed, the overlap being then eliminated by utilizing surrounding space, resulting in unused space in the floorplan. In an enlargement stage, the unused space is utilized for enlarging the first-type block.

Abstract: A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract: A system and method are provided for establishing a debugging environment in an Electronic Design Automation work-flow. A user-interface is provided for interfacing with users by displaying a list of debuggable parameters, accepting a selection thereof, and automatically locating both the callback function which sets the selected parameter, and the source code file which contains the callback function. Additionally, it is determined whether the callback function sets solely the selected parameter, or several different parameters, and an automatic breakpoint is set accordingly to break only responsive to the selected parameter. On execution of the modified callback function, execution will be arrested by the automatically-set intelligent breakpoint and a debugging user-interface will be generated for the user to display the relevant source code, callback function, parameter names and values, system state, and the like. Upon completion of the debugging process, the automatically-set breakpoint will be removed.

Abstract: A method for generating legal colorable multiple patterning standard cell placement is provided. In this method, a standard cell library including color information can be accessed. For each standard cell, edge labels can be assigned based on colors of objects within a predetermined distance from each edge. A truth table, which indicates legal spacing between pairs of standard cells based on their edge labels, can be accessed. A plurality of standard cells of a design can then be placed based on the truth table.

Abstract: A mechanism is provided for determining connectivity while minimizing wiring in an electronic system. The mechanism identifies a configuration of the electronic system, a location of each module in a plurality of modules within the electronic system and at least one constraint with regard to wiring the electronic system, the location of each module being identified using three-dimensional coordinates. The mechanism routes a separate cable from each module in the plurality of modules to each of the other modules in the plurality of modules without violating any constraints, thereby forming a plurality of cables. The mechanism then generates a cabling list indicating how each cable in the plurality of cables is to be routed in the electronic system in order to not violate any constraints and provide connectivity while minimizing wiring.

Abstract: Techniques for use in integrated circuit design systems for reducing metal fill insertion time in the integrated circuit design process. In one example, a method includes the following steps. Metal fill data associated with a given layout from a placement and routing database of an integrated circuit design system is stored. The metal fill data is purged from the placement and routing database. At least one change to layout data in the placement and routing database is implemented. The stored metal fill data is loaded into the placement and routing database after the at least one change is implemented to the layout data. A check is performed for an existence of one or more violations associated with the metal fill data due to implementing the at least one change to the layout data in the placement and routing database. A correction procedure is performed on the metal fill data when one or more violations exist.

Abstract: A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow for the debugging of parameterized cells (PCELLS/PyCELLS) in a layout. A user may merely select a particular PCELL within a hierarchical PCELL and the system and method will determine dependencies thereof. The source code for the selected PCELL and its dependencies may be located and loaded. At least one breakpoint may be set in the source code of the selected PCELL. The source code for the selected PCELL and its dependencies may be executed to be arrested at the set breakpoints. Upon the arrest of execution, a debugging environment may be established and the located source code of the selected PCELL may be displayed along with values for parametric components thereof and progression control tools.

Abstract: Approaches for placing and routing a circuit design on a programmable integrated circuit (IC) are disclosed. One partial reconfiguration (PR) resource portion of the circuit design is selected from a plurality of PR resource portions of the design. Uncontained resources in the PR resource portion is identified. The PR resource portion, less the uncontained resources, is placed in an assigned region, and the uncontained resources is placed on the programmable IC unconstrained by the assigned region of the PR resource portion. The design is routed from the placed PR resource portion to the placed uncontained resources, and the process is repeated for each unplaced PR resource portion. After placing the plurality of PR resource portions and routing to uncontained resources in the plurality of PR resource portions, unplaced portions of the circuit design are placed and routed.

Abstract: A method is provided to align poly features within chain sets in an integrated circuit layout design stored in a non-transitory computer readable storage device comprising: vertically aligning a first poly feature of a first pcell instance in a first chain set with a second poly feature of a second pcell instance in a second chain set; configuring a computer to, starting with the aligned first and second poly features, successively determine multiple changed poly feature spacing values associated with at least one of the first and second pcell instances to align successive poly features in chain order in a first horizontal direction; and assigning respective determined changed poly feature spacing values to their associated first or second pcell instances.

Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

Abstract: A method for efficiently producing a design layout that includes several fills between and around nets of the design layout is described. The method of some embodiments first places a set of fills in the design layout. The method then performs a timing analysis on the design layout to find out the impact of the fills on the timing of the nets. The method identifies a region of the design layout in which to trim a set of fills in order to fix any timing violations of the nets. The method then trims the set of fills in the identified region. In some embodiments, the method employs different trimming strategies for trimming fills around different nets based on the characteristics of the nets.

Abstract: A multi-level integrated circuit, having a superposition of a first stack and a second stack of layers, and including a first row of electronic devices produced in the first stack, extending parallel to a first direction and fitting into a first volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H1; a second row of electronic devices produced in the second stack, extending parallel to the first direction and fitting into a second volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H2<H1; and a plurality of electrical connection elements passing through the second stack of layers, each connection element fitting into a third volume arranged on the first volume and next to the second volume.

Abstract: In a first process of a pattern generation method, a first segment to be handled which is not on a grid is extracted. In a second process, a second segment opposite to the first segment is extracted. In a third process, whether the second segment is on the grid is determined. In FIG. 1A, the second segment is not on the grid. Therefore, in a fourth process the first segment is shifted onto the grid under a determined condition. In addition, the second segment is shifted onto the grid so that line width between the first segment and the second segment is closest to target line width.

Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.

Abstract: Techniques are disclosed for improving bit slice placement and wiring. Some embodiments include swapping cells to improve routing. An alternative embodiment includes copying wiring from a first bit slice to a second bit slice. Another embodiment includes copying blocks or cells from a first bit slice to a second bit slice. Further, the wiring from the first bit slice may be copied to the second bit slice.

Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.

Abstract: A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.