Abstract: A system and method for discovering a set of possible iteration sequences for a given loop in a software program is described, to transform the loop representation. In a program containing a loop, the loop is partitioned into a plurality of portions based on splitting criteria. Labels are associated with the portions, and an initial loop automaton is constructed that represents the loop iterations as a regular language over the labels corresponding to the portions in the program. Subsequences of the labels are analyzed to determine infeasibility of the subsequences permitted in the automaton. The automaton is refined by removing all infeasible subsequences to discover a set of possible iteration sequences in the loop. The resulting loop automaton is used in a subsequent program verification or analysis technique to find violations of correctness properties in programs.

Abstract: Generating decode time instruction optimization (DTIO) object code that enables a DTIO enabled processor to optimize execution of DTIO instructions. A code sequence configured to facilitate DTIO in a DTIO enabled processor is identified by a computer. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A schedule associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified schedule that is configured to place the first instruction next to the second instruction. An object file is generated based on the modified schedule. The object file includes the first instruction placed next to the second instruction. The object file is emitted.

Abstract: A website optimisation system is integrated with a website by applying generic code to the website, that being the only code needed to be applied to the native source code of the website to enable the website optimisation system to optimise the website by altering one or more of: the data, functions or content assets of web pages in the website. Integration can be achieved on a one-time basis. The generic code can be placed into a website's page template or global page header, or manually to all pages in a website. The generic code can be just a single line of code, such as JAVASCRIPT code. The generic code remains the same irrespective of any differences in the data, functions or content assets of the web pages. The generic code includes code for all commands that enable tracking of the actions that relate to the optimisation objectives.

Abstract: A system, method and article of manufacture of increasing access speed of frequently accessed variables (symbols) in a dynamic language program. The system includes a range identifying unit to identify a range for communizing symbol accesses in the program; an instruction generating unit to generate instructions to access a symbol table using a key, to get an address of a symbol entry, and to store the address; an instruction extracting unit to fetch instructions from the identified range; and an instruction judging unit to determine whether or not each of the fetched instructions is an instruction to access the symbol. If the fetched instruction is an instruction to access the symbol, and the symbol is present when generating an instruction to access the symbol by using an address of the stored symbol entry, an instruction is generated allowing access to the symbol without checking whether the symbol is present.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: An execution trace of building blocks of computer code includes a head building block at which the execution trace starts, and a tail building block at which the execution trace ends. The building blocks are executable in a sequence from the head building block to the tail building block. The execution trace is truncated at a particular building block of the execution trace, which becomes the tail building block. The particular building block can correspond to a head building block of an additional execution trace, and/or to a loop header building block of a loop within the execution trace and at which the loop is entered. The execution trace is a compilation unit on which basis a trace-based compiler computer program generates an executable version of the code at least by compiling these units.

Abstract: A multiprocessor system has a background memory and a plurality of processing elements, each comprising a processor core and a cache circuit. The processor cores execute programs of instructions and the cache circuits cache background memory data accessed by the programs. A write back monitor circuit is used to buffer write addresses used for writing data by at least part of the processor cores. The programs contain commands to read the buffered write back addresses from the write back monitor circuit and commands from the programs to invalidate cached data for the write back addresses read by the commands to read the buffered write back addresses. Thus cache management is performed partly by hardware and partly by the program that uses the cache. The processing core may be a VLIW core, in which case instruction slots that are not used by the program can be made useful to include instructions for cache management.

Abstract: A cost oriented profiler (COP) mechanism that analyzes the behavior of input application source code with regard to the software total cost of ownership (TCO). The cost analysis tool provided by the mechanism analyzes the behavior of the source code and generates a cost report with indications as to the portions of the source code that have the most impact on the TCO of the application. Based on simulations and by comparing multiple versions of the source code, the COP mechanism determines if a particular change to the source code will increase or decrease software TCO. Behavior analysis, including static and dynamic analysis of the source code, is used to generate one or more code recommendations to reduce the TCO.

Abstract: A capability for limited customization that utilizes existing virtual dispatch table technology and allows selective customization is provided. Such a capability combines the usage of virtual dispatch tables with both customized and non-customized code to reduce, or even eliminate over-customization. Further, such a capability may employ a runtime system that decides what methods to customize based on several factors including, but not limited to the size of a class hierarchy, the amount of available space for compiled code, and the amount of available time for compilation.

Abstract: Embodiments disclosed herein relate to a process flow optimized directed graph traversal. In one embodiment, a processor performs a depth first traversal of the optimized directed graph where a node from a first node is not traversed until the nodes before the first node are traversed. The processor may output information associated with the nodes based on the traversal.

Abstract: A method, computer, and computer program for speculatively optimizing a code. The method includes speculatively optimizing the code characterized by searching in a predetermined order in at least one dictionary; extracting a value associated with a symbol name from a dictionary using the symbol name as a key; performing optimization to replace a symbol in the code with the value; compiling the code to be compiled including some or all of the optimized code; comparing, in response to detection of a change related to one dictionary among at least one dictionary, an order m in the predetermined order of the dictionary with the detected change to an order n of the dictionary with the extracted value; and invalidating the optimized code in the compiled code associated with the dictionary having the detected change in response to the results from the orders comparison and the type of change.

Abstract: Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least two multi-stage execution units that avow for parallel execution of tasks. The first custom computing apparatus optimizes the code for both parallelism and locality of operations on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: An embodiment includes a computer-implemented method of managing access control policies on a computer system having two high-level programming language environments. The method includes managing, by the computer system, a structured language environment. The method further includes managing, by the computer system, a dynamic language environment within the structured language environment. The method further includes receiving a policy. The policy is written in a dynamic language. The method further includes storing the policy in the dynamic language environment. The method further includes converting the policy from the dynamic language environment to the structured language environment. The method further includes generating a runtime in the structured language environment that includes the policy.

Abstract: Embodiments of the invention provide systems and methods for optimizing handling of breakpoints in a Java debugger agent. Embodiments provide a novel command that allows execution of the application in the debugger to stop or break at the beginning of a next called function or method (e.g., a “break on next called function” or “BNCF” command). When the BNCF command is given to the debugger, a flag may be set in the interpreter of the virtual machine to which the debugger is attached. On encountering a new method or function call, the flag is examined by the interpreter to determine whether it should stop or break in that call. If the flag is set, the interpreter will stop; otherwise the interpreter proceeds.

Abstract: A code optimizer is used to optimize a computer program that references a database by reading database metadata and making suitable optimizations based on the metadata. By taking into account the metadata of a database referenced in the computer program, the optimizer may make suitable optimizations to the computer program. Such optimizations include, without limitation, removing unnecessary calls to the database, removing unnecessary loops, removing unnecessary database operations, providing compile-time errors, and replacing dynamic calls with static data.

Abstract: A system and method for improving modularity of a software source code is provided. The system comprises of a user interface for receiving source code; a source code model extractor for parsing and forming a model of the source code; a source code model database for storing the source code model, refactoring operators, and a record of refactoring changes; a modularity improvement analyzer for reading the source code model and modularity problem diagnosis data and generating a set of prescriptions; an optimal improvement suggestion selector for evaluating and selecting prescriptions; and a refactoring engine for receiving selected prescriptions and applying them on the source code.

Abstract: A method, system and computer program product for performance configuration of an application by setting at least one performance preference for a performance-sensitive class in the application, specifying performance preference propagation policy of the class in the application based on the at least one performance preference, and calling the class to perform performance configuration for application according to the performance preference propagation policy.

Abstract: A novel eco-system is provided which first supplies a standardized template of one or more virtual machine images for software module providers/vendors. A plurality of modules executing on the virtual machine images is selected by a user to comprise a plurality of configurations. A suitable configuration may be determined according to a metric and the determined suitable configuration of software modules is subsequently used to build an end-to-end solution.

Abstract: Debugging source code includes: tracking, by a debugger during a debug session, duration of user examination of source code locations; providing, by the debugger to an optimizing compiler, a source code examination profile specifying source code locations examined by the user during the debug session; and receiving, by the debugger from the optimizing compiler: compiled source code for debugging, the compiled source code comprising, at each of one or more source code locations specified in the source code examination profile: a snapshot before the source code of the source code location, followed by an expanded snapshot, the expanded snapshot including computer program instructions to enable, during a debug session, examination of variable values changing during execution of the source code at the source code location; and a recording of snapshot locations and expanded snapshot locations.

Abstract: Mechanisms for optimized code generation targeting a high locality software cache are provided. Original computer code is parsed to identify memory references in the original computer code. Memory references are classified as either regular memory references or irregular memory references. Regular memory references are controlled by a high locality cache mechanism. Original computer code is transformed, by a compiler, to generate transformed computer code in which the regular memory references are grouped into one or more memory reference streams, each memory reference stream having a leading memory reference, a trailing memory reference, and one or more middle memory references.

Abstract: A software compiler is provided that is operable for generating an executable that comprises instructions for a plurality of different instruction sets as may be employed by different processors in a multi-processor system. The compiler may generate an executable that includes a first portion of instructions to be processed by a first instruction set (such as a first instruction set of a first processor in a multi-processor system) and a second portion of instructions to be processed by a second instruction set (such as a second instruction set of a second processor in a multi-processor system). Such executable may be generated for execution on a multi-processor system that comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set, and at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured.

Abstract: A method, tangible computer-readable medium and apparatus for concurrently executing subsystems in a graphical model is provided. An embodiment can transform a conventional graphical model supporting single threaded execution into a model supporting multi-threaded execution through the replacement of a single block. The transformed model may support concurrent execution of a plurality of subsystems using a plurality of threads when the graphical model executes. An embodiment provides a user interface that allows a user to intuitively configure a model for current execution of the subsystems.

Abstract: Mechanisms are provided for optimizing irregular memory references in computer code. These mechanisms may parse the computer code to identify memory references in the computer code. These mechanisms may further classify the memory references in the computer code as either regular memory references or irregular memory references. Moreover, the mechanisms may transform the computer code, by a compiler, to generate transformed computer code in which irregular memory references access a storage of a software cache of a data processing system through a transactional cache mechanism of the software cache.

Abstract: Techniques for processing computer code are disclosed. In one example, an indication that a computer code is to begin execution at a portion of code other than a starting portion of the code is received, and a runtime state associated with the portion of the code at which execution is to begin is constructed. In some examples, execution of the portion of code is initiated. In some examples, a program counter associated with the portion of the code is used to initiate execution of the code. In some examples, the computer code comprises a fallback code associated with a previously executing code.

Abstract: A system and method for reducing the bytecode execution time in the Java virtual machine are disclosed. The system includes a DB cache to store old machine code converted from a bytecode, a machine code change unit to change the old machine code to new machine code by removing a predetermined instruction included therein, a register management unit to manage stack data necessary for operations of the new machine code and a register file to provide a register region to conduct the operations, and a machine code information storage unit to store basic block information on the new machine code and spill and fill execution information in the stack of the register file.

Abstract: A computer-implemented method, apparatus, and computer program product to manage variable assignments in a program. The process identifies a set of variable assignments that is live on a portion of paths to form a set of identified variable assignments. Each of the set of identified variable assignments assign a value to at least one variable of a set of variables. The process determines a set of program points at which the set of identified variable assignments is live on all paths. The process also moves the set of identified variable assignments to the set of program points in response to determining that the set of identified variable assignments is movable to the set of program points.

Abstract: In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.

Abstract: A mechanism for performing register allocation based on priority spills and assignments is disclosed. A method of embodiments of the invention includes repetitively detecting fat points during a compilation process of a software program running on a virtual machine of a computer system, each fat point representing a program point having a high register pressure, the high register pressure occurs when a number of live program variables of the software program living at a given program point of the software program is greater than a number of available processor registers of the computer system. The method further includes choosing a fat point with a highest register pressure, selecting a live program variable having a lowest priority at the chosen fat point, and spilling the lowest priority live program variable to memory of the computer system.

Abstract: Performance of a program written in dynamic languages is improved through the use of a compiler that provides type inference for methods having a user-defined element. The user-defined element may be an input in a user-defined type. Though, the user-defined element may reflect that the method is user-defined. Type inference may be performed based on a user-defined mapping, relating input types to output types for one or more methods. The mapping may be specified as a data table provided to the compiler or as one or more functions that register with the compiler such that, as the compiler processes portions of a source program and detects a method with a user-defined element, the compiler may access the mapping and infer the type of an output of the method. The inferred type may then be used to optimize code dependent on that output.

Abstract: A mechanism for performing instruction scheduling based on register pressure sensitivity is disclosed. A method of embodiments of the invention includes performing a preliminary register pressure minimization on program points during a compilation process of a software program running on a virtual machine of a computer system. The method further includes calculating a register pressure at each of the program points, detecting an instruction to be scheduled, and performing instruction scheduling of the instruction based on a current register pressure at a current scheduling point and potential register pressures at subsequent scheduling points.

Abstract: Detection of redundant or duplicate method calls in a running program is provided. One or more methods can be selectively called when a program is running. Specified data is collected each time that a call to a given one of the methods occurs, wherein a given call to the given method is associated with a set of arguments comprising one or more particular argument values for the given method. The collected data includes an element uniquely identifying each of the particular argument values. The collected data is stored at a selected location, and a call threshold is selected for the given method, wherein the call threshold comprises a specified number of occurrences of the given call to the given method. The collected data is selectively analyzed at the storage location, to determine whether an occurrence of the given call to the given method has exceeded the call threshold.

Abstract: Dangling pointers and memory leak locations within software are detected. As the software allocates and deallocates memory, lists of pointers referencing the memory, and pointer status, are maintained. As the software writes new addresses within pointers and reads addresses referenced by the pointers, the pointer lists are maintained to determine whether the pointers are dangling and to detect memory leak locations. A balanced binary tree having a number of nodes can be maintained. The nodes represent heap or stack records. Each heap record corresponds to heap memory that has been allocated and has a list of pointers referencing the heap memory. Each stack record corresponds to a stack within which a stack frame is allocated each time a function is entered. The stack record has frame records corresponding to the stack frames. Each frame record has a list of pointers referencing the corresponding stack frame.

Abstract: A device receives, via a technical computing environment, a program that includes a parallel construct and a command to be executed by graphical processing units, and analyzes the program. The device also creates, based on the parallel construct and the analysis, one or more instances of the command to be executed in parallel by the graphical processing units, and transforms, via the technical computing environment, the one or more command instances into one or more command instances that are executable by the graphical processing units. The device further allocates the one or more transformed command instances to the graphical processing units for parallel execution, and receives, from the graphical processing units, one or more results associated with parallel execution of the one or more transformed command instances by the graphical processing units.

Abstract: A method of compiling code that includes partitioning instructions in the code among a plurality of processors based on memory access latency associated with the instructions is disclosed. According to one aspect of the invention, partitioning instructions includes partitioning memory access dependence chains. Other embodiments are described and claimed.

Abstract: Idle processor cores can be used to compile methods that are likely to be executed by a program based on profile data that is captured during one or more previous executions. Methods that are determined by the profile data to be likely to be used can be compiled eagerly on one or more background threads. Transparency can be achieved by ensuring that module load order is not altered because of the background threads by recording the state of loaded modules after each profiled compilation, persisting that data, and waiting to eagerly compile a method until the method to be compiled and all its dependencies has been loaded by the executing program.

Abstract: Using cache resident transaction hardware to accelerate a software transactional memory system. The method includes identifying a plurality of atomic operations intended to be performed by a software transactional memory system as transactional operations as part of a software transaction. The method further includes selecting at least a portion of the plurality of atomic operations. The method further includes attempting to perform the portion of the plurality of atomic operations as hardware transactions using cache resident transaction hardware.

Abstract: Computing responses to semantic queries. A method includes accessing a plurality of objects that represent source code for an input program. The source code is transformed into a plurality of immutable objects that are structured such that the immutable objects can be used to derive any response as defined by the semantic rules about the source code. A query is received from a requestor requesting a semantic characteristic of the input program. The semantic characteristic is calculated. The semantic characteristic is returned to the requestor. The semantic characteristic is cached in a cache. Information describing a dependency between the cached semantic characteristic and one or more of the objects in the plurality of objects is stored.

Abstract: Embodiments relate to solving conflicts in assembler programs. An aspect includes generating an internal representation of the control flow of the source code of the assembler program, the internal representation including nodes for every instruction and a directed edge for every possible flow of control between nodes. Data attributes are attributed to the nodes and/or the edges to store the information about whether the resource used by an instruction is available or for which amount of time is unavailable. A data-flow analysis is the applied to the internal representation of the control flow of the source code to determine whether the resource used by an instruction of the assembler program is available or for which amount of time is unavailable. Each node is checked for whether the instruction accesses a resource which is unavailable. An appropriate action is then taken to overcome the resource conflict.

Abstract: The rendering of sequential data-driven scenes. Each data-driven scene is constructed using a plurality of view components, each receiving data into its input parameters, and using construction logic to formulate a rendering of corresponding visual item(s). When a transition even is detected, the data-driven scene changes from one scene to the next. For instance, the transition might occur by changing any one or more of the following: changing the data that is applied to the view components, 2) changing the set of view components, 3) changing the dimension set, or 4) changing one or more geometries used to construct the scene. Thus, data-driven scenes may be presented sequentially.

Abstract: A device initiates a technical computing environment (TCE), and receives, via the TCE, a program command that permits the TCE to access a graphical processing unit that is remote to the device, where the program command permits the TCE to seamlessly transfer data to the remote GPU. The device transforms, via the TCE, the program command into a program command that is executable by the remote GPU, and provides the transformed program command to the remote GPU for execution. The device also receives, from the remote GPU, one or more results associated with execution of the transformed program command by the remote GPU, and utilizes the one or more results via the TCE.

Abstract: The present invention extends to methods, systems, and computer program products for optimizing execution of kernels. Embodiments of the invention include an optimization framework for optimizing runtime execution of kernels. During compilation, information about the execution properties of a kernel are identified and stored alongside the executable code for the kernel. At runtime, calling contexts access the information. The calling contexts interpret the information and optimize kernel execution based on the interpretation.

Abstract: Systems and methods for optimizing code may use transactional memory to optimize one code section by forcing another code section to execute atomically. Application source code may be analyzed to identify instructions in one code section that only need to be executed if there exists the possibility that another code section (e.g., a critical section) could be partially executed or that its results could be affected by interference. In response to identifying such instructions, alternate code may be generated that forces the critical section to be executed as an atomic transaction, e.g., using best-effort hardware transactional memory. This alternate code may replace the original code or may be included in an alternate execution path that can be conditionally selected for execution at runtime. The alternate code may elide the identified instructions (which are rendered unnecessary by the transaction) by removing them, or by including them in the alternate execution path.

Abstract: Mechanisms are provided for optimizing regular memory references in computer code. These mechanisms may parse the computer code to identify memory references in the computer code. These mechanisms may further classify the memory references in the computer code as either regular memory references or irregular memory references. Moreover, the mechanisms may transform the computer code, by a compiler, to generate transformed computer code in which regular memory references access a storage of a software cache of a data processing system through a high locality cache mechanism of the software cache.

Abstract: A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.

Abstract: Routines which are likely to be good candidates for cross-module inlining are automatically identified according to criteria based on service history, compiler inlining criteria, and/or execution performance criteria. Candidates can also be automatically identified by pattern matching codes of routines which satisfy service history, execution performance, and/or compiler criteria. Automatically identified candidate routines are presented in an inlining advisory tool, allowing developers to approve/veto automatically identified candidates, to add other routines, and to either suggest or require that the development tools perform cross-module inlining with particular routines. Changes to a candidate routine can trigger regeneration of native image(s) into which the routine has been compiled.

Abstract: A system and method for discovering a set of possible iteration sequences for a given loop in a software program is described, to transform the loop representation. In a program containing a loop, the loop is partitioned into a plurality of portions based on splitting criteria. Labels are associated with the portions, and an initial loop automaton is constructed that represents the loop iterations as a regular language over the labels corresponding to the portions in the program. Subsequences of the labels are analyzed to determine infeasibility of the subsequences permitted in the automaton. The automaton is refined by removing all infeasible subsequences to discover a set of possible iteration sequences in the loop. The resulting loop automaton is used in a subsequent program verification or analysis technique to find violations of correctness properties in programs.

Abstract: Described herein are optimizations of thread loop intermediate representation (IR) code. One embodiment involves an algorithm that, based on data-flow analysis, computes sets of temporary variables that are loaded at the beginning of a thread loop and stored upon exit from a thread loop. Another embodiment involves reducing the size of a thread loop trip for a commonly-found case where a piece of compute shader is executed by a single thread (or a compiler-analyzable range of threads). In yet another embodiment, compute shader thread indices are cached to avoid excessive divisions, further improving execution speed.

Abstract: A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the redirection instruction with a replacement instruction having a desired result resolved in accordance with the current machine state. The instructions that are replaced may be conditional branch instructions and the result a desired execution path. The examination of the machine state permits determination of a branch condition for the replacement instruction so that the next pass of the test code executes along the desired path. Alternatively, the handler can execute a jump to the branch instruction, causing immediate execution of the desired branch path.

Abstract: A mechanism for allocating statement frontier annotations to source code statements of a software program is disclosed. A method of embodiments of the invention includes generating statement frontier annotations during translation of source code statements of a software program on a computer system. The method further includes allocating the statement frontier annotations to the source code statements, wherein a statement frontier annotation indicates a frontier of a source code statement to which the statement frontier annotation is allocated.

Abstract: A computer implemented method, apparatus, and computer usable program code for monitoring and managing a stack. Usage of stack space is monitored for a plurality of threads. Usage of stack space is compared to a policy to form a comparison. An action is selectively initiated based on the comparison to the policy.