Abstract: Disclosed herein is a method of optimizing an executable program to improve instruction cache hit rate when executed on a processor. A method of predicting instruction cache behavior of an executable program is also disclosed. According to further aspects of the present invention, there is provided a software development tool product comprising code which when executed on a computer will perform the method of optimizing an executable program. A linker product and a computer program are also disclosed.

Abstract: A system and method for optimizing the object codes of a computer program is disclosed. The method includes receiving one or more object code units associated with an executable program; identifying, among the object code units, a first program entity and a first set of operations associated with the first program entity and a second program entity and a second set of operations associated with the second program entity, each program entity having an object code segment and an associated address; updating the object code units by inserting a predefined instruction before the first program entity's object code segment and causing the second set of operations to be associated with the predefined instruction if the first program entity's object code segment is identical to the second program entity's object code segment; and combining the updated object code units into the executable program.

Abstract: A compiling system and method for optimizing binary code. The method includes the step of replacing a memory access on a stack area in order to save a value of a register with local variable access. The method further includes: giving a call number to a call instruction and an inlined code in response to an inline expansion of a code to be called by the call instruction; creating a parent-child relationship information for at least one of the call number; processing the memory accesses with an escaped stack pointer as a base address if a stack pointer has escaped; prohibiting a replacement of a prohibited memory access if the stack pointer has escaped; and replacing unprohibited memory access with the local variable access if the stack pointer has escaped.

Abstract: The display of a debugging interface for use with parallel computing. When a break state has been entered in a particular code context (such as a method) by a particular execution context (such as a thread), related execution contexts are found that were also executing in the particular code context. While in the break state, multiple expressions are then evaluated for each of the execution contexts. The results are then displayed with perhaps navigation controls that allow the results to be efficiently navigated.

Abstract: In one embodiment, a decision tree is evaluated in interpreted mode while statistics are collected. The decision tree is then represented as source code, and each decision in the decision tree is annotated with instructions determined based on the collected statistics. The source code is compiled into machine code, and the machine code is optimized based on the instructions annotating each decision in the decision tree.

Abstract: The present invention extends to methods, systems, and computer program products for block count based procedure layout and splitting. Embodiments of the invention utilize code block counts to provide a total ordering of code blocks that improves execution time of generated procedure code by minimizing branches along more frequently executed paths. The total ordering is optimized using prioritized precedence relationships. For example, the total ordering is optimized to maximize the appropriate placement of code block chains after other code block chains. The total ordering is also optimized to place zero count (untouched) code blocks after any non-zero (touched) code blocks.

Abstract: A method and an apparatus that instructs a compiler server to build or otherwise obtain a compiled code corresponding to a compilation request received from an application are described. The compiler server may be configured to compile source codes for a plurality of independent applications, each running in a separate process, using a plurality of independent compilers, each running in a separate compiler process. A search may be performed in a cache for a compiled code that satisfies a compilation request received from an application. A reply message including the compiled code can be provided for the application, wherein the compiled code is compiled in direct response to the request, or is obtained from the cache if the search identifies in the cache the compiled code that satisfies the compilation request.

Abstract: Disclosed herein are methods and systems for using on stack replacement for optimization of software. A source code is compiled into an unoptimized code on a computing device. The unoptimized code is then executed on a computing device. A hot count is incremented. It is then determined whether a function within the unoptimized code is hot. If a function is determined to be hot, an OSR triggering code is inserted at a back edge of each loop within the function. The OSR triggering code is configured to trigger OSR at a loop depth that is less than the hot count.

Abstract: Methods and apparatus to data dependence testing for loop fusion, e.g., with code replication, array contraction, and/or loop interchange, are described. In one embodiment, a compiler may optimize code for efficient execution during run-time by testing for dependencies associated with improving memory locality through code replication in loops that enable various loop transformations. Other embodiments are also described.

Abstract: A method of providing transports for a data distribution middleware over a plurality of transport networks is provided. A data distribution middleware with a pluggable transport layer is provided. A plurality of transport plugins in the transport layer are provided. Aliases are assigned to each of the transport plugins of the plurality of transport plugins, wherein at least one of the transport plugins of the plurality of transport plugins has a plurality of aliases.

Abstract: A compiler includes a register allocator for allocating registers for instructions in a program to be compiled, and a code generator for generating object code based on the register allocation results performed by the register allocator. The register allocator allocates logical registers for instructions in the program to be compiled. The register allocation further allocates, to physical registers, the logical registers that are allocated to the instructions of the program, so that the physical registers that are live at a procedure call in the program to be compiled are allocated from the bottom of the register stack.

Abstract: Described is a technology by which a series of loop nests corresponding to source code are detected by a compiler, with the series of loop nests tiled together, (thereby increasing the ratio of cache hits to misses in a multi-processor environment). The compiler transforms the series of loop nests into a plurality of tile loops within a controller loop, including using dependency analysis to determine which results from a tile loop need to be pre-computed before another tile loop. For dependency analysis, the compiler may use a directed acyclic graph as a high-level intermediate representation, and split the graph into sub-graphs each representing an array. The compiler uses descriptors processed from the graph to determine the controller loop and the tile loops within that controller loop.

Abstract: A technique includes providing first objects that are associated with an application session and in a processor-based system, identifying second objects in another application session corresponding to the first objects based at least in part on a comparison of the second objects to matching rules associated with the first objects.

Abstract: Methods, apparatus and computer software product for local memory compaction are provided. In an exemplary embodiment, a processor in connection with a memory compaction module identifies inefficiencies in array references contained within in received source code, allocates a local array and maps the data from the inefficient array reference to the local array in a manner which improves the memory size requirements for storing and accessing the data. In another embodiment, a computer software product implementing a local memory compaction module is provided. In a further embodiment a computing apparatus is provided. The computing apparatus is configured to improve the efficiency of data storage in array references. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: A code generation system comprises a model analyzer configured to identify data dependencies in a data flow diagram that describes functional behavior of an application, wherein the model analyzer is further configured to compute a data and computation map based on the data dependencies and to compute one or more implementation constraints; a model partitioner configured to compute one or more partition boundaries based on the data and computation map and the one or more implementation constraints; and a code generator configured to generate parallelized code based on the data flow diagram, the one or more implementation constraints, and the one or more partition boundaries, wherein the code generator is configured to map the code corresponding to each partition defined by the one or more partition boundaries to one of a plurality of cores of a multi-core processor, and to generate inter-core communication code for at least one line of the data and computation map crossed by the one or more partition boundari

Abstract: Memoization may be deployed using a configuration file or database that identifies functions to memorize, and in some cases, includes input and result values for those functions. At compile time, functions defined in the configuration file may be captured and memoized. During compilation or other pre-execution analysis, the executable code may be modified or otherwise decorated to include memoization code. The memoization code may store results from a function during the first execution, then merely look up the results when the function may be called again. The memoized value may be stored in the configuration file or in another data store. In some embodiments, the modified executable code may operate in conjunction with an execution environment, where the execution environment may optionally perform the memoization.

Abstract: A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on instructions of the DSP processor, wherein the cluster information is provided by a program with cluster intrinsic coding; identifying data stream operations indicating parallel instruction sequences applied on different data sets in the program representation; identifying data sharing relations indicating data shared by the data stream operations in the program representation; identifying data aggregation relations indicating results aggregated from the data stream operations in the program representation; and performing register allocation for the DSP processor according to the identified data stream operations, the data sharing relations and the data aggregation relations.

Abstract: A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common across multiple logical entities. The functions to be instantiated are determined, for instance, dynamically during run-time.

Abstract: Embodiments are directed to tracking variable location information in optimized code and efficiently collecting and storing reaching definition information. A computer system receives a portion of source code at a compiler, where the compiler is configured to compile and optimize the source code for execution. The computer system tags selected variables in the source code with a tag, where the tag is configured to provide location information for the variable. The computer system optimizes the received portion of source code including changing at least one of the tagged variables. The computer system also tracks the tagged variables as the variables are changed by the compiler during code optimization and persists the variable location information, so that the persisted variable location information is available to other compiler components.

Abstract: Various methods are provided directed to a compiler-guided software accelerator for iterative HADOOP jobs. A method includes identifying intermediate data, generated by an iterative HADOOP application, below a predetermined threshold size and used less than a predetermined threshold time period. The intermediate data is stored in a memory device. The method further includes minimizing input, output, and synchronization overhead for the intermediate data by selectively using at any given time any one of a Message Passing Interface and Distributed File System as a communication layer. The Message Passing Interface is co-located with the HADOOP Distributed File System.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to externally stored static elements for a document in a document editor and provide a method, system and computer program product for moving static elements for a document between an external file and the document in a document editor. A data processing system for moving static elements for a document between an external file and the document in a document editor can include an automated de-externalization and re-externalization processor coupled to a document editor. The automated de-externalization and re-externalization processor can include program code enabled both to replace static elements in a subject document with static element references while storing replaced static elements in entries in an external file, and also to replace static element references in the subject document with corresponding static elements stored in the entries in the external file.

Abstract: A method and apparatus for optimizing source code for use in a parallel computing environment by compiling an application source code, performing analysis, and optimizing the application source code. At the time of compilation, a compiler adds instrumentation to a prepared executable. An analysis program then analyzes the prepared executable and generates an analysis result. The analysis result is then used by the analysis program to optimize the application source code for parallel processing.

Abstract: The present invention provides a method to optimize object code files produced by a compiler for several different types of target processors. The compiler divides the source code to be compiled into several functional modules. Given a specified set of target processors, each functional module is compiled resulting in a target object version for each target processor. Then, for each functional module, a merging process is performed wherein identical target object versions or target object versions with similar contents are merged by deleting the identical or similar versions. After this merging process, a composite object code file is formed containing all of the non-deleted target object versions of the function modules.

Abstract: In one embodiment, symbolically executing a software module having a number of execution paths; and losslessly reducing the number of execution paths during the symbolic execution of the software module.

Abstract: A process for check pointing in speculative execution frameworks, identifies calls to a set of setjmp/longjmp instructions to form identified calls to setjmp/longjmp, determines a control flow path between a call to a setjmp and a longjmp pair of instructions in the identified calls to setjmp/longjmp and replaces calls to the setjmp/longjmp pair of instructions with calls to an improved_setjmp and improved_longjmp instruction pair. The process creates a context data structure in memory, computes a non-volatile save/restore set and replaces the call to improved_setjmp of the setjmp/longjmp pair of instructions with instructions to save all required non-volatile and special purpose registers and replaces a call to improved_longjmp of the setjmp/longjmp pair of instructions with instructions to restore all required non-volatile and special purpose registers and to branch to an instruction immediately following a block of code containing the call to improved_setjmp.

Abstract: Technologies are generally described for runtime optimization adjusted dynamically according to changing costs of one or more system resources. Multicore systems may encounter dynamic variations in performance associated with the relative cost of related system resources. Furthermore, multicore systems can experience dramatic variations in resource availability and costs. A dynamic registry of system resource costs can be utilized to guide dynamic optimization. The relative scarcity of each resource can be updated dynamically within the registry of system resource costs. A runtime code generating loader and optimizer may be adapted to adjust optimization according to the resource cost registry. Information regarding system resource costs can support optimization tradeoffs based on resource cost functions.

Abstract: A method of reproducing runtime environment for debugging an application includes reading an optimizer file from a non-volatile storage medium. The optimizer file includes a runtime environment, application definition information, and a log. The log includes summaries of events, actions, and a time mark of occurrence for each of the actions. A runtime environment for debugging the application is then defined and the application runtime is set up using the application definition information in the optimizer file. Further, the method includes running the application, attaching an optimizer, and triggering each of the actions to occur at a time mark of occurrence associated with each of the actions. Then, each of the actions and associated events is analyzed by comparing the events produced by running the application with the events in the optimizer file. If a fault is produced by the triggering, a debugger is invoked to analyze the fault.

Abstract: A method for vectorization of a block of code is provided. The method comprises receiving a first block of code as input; and converting the first block of code into at least a second block of code and a third block of code. The first block of code accesses a first set of memory addresses that are potentially misaligned. The second block of code performs conditional leaping address incrementation to selectively access a first subset of the first set of memory addresses. The third block of code accesses a second subset of the first set of memory addresses starting from an aligned memory address, simultaneously accessing multiple memory addresses at a time. No memory address belongs to both the first subset and the second subset of memory addresses.

Abstract: Technologies are generally described for parallel dynamic optimization using multicore processors. A runtime compiler may be adapted to generate multiple instances of executable code from a portable intermediate software module. The various instances of executable code may be generated with variations of optimization parameters such that the code instances each express different optimization attempts. A multicore processor may be leveraged to simultaneously execute some, or all, of the various code instances. Preferred optimization parameters may be determined from the executable code instances that may correctly complete in the least time, or may use the least amount of memory, or that may prove superior according to some other fitness metric. Preferred optimization parameters may be used to seed future optimization attempts. Output generated from the preferred instances may be used as soon as the first instance correctly completes block.

Abstract: Embodiments of a computer system that determines a performance metric are described. During operation, the computer system determines the performance metric for tasks performed by financial software during a time interval. This performance metric is based on a weighted summation of contributions from the tasks, and a given weight associated with a given task is based on a frequency of occurrence of the given task. Then, the computer system performs a remedial action to improve the determined performance metric during a subsequent time interval.

Abstract: A method and system for updating tuning parameters associated with a controller without repetitive compilation of a controller code. The controller code represents an algorithm associated with the controller and can be compiled separately from a data set representing a solution for an optimization problem and also from a data set representing parameters required for prediction. The algorithm can be implemented in a programming language code suitable for implementation on an embedded platform or other types of computer platforms. The data sets can be represented in a specified data structure and the variables associated with the data structure can be declared in the controller template code. The variables can be updated independently without varying the compiled code associated with the controller algorithm that is referring to the variables. The controller can also be updated while the controller actively performs online.

Abstract: Compiling software for a hierarchical distributed processing system including providing to one or more compiling nodes software to be compiled, wherein at least a portion of the software to be compiled is to be executed by one or more other nodes; compiling, by the compiling node, the software; maintaining, by the compiling node, any compiled software to be executed on the compiling node; selecting, by the compiling node, one or more nodes in a next tier of the hierarchy of the distributed processing system in dependence upon whether any compiled software is for the selected node or the selected node's descendants; sending to the selected node only the compiled software to be executed by the selected node or selected node's descendant.

Abstract: There is provided an autonomic software system and method for normalizing a profile collected for an executing application to account for one or more actions applied to the executing application after the profile was collected, comprising: predicting an impact of applying the one or more actions to the executing application by utilizing the profile and the one or more actions; and adjusting the profile to form a normalized profile according to the predicted impact. A plurality of different a profile consumers, such as, a phase shift detector, an action evaluator as well as a normalizing controller, may utilize the normalized profile to improve the behavior of the executing application. In addition, online visualization tools may be implemented to graphically depict the normalized profiles, as well as differences between the collected profiles and the normalized profiles.

Abstract: A method, and system employing the method, for service channel reconfiguration at a service outlet includes generating service transaction data of a service outlet, generating queue management system (QMS) data of the service outlet, and generating cost and profit data for the service outlet. Data is extracted from the service transaction data and the QMS data relating to specified parameters including customer experience data, and customer demand data. The service transaction data and the QMS data is integrated with the cost and profit data providing a unified objective function. Stochastic service processes and customer behavior data are modeled. The unified objective function is evaluated using the stochastic service processes and customer behavior data model, and the service channel function of the service outlet is reconfigured using the unified objective function.

Abstract: Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.

Abstract: A method and an apparatus that optimally compile a source code for a data transformation operation in response to a request from a run-time application are described. A current state of the run-time application is included in the request. The application executes a non-optimized library routine for the data transformation operation while a separate worker thread performs optimized code compilation on the source code for the data transformation operation based on the request at the same time. The request includes a current state of the run-time application. The non-optimized library routine has been pre-built during build time.

Abstract: Compiling code for an enhanced application binary interface (ABI) including identifying, by a computer, a code sequence configured to perform a variable address reference table function including an access to a variable at an offset outside of a location in a variable address reference table. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A scheduler cost function associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified scheduler cost function that is configured to place the first instruction next to the second instruction. An object file is generated responsive to the modified scheduler cost function. The object file includes the first instruction placed next to the second instruction. The object file is emitted.

Abstract: In a managed execution environment, an error may be deferred until execution of the application, program, function, or other assemblage of code reaches a point at which calling the reference to a module associated with a missing type or type member becomes inevitable.

Abstract: A code sequence made up multiple instructions and specifying an offset from a base address is identified in an object file. The offset from the base address corresponds to an offset location in a memory configured for storing an address of a variable or data. The identified code sequence is configured to perform a memory reference function or a memory address computation function. It is determined that the offset location is within a specified distance of the base address and that a replacement of the identified code sequence with a replacement code sequence will not alter program semantics. The identified code sequence in the object file is replaced with the replacement code sequence that includes a no-operation (NOP) instruction or having fewer instructions than the identified code sequence. Linked executable code is generated based on the object file and the linked executable code is emitted.

Abstract: A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.

Abstract: A method and apparatus for rendering 3D graphics data. The method includes analyzing a characteristic of input 3D graphics data, reconstructing a rendering function based on the analyzed characteristic, and rendering the input 3D graphics data using the reconstructed rendering function. The characteristic of 3D graphics data to be rendered is analyzed and a rendering function is reconstructed only using code blocks corresponding to the analyzed characteristic, thereby minimizing the size of the rendering function.

Abstract: A method and apparatus for dynamic optimization of strong atomicity barriers is herein described. During runtime compilation, code including non-transactional memory accesses that are to conflict with transactional memory accesses is patched to insert transactional barriers at the conflicting non-transactional memory accesses to ensure isolation and strong atomicity. However, barriers are omitted or removed from non-transactional memory accesses that do not conflict with transactional memory accesses to reduce barrier execution overhead.

Abstract: A dynamic compiling method, and device for sequentially compiling a partial computer program in a computer. The computer runs methods to acquire respective values of one or more pieces of current execution status information; read, from the shared pool, a list of the conditions associated with an executable instruction stream generated by compiling a partial program that is the same as a partial program to be compiled, and determine whether respective values of corresponding pieces of current execution status information satisfy the conditions. The computer runs methods to further generate an executable instruction stream by compiling the partial program to be compiled on the condition that a result of determination made is negative.

Abstract: The tool, MC/DC-Automatic Tool Generator automatically generates test data to satisfy Modified Condition Decision Coverage (MCDC) from input code/model. This tool reduces the effort required to generate MCDC test data significantly. In order to reduce the time required by model checkers, abstraction and optimization methodologies have been implemented to analyze typical reactive software model/code.

Abstract: A computer software execution system may have a configurable memory allocation and management system. A configuration file or other definition may be created by analyzing a running application and determining an optimized set of settings for the application on the fly. The settings may include memory allocated to individual processes, memory allocation and deallocation schemes, garbage collection policies, and other settings. The optimization analysis may be performed offline from the execution system. The execution environment may capture processes during creation, then allocate memory and configure memory management settings for each individual process.

Abstract: A processor framework includes a compiler to add control information to an instruction sequence at compile time. The control information is added in the instruction sequence prior to a control-flow changing instruction. Microarchitecture is configured to use the control information at runtime to predict an outcome of the control-flow changing instruction prior to fetching the control-flow changing instruction.

Abstract: A device (D) is intended for optimizing composite applications comprising at least two orchestrated activities participating to at least one process. This device (D) comprises i) an analyzing means (AM) arranged for determining orchestrated activities contained into a composite application to be optimized and dependencies between these activities, and ii) an optimizing means (OM) arranged for determining a new orchestration between the determined activities which allows the composite application to execute requests of users in a minimal time, according to the determined dependencies and to predefined rules, and for outputting an optimized composite application based on the new orchestration.

Abstract: Various technologies and techniques are disclosed that provide software transactional protection of managed pointers. A software transactional memory system interacts with and/or includes a compiler. At compile time, the compiler determines that there are one or more reference arguments in one or more code segments being compiled whose source cannot be recovered. The compiler executes a procedure to select one or more appropriate techniques or combinations thereof for communicating the sources of the referenced variables to the called code segments to ensure the referenced variables can be recovered when needed. Some examples of these techniques include a fattened by-ref technique, a static fattening technique, a dynamic ByRefInfo type technique, and others. One or more combinations of these techniques can be used as appropriate.

Abstract: Embodiments of systems, methods and computer program products are described for implementing repository relationship programming. Implementations described herein describe processes for implementing a union of concerns, integrating concerns, assembling concerns and separating concerns.

Abstract: One set of instructions is generated in part by compiling application-specific source code. When natively executed on a platform provided by a device, the set of instructions provides an application. Another set of instructions is generated in part by compiling the same business logic source code. When natively executed on another platform provided by another device, the other set of instructions provides the same application. The business logic source code is substantially free of code specific to any platform. Moreover, the business logic source code defines substantially all application-specific functionality of the application.