Abstract: A spilling method in register files for a processor is proposed. The processor with Parallel Architecture Core structure includes multiple clusters and a memory. Each cluster includes multiple function units (M-Unit and I-Unit), multiple local register files and a global register file. The local register files are used by the multiple function units, respectively. For a specified live range, the method includes calculating communication costs of the local register files and the global register file in each cluster, and communication cost of the memory for spilling the live range when spilling occurs; calculating use ratios of the local register files and the global register file in each cluster, and use ratio of the memory for the live range; and selecting one of the local register files and the global register file in each cluster and the memory for spilling the live range based on the communication costs and use ratios.

Abstract: Method for optimizing a control program for actuators, wherein by means of the control program, at least one first function comprising the allocated program lines is executed to control a first actuator, the control program being in the form of an executable model in a first step, and, based on the model, an instrumented program code being generated by a code generator for a test control program, and a first parameter being allocated to the first function, and wherein by means of a test unit, the test control program is processed repeatedly with predefined input values and, based on the result of this processing, a value is allocated to the first parameter, and the value allocated to the first parameter is stored in a memory area allocated to the model, and in a second step, the optimized control program is generated by the code generator, the value allocated to the first parameter being read out of the allocated memory area by an optimization unit of the code generator and compared with a predefined threshol

Abstract: A method and an apparatus that modify pointer values pointing to typed data with type information are described. The type information can be automatically checked against the typed data leveraging hardware based safety check mechanisms when performing memory access operations to the typed data via the modified pointer values. As a result, hardware built in logic can be used for a broad class of programming language safety check when executing software codes using modified pointers that are subject to the safety check without executing compare and branch instructions in the software codes.

Abstract: A method and an apparatus that optimize operations for a key among a collection of key indexed data structures using meta data describing properties of the key with respect to the collection of data structures are described. The meta data may correspond to a cache dynamically updated to indicate invariants which are true for the key in a current state of the collection of data structures. Expensive calculations to search through the collection of data structures for the key may be avoided. For example, costly lookup operations over a collection of data structures may not be required at all if a key is known to always (or to never) reference certain specific values, or for these values to have certain meta-properties, in any of the collection of data structure globally throughout a system at a current state.

Abstract: There is provided a computer-implemented method of performing ownership acquire policy selection. The method includes compiling an atomic section to generate an instrumented executable. The instrumented executable is configured to generate a runtime abort graph describing a plurality of computer memory accesses made by the instrumented executable. The method also includes selecting each of a plurality of policies based on the runtime abort graph. The plurality of policies include a first policy and a second policy. The first policy is different from the second policy. The method further includes compiling the atomic section to generate a modified executable. The modified executable is configured to perform the computer memory accesses according to the selected policies.

Abstract: In an embodiment, hardware implementing a transcendental or other non-linear function is based on a series expansion of the function. For example, a Taylor series expansion may be used as the basis. One or more of the initial terms of the Taylor series may be used, and may be implemented in hardware. In some embodiments, modifications to the Taylor series expansion may be used to increase the accuracy of the result. In one embodiment, a variety of bit widths for the function operands may be acceptable for use in a given implementation. A methodology for building a library of series-approximated components for use in integrated circuit design is provided which synthesizes the acceptable implementations and tests the results for accuracy. A smallest (area-wise) implementation which produces a desired level of accuracy may be selected as the library element.

Abstract: A method and system are provided in which one or more processors may be operable to generate an intermediate representation of a shader source code, wherein the intermediate representation comprises one or more whole-program data flow graph representations of the shader source code. The one or more processors may be operable to generate machine code based on the generated intermediate representation of the shader source code. The one or more whole-program data flow graph representations of the shader source code may be generated utilizing a compiler front end. The machine code may be generated utilizing a compiler back end. The generated machine code may be executable by a graphics processor. The generated machine code may be executable by a processor comprising a single-instruction multiple-data (SIMD) architecture. The generated machine code may be executable to perform coordinate and/or vertex shading of image primitives.

Abstract: In one embodiment, a method comprises generating a first executable program optimized for an executable system based on compiling a program relative to an initial set of independent optimization metrics; determining first performance metrics based on the executable system executing the first executable program; adjusting the initial set of independent optimization metrics based on the first performance metrics to generate a second set of independent optimization metrics; and generating a second executable program, based on compiling the program relative to the second set of independent optimization metrics, for improved execution of the program in the executable system.

Abstract: A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include associating with each register a symbolic expression selected from a set of possible symbolic expressions, locating an operation, if any, that is next within the sequence of operations and setting that operation to be a working operation, where the working operation has associated therewith a destination register and zero or more source registers, and processing the working operation when the working operation and any symbolic expressions of its source registers, if any, match at least one of a set of rules, where each rule specifies that the working operation must match a subset of the operation set, where each rule also specifies that the symbolic expressions, if any, of any source registers of the working operation must match a subset of the possible symbolic expressions, and where the rule also specifies a result, then posting the result as the symbolic expression of the destination

Abstract: A shared memory architecture is disclosed to support operations associated with executing shared functions from a shared memory space in such a manner that separate pieces of software can execute the shared functions.

Abstract: A system performs operations comprising creating a call graph for a program translated from source code, identifying redundant exception handling code in the program utilizing the call graph, and removing the redundant exception handling code. The operation of identifying redundant exception handling code may comprise identifying at least one function or callsite by determining that a first function in the at least one function's or callsite's callee chain throws an exception and that the exception is handled by a second function in the function's or callsite's callee chain or by determining that an exception is not thrown in the at least one function's or callsite's callee chain. The operation of removing the redundant exception handling code may comprise removing redundant exception handling code included in at least one function or callsite and/or removing at least one entry for the at least one function or callsite from an exception lookup table.

Abstract: The present disclosure includes a shader compiler system and method. In an embodiment, a shader compiler includes a decoder to translate an instruction having a vector representation to a unified instruction representation. The shader compiler also includes an encoder to translate an instruction having a unified instruction representation to a processor executable instruction.

Abstract: A compiler may optimize source code and any referenced libraries to execute on a plurality of different processor architecture implementations. For example, if a compute node has three different types of processors with three different architecture implementations, the compiler may compile the source code and generate three versions of object code where each version is optimized for one of the three different processor types. After compiling the source code, the resultant executable code may contain the necessary information for selecting between the three versions. For example, when a program loader assigns the executable code to the processor, the system determines the processor's type and ensures only the optimized version that corresponds to that type is executed. Thus, the operating system is free to assign the executable code to any processor based on, for example, the current status of the processor (i.e.

Abstract: The invention includes a computerized method responding to a navigation cue from a user by saving the writable state of the application and directing the computer through the window operating system to perform the navigation task 36 indicated by the navigation cue. The invention includes the following, which will each be discussed in turn. An alteration mechanism including means for altering window operating system by altering the hook triggered by each navigation cue to integrate saving the writable state. The window operating system integrating response to each navigation cue and saving the writable state. Source code artifacts which can be installed to implement navigation cues triggering saving the writable state. A business method generating revenue for a business entity.

Abstract: Mechanisms are provided for optimizing code to perform prefetching of data into a shared memory of a computing device that is shared by a plurality of threads that execute on the computing device. A memory stream of a portion of code that is shared by the plurality of threads is identified. A set of prefetch instructions is distributed across the plurality of threads. Prefetch instructions are inserted into the instruction sequences of the plurality of threads such that each instruction sequence has a separate sub-portion of the set of prefetch instructions, thereby generating optimized code. Executable code is generated based on the optimized code and stored in a storage device. The executable code, when executed, performs the prefetches associated with the distributed set of prefetch instructions in a shared manner across the plurality of threads.

Abstract: A method for validating a translation of a graphical workflow of activities into an arbitrary, but structured language uses as input a term of a high level graphically expressed language having a number of graphical elements related logically to each other and analyzes its content and/or structure in order to translate this content and/or structure into a structured set of instructions. The graphical workflow of activities is simulated to arrive at a first set of activity results. Each instruction is translated into a generic language in order to trace the execution of such instruction to arrive at a second set of results from the translated instructions. The first set of activity results is compared with the second set of results, and the translation is validated in case of a match among the first set of activity results and the second set of results.

Abstract: The present invention teaches a variety of systems, platforms, applications, and methods, and relates to mobile platforms, embedded native applications, Java virtual machines, user interfaces, and the like. The present invention discloses a mobile platform which unifies the worlds of the Java virtual machine and native applications to provide a unified and consistent environment for multitasking both Java and native applications within a mobile device.

Abstract: The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.

Abstract: Optimizing program code in a static compiler by determining the live ranges of variables and determining which live ranges are candidates for moving code from the use site to the definition site of source code. Live ranges for variables in a flow graph are determined. Selected live ranges are determined as candidates in which code will be moved from a use site within the source code to a definition site within the source code. Optimization opportunities within the source code are identified based on the code motion.

Abstract: Techniques for performing capacity planning for applications running on a computational infrastructure are provided. The techniques include instrumenting an application under development to receive one or more performance metrics under a physical deployment plan, receiving the one or more performance metrics from the computational infrastructure hosting one or more applications that are currently running, using a predictive inference engine to determine how the application under development can be deployed, and using the determination to perform capacity planning for the applications on the computational infrastructure.

Abstract: Disclosed is a system and method for maintaining software instructions stored in a wireless communications device memory. The software is organized using code sections, where each code section is in a contiguous portion of memory and relocatable independently of other code sections. Maintenance includes the ability to run a unique software component called a compactor while the normal system is not in executable form. The compactor expands, compresses, and relocates code sections to allow downloaded code to be incorporated into the system code base.

Abstract: Detecting locking discipline violations on shared resources. For example, a method of detecting locking discipline violations of shared resources of a computing platform, by a testing process to be executed concurrently with one or more other processes on said computing platform, the testing process comprising: locking a shared resource of said computing platform; reading a value of the shared resource; locally storing the value of the shared resource; rereading the value of the shared resource after a predefined time period; and generating a locking discipline violation report if the value of said shared resource as reread by said rereading is different from the value of said resource as locally stored by said locally storing.

Abstract: A method for compiling a program including a loop is provided. In the program, the loop includes K instructions (K>2) and repeats for M times (M>2). The compiling method comprises following steps: performing resource conflict analysis to the K instructions in the loop; dividing the K instructions in the loop into a first combined instruction section, a connection instruction section and a second combined instruction section, wherein there is no resource conflict between the instructions in the first combined instruction section and the instructions in the second combined instruction section respectively; and compiling the program, wherein the instructions in the first combined instruction section in the cycle N (N=2, 3, . . . M) and the instructions in the second combined instruction section in the cycle N?1 are combined to be compiled respectively. A compiling apparatus and a computer system for realizing the above-mentioned compiling method are further provided.

Abstract: An apparatus, method and article of manufacture tangibly embodying computer readable instructions for optimizing a Java object on a target computer program. The apparatus includes: a storage unit for storing a value of the object and management information on the object in association with each other; a code generation unit for generating, from the target computer program, optimized code and unoptimized code; a switching unit for switching from executing the target computer program using the optimized code to executing the target computer program using the unoptimized code in response to an event in which the value of the object is written while the target computer program is executed by using the optimized code; and a management unit for managing the object by accessing the management information by a non-detection write operation in which writing to the object is performed without being detected.

Abstract: The invention relates to a system and method for demarcating information related to one or more blocks in an application source code. This invention provides a means to annotate block information in the source code. It parses the application source code to generate an abstract syntax tree and instruments the source code to capture information related to the one or more blocks generated at the time of dynamic analysis of the application. The information related to the one or more blocks are stored in Hash Map and based on this information the abstract syntax tree is modified to add the information related to the one or more blocks and inserting this information in the application source code.

Abstract: Pre-compiling postdominating functions. Some embodiments may be practiced in a computing environment including a runtime compilation. For example one method includes acts for compiling functions. The method includes determining that a function of an application has been called. A control flow graph is used to determine one or more postdominance relationships between the function and one or more other functions. The one or more other functions are assigned to be pre-compiled based on the postdominance relationship.

Abstract: A method for executing non-native binaries on a host computer architecture comprises receiving the guest executable binary into a computer readable medium. The guest executable binary is executed on the host computer architecture by translating the guest executable binary into a translated executable binary. Each instruction of the translated executed binary is then executed on the host computer architecture. Signals are responded to by placing signal information on a signal queue and deferring signal handling until a safe point is reached. A computer system implementing the method is also provided.

Abstract: An image may be represented by a directed acyclic graph (DAG) including a number of nodes on paths between input parameters and output values. Intermediate operations are performed at the nodes to produce intermediate output values. One or more of the input parameters may be modified (e.g., by an animator). A determination is then made as to which intermediate output values are affected by the modified input parameters. A simplified DAG is constructed from the nodes corresponding to the intermediate output values affected by the modified input parameters. The intermediate output values that are not affected by the modified input parameters and are maintained at a constant value corresponding to a previously determined value for the intermediate output value. The simplified DAG is evaluated to determine the output resulting from the modified input parameter such that the image may be re-rendered without re-evaluating the full DAG.

Abstract: The present invention extends to methods, systems, and computer program products for binding executable code at runtime. Embodiments of the invention include late binding of specified aspects of code to improve execution performance. A runtime dynamically binds lower level code based on runtime information to optimize execution of a higher level algorithm. Aspects of a higher level algorithm having a requisite (e.g., higher) impact on execution performance can be targeted for late binding. Improved performance can be achieved with minimal runtime costs using late binding for aspects having the requisite execution performance impact.

Abstract: A method and apparatus for the manually optimizing the scheduling of code are disclosed. Accordingly, a software development tool with a graphical user interface enables manually ordering the scheduling of operations for architectures that execute multiple instructions/operations per machine cycle, such as very long instruction word (VLIW) processors. Assistance is provided at the instruction scheduling stage of VLIW compilation process to increase instruction level parallelism (ILP). The apparatus provides graphical views of assembly code and related information. An interactive, user friendly method to manipulate the code during or after scheduling is provided. The programmer can temporarily pause the automated scheduling, override decision taken by the scheduler, and then resume scheduling. The method lets the programmer interact graphically with scheduling decisions in a feedback environment.

Abstract: A state component saves a present state of a program or model. This state component can be invoked by the program or model itself, thereby making state a first-class citizen. As the state of the program evolves from the saved state, the saved state remains for reflection and recall, for example, for testing, verification, transaction processing, etc. Using a state reference token, the saved state of the program or model can be accessed by the program or model. For example, the program or model by utilizing a state component, can return itself to the saved state. After returning to the saved state, a second execution path can be introduced without requiring re-execution of the actions leading to the saved state. In another example, the state space of an executing model is saved in order to generate inputs required to exercise a program or model.

Abstract: Disclosed herein are methods and systems for creating and using pre-parsed headers. One or more header files may be scanned into tokens. These tokens may then be parsed into abstract syntax trees. The abstract syntax trees may then be serialized in a modular form into pre-parsed headers on a storage device. Based upon directives in one or more source files, the pre-parsed headers may then be deserialized into abstract syntax trees and loaded from the storage device. The loaded abstract syntax trees may then be used in the compilation of the source files.

Abstract: The present invention extends to methods, systems, and computer program products for compile time interpretation of markup codes. Embodiments of the invention can be used to specify custom behaviors to be taken in response to any of a number of ways that markup codes (e.g., XML data) can be constructed and in response to any number of ways that markup codes can be accessed. At compile time, the construction of objects and/or the modes of access for objects using mark up codes are known. As such, the compiler, type-system and development environment can use a known set of custom behaviors to regulate or give feedback on what constructions or modes of access are allowed, and what their characteristics are.

Abstract: Example embodiments relate to storage devices, computing devices, and machine-readable storage media that optimize storage device operating parameters for desktop and notebook computing devices. Example embodiments allow for optimization of operating parameters of a storage device for one of a desktop computing device and a notebook computing devices based on provision of a command to the storage device. In example embodiments, upon receipt of such a command, the storage device may reconfigure its operating parameters to be optimized for the particular type of system.

Abstract: Computer code from an application program comprising a plurality of modules that each comprise a separately loadable file is code cached in a shared and persistent caching system. A shared code caching engine receives native code comprising at least a portion of a single module of the application program, and stores runtime data corresponding to the native code in a cache data file in the non-volatile memory. The engine then converts cache data file into a code cache file and enables the code cache file to be pre-loaded as a runtime code cache. These steps are repeated to store a plurality of separate code cache files at different locations in non-volatile memory.

Abstract: A method for optimizing the object code of a program is disclosed. A compiler generates, respectively, first and second object code segments for first and second source code segments of the program. If the two object code segments are determined to be identical, the compiler generates first and second debugging information entries in a compilation unit of the program and both entries include information for locating the first object code segment. The compiler inserts two entries into a call table in the compilation unit, each entry including information for locating a respective call site that invokes a respective source code segment within a call stack of the program and information for locating a respective debug information entry. The call table is used for associating an operation within the first object code segment with one of the first and second source code segments at runtime.

Abstract: A host computer which generates a print job subjected to printing by a printer stores a drawing command output from an application in a spool file via a graphic engine. A spool system, the graphic engine, and a job chasing function processing unit execute a chasing data generation process by using the drawing command. The spool system, the graphic engine, and a graphics control unit execute a print data generation process by using the same drawing command. At this time, the drawing command is read out and output so as to successively execute the chasing data generation process and print data generation process. With this configuration, there are provided a method of protecting leakage of information by which the contents of information can be reliably chased without requiring either a special application or a device having a special function and posing any restriction on the read or output path, and an information processing apparatus and driver program which implement the method.

Abstract: A technique for reducing non-local access, in dynamically generated code that resides in a code buffer of a non-uniform memory access computer system including multiple nodes, for improving overall performance of dynamic optimization systems. In one example embodiment, this is accomplished by partitioning the code buffer into multiple smaller code buffers and assigning each of the multiple smaller code buffers to one of the multiple nodes. Statically determining which methods in the generated code are executed by a thread and then to place those methods in associated one of the multiple smaller code buffers to reduce memory latencies introduced by non-local accesses.

Abstract: A method of compiling code includes ordering instructions that protect and release critical sections in the code to improve parallel execution of the code according to an intrinsic order of the critical sections. According to one embodiment, the intrinsic order of the critical sections in the code is determined from data dependence and control dependence of instructions in the critical sections, and additional dependencies are generated to enforce the intrinsic order of the critical sections. Other embodiments are described and claimed.

Abstract: According to some embodiments, a token synchronization gateway may be recognized in a graph-based business process model, such as a business process modeling notation model. A number of upstream artifacts located upstream from the token synchronization gateway may then be identified in the business process modeling notation model. In addition, a final artifact may be identified directly in front of the token synchronization gateway. The token synchronization gateway may then be compiled into code that will be executed at runtime to perform a synchronization process. The synchronization process may, for example, include handling tokens T1 through Tn to synchronize the upstream artifacts, with each token being associated with one of the n upstream artifacts.

Abstract: One embodiment of a method for eliminating redundant operations establishing common properties includes identifying a first virtual register storing a first value having a common property. The method may assign the first virtual register to use a real register. The method may further identify a second virtual register storing a second value also having the common property. The method may assign the second virtual register to use the same real register after the first value is no longer live. As a result of assigning the second virtual register to the first real register, the method may eliminate an operation configured to establish the common property for the second virtual register since this operation is redundant and is no longer needed.

Abstract: An execution time estimation device includes a program partitioning section that extracts partial programs partitioned by a conditional branch instruction or a function call instruction from a target program, a partial program execution time estimation calculating section that calculates the execution time of each of the partial programs to associate the leading instruction and the end instruction of each of the partial programs, and the calculated execution time with one another, a branch history information generating section that generates a branch history bit sequence which is a sequence of the true-false of the conditional branch instruction of when the target program is executed, an execution trace reproducing section that generates the execution sequences of the partial programs based on the branch history bit sequence, and an execution time estimation calculating section that adds the execution time of the partial programs based on the execution sequences of the partial programs.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: The specification of a string within source code written in a programming language is received. The source code is processed for ultimate execution of a computer program encompassing the source code, by at least performing the following. It is determined whether the string specified is a short string or a long string. The string is processed in accordance with a first manner where the string is a short string. The string is processed in accordance with a second manner where the string is a long string.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: Reactive programming is facilitated. Reactive expressions can be generated automatically from non-reactive expressions or in other words standard expressions. Additionally or alternatively, reactive expressions can be optimized in a number of different ways to minimize computational work.

Abstract: One embodiment of the present invention sets forth a technique for extracting a memory address offset from a 64-bit type-conversion expression included in high-level source code of a computer program. The technique involves receiving the 64-bit type-conversion expression, where the 64-bit type-conversion expression includes one or more 32-bit expressions, determining a range for each of the one or more 32-bit expressions, calculating a total range by summing the ranges of the 32-bit expressions, determining that the total range is a subset of a range for a 32-bit unsigned integer, calculating the memory address offset based on the ranges for the one or more 32-bit expressions, and generating at least one assembly-level instruction that references the memory address offset.

Abstract: A degree of detail calculation required for calculations to process computer graphics data is determined based on input parameters that are varying in certain dimensions. During a detail analysis of a shader, a directed graph is built in such a way that each connection between nodes indicates a dependency among inputs and outputs of calculations and/or input parameters. For each input parameter, variability information about the input parameter is obtained. A lattice or a table representing dimensional variability is used to determine a variability value for each calculation for given input parameters and dependency relationships among other calculations. After a variability value has been determined for each calculation, calculations are grouped into several groups and executed once per the variability value.

Abstract: Paralleling processing system and method. When clusters are formed based on strongly connected components, a single cluster (fat cluster) having at least a predetermined number of blocks, or an expected processing time exceeding a predetermined threshold, is formed. The fat cluster is subjected to an unrolling process to make multiple copies of the processing of the fat cluster and to assign the copies to individual processors. Processing of the fat cluster is executed by the multiple processor devices in a pipelined manner. If a fat cluster to be iteratively executed cannot be executed in the pipelined manner because a processing result of an nth iteration of the fat cluster depends on a processing result of a preceding iteration of the fat cluster an input value needed for execution of the fat cluster is generated based on a certain prediction, and the fat cluster is speculatively executed.

Abstract: Various embodiments herein include one or more of systems, methods, software, and/or data structures to implement a multi-way branch statement in a computer programming language. The multi-way branch statement may include a plurality of case labels each having a non-primitive data type (e.g., strings) and being associated with a block of code to be executed dependent upon a control variable that also has a non-primitive data type. The implementation may include encoding the case labels for the multi-way branch statement as a binary decision diagram (BDD), such as a zero-suppressed binary decision diagram (ZDD), wherein the control variable for the multi-way branch statement may be compared with the case labels by stepping through the BDD. The BDD may include identifiers that provide information regarding which of the case labels is matched by the control variable, such that an appropriate code block may be executed.