Abstract: The present invention provides a method to optimize object code files produced by a compiler for several different types of target processors. The compiler divides the source code to be compiled into several functional modules. Given a specified set of target processors, each functional module is compiled resulting in a target object version for each target processor. Then, for each functional module, a merging process is performed wherein identical target object versions or target object versions with similar contents are merged by deleting the identical or similar versions. After this merging process, a composite object code file is formed containing all of the non-deleted target object versions of the function modules.

Abstract: A method and system for evaluating a system are described. A parameter space comprising one or more parameters corresponding to the system and/or an application executed on the system is defined. Additionally, one or more search functions for selecting a parameter from the parameter space to evaluate a desired characteristic of the system are determined. Further, at least one parameter from the parameter space is selected using the one or more search functions and the application is executed using the selected parameter. Subsequently, the execution of the application is monitored and metrics associated with the application are recorded. The method further includes iteratively selecting another parameter from the parameter space based on the recorded metrics and executing the application using the selected another parameter.

Abstract: Nested virtual machines cooperate with one another to improve system performance. In particular, an outer virtual machine performs tasks on behalf of an inner virtual machine to improve system performance. One such task includes translation of instructions for the inner virtual machine.

Abstract: In one embodiment, a method comprises generating a first executable program optimized for an executable system based on compiling a program relative to an initial set of independent optimization metrics; determining first performance metrics based on the executable system executing the first executable program; adjusting the initial set of independent optimization metrics based on the first performance metrics to generate a second set of independent optimization metrics; and generating a second executable program, based on compiling the program relative to the second set of independent optimization metrics, for improved execution of the program in the executable system.

Abstract: A mechanism for efficient software cache accessing with handle reuse is provided. The mechanism groups references in source code into a reference stream with the reference stream having a size equal to or less than a size of a software cache line. The source code is transformed into optimized code by modifying the source code to include code for performing at most two cache lookup operations for the reference stream to obtain two cache line handles. Moreover, the transformation involves inserting code to resolve references in the reference stream based on the two cache line handles. The optimized code may be output for generation of executable code.

Abstract: A method, system, and article of manufacture are disclosed for transforming a definition of a process for delivering a service. This service process definition is comprised of computer readable code. The method comprises the steps of expressing a given set of assumptions in a computer readable code; and transforming said process definition by using a processing unit to apply said assumptions to said process definition to change the configuration of the process definition. The process definition may be transformed by using factors relating to the specific context in or for which the process definition is executed. Also, the process definition may be transformed by identifying, in a flow diagram for the service process definition, flows to which the assumptions apply, and applying program rewriting techniques to those identified flows.

Abstract: According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The portion of code is optimized in the sense that the number of instructions executed will be smaller. However, since the applied optimization is speculative, the optimized version can be incorrect and some mechanism to recover from that situation is required. Thus, the quality of the produced code will be measured by taking into account both the final length of the code as well as the frequency of misspeculation.

Abstract: A compiler receives source code for a program and determines that the code includes a declaration expression and an initialization expression in an assignment context. The declaration expression introduces a variable and specifies part of a parameterized type for the variable but not another part of the parameterized type. A parameterized type may include a ground type part and one or more type arguments; in a declaration expression, the specified part of the parameterized type may include a ground type and the unspecified part may include one or more of the type arguments. The initialization expression specifies an initial value for the variable, where the value has a parameterized type. The assignment context associates the declared variable with the initial value. The compiler infers the type for the variable based at least on the part specified in the declaration expression and on the type specified by the initialization expression.

Abstract: A program is executed with a first programmable device (10). Device operating points such as power supply voltage and/or clock frequency are adapted dependent on the states reached by the device during execution. Operation of programs that may have been sold after the device has been supplied to users is optimized by executing the computer program on each of a plurality of programmable devices (10) like the first programmable device, and collecting statistical data associated with the execution states encountered during execution by the plurality of programmable devices (10). Each of the plurality of programmable devices (10) collects its own statistical data and uploads the collected information to a common profiling apparatus (14). The profiling apparatus assigns device operating points to respective ones of the execution states, using an optimization that depends on the combined statistical data from the plurality of programmable devices (10).

Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between the states, wherein the states in the automaton include a special purpose state that corresponds to a special purpose hardware element. The compiler converts the automaton into a netlist, and places and routes the netlist to provide machine code for configuring a target device.

Abstract: A method of detecting portions of code of a computer program that protect resources of a computer system unnecessarily can include identifying threads and synchronization objects that are used by a computer program during execution, determining the number of threads that have accessed each resource while it has been consistently protected by a particular synchronization object, and indicating whether the resource is suited for protection according to the number of threads that have accessed the resource.

Abstract: A method includes generating a first executable program module based on source code modules and collecting profile information for the source code modules by executing the first executable program module. The profile information includes information pertaining to invocation of procedures in the first executable program module. The method further includes determining module grouping information for the source code modules based on procedure invocation patterns in the profile information and according to one or more inter-procedural optimization (IPO) heuristics. The method includes performing IPO based on the module grouping information to generate object code modules and generating a second executable program module based on the plurality of object code modules.

Abstract: Deferred constant pool generation is disclosed. Optimization processing is performed with respect to an intermediate representation of a source code. The optimized intermediate representation is used to generate a constant pool. In some embodiments, the source code comprises JavaScript, which is used to generate a low level virtual machine (LLVM) or other intermediate representation (IR), which intermediate representation is optimized prior to a constant pool being generated.

Abstract: Systems and methods for using memory usage to pinpoint sub-optimal code for gaming systems are provided herein. Memory usage characteristics, such as latency, cache misses, load-hit-store, memory address misuse, and wasted cache bandwidth are presented, preferably in a graphical format, to provide the developer with information for optimizing source code. A trace analysis is performed on source code undergoing optimization. Relevant data is extracted from the trace analysis, sorted as necessary, and presented to the user. The user may be presented with multiple results sorting mechanisms as well as ways to change the presentation of the results.

Abstract: A method, system, and program product for removing exception classes that match a pattern is disclosed. Exception classes are searched for those of the exception classes that match that pattern. The parent classes of matched exception classes are refactored to accept an exception type argument. Code that throws the matched exceptions is rewritten by replacing the exception class with the parent class and adding a corresponding exception type. Code that catches the thrown exceptions is rewritten by changing a catch clause to catch a parent exception class and inserting a case statement for the exception type in that catch clause. The matched exception classes are removed.

Abstract: A software transactional memory system is described which utilizes decomposed software transactional memory instructions as well as runtime optimizations to achieve efficient performance. The decomposed instructions allow a compiler with knowledge of the instruction semantics to perform optimizations which would be unavailable on traditional software transactional memory systems. Additionally, high-level software transactional memory optimizations are performed such as code movement around procedure calls, addition of operations to provide strong atomicity, removal of unnecessary read-to-update upgrades, and removal of operations for newly-allocated objects. During execution, multi-use header words for objects are extended to provide for per-object housekeeping, as well as fast snapshots which illustrate changes to objects. Additionally, entries to software transactional memory logs are filtered using an associative table during execution, preventing needless writes to the logs.

Abstract: In the various aspects, virtualization techniques may be used to reduce the amount of power consumed by execution of applications by power-optimizing the code prior to execution. A dynamic binary translator operating at the machine layer may use a power consumption model to identify code segments that can benefit from optimization and to perform an instruction-sequence to instruction-sequence translation of object code to generate power-optimized object code. Execution hardware may be instrumented with additional circuitry to measure the power consumption characteristics of executing code. The power consumption models may be updated and object code may be regenerated based on the measured the power consumption characteristics of previously executed code. In an aspect, power optimization may be accomplished when the computing device is connected to a battery charger.

Abstract: The present invention relates to an XML application framework (XAF). XAF applications are data driven such that all operations with the computer system are data focused. In addition, the components used in the XAF application are instantiated and connected according to how the data is displayed and what type of data is used. Applications within XAF comprise a user interface (UI) connector, an action module, and a data connector. UI connectors receive UI events and connect the UI event to an action module. The action module generates a standard format action from the UI event and sends it to the data connector. The data connector translates the standard format action into a data-specific action that changes data in a data store. A data connector then sends a standard format data representation corresponding to the changed data back to the UI connector to provide the changed data to the UI.

Abstract: Processes in a message passing system may be launched when messages having data patterns match a function on a receiving process. The function may be identified by an execution pointer within the process. When the match occurs, the process may be added to a runnable queue, and in some embodiments, may be raised to the top of a runnable queue. When a match does not occur, the process may remain in a blocked or non-executing state. In some embodiments, a blocked process may be placed in an idle queue and may not be executed until a process scheduler determines that a message has been received that fulfills a function waiting for input. When the message fulfills the function, the process may be moved to a runnable queue.

Abstract: Interface optimization is provided using a closed system in which all the individual software components in the system are known to the compiler at a single point in time. This knowledge enables significant opportunities to optimize the implementation of interfaces on a set of implemented objects. When code is compiled, because the compiler knows the full list of interfaces and the objects which implement the interfaces, it can improve execution and working set (i.e., recently referenced pages in a program's virtual address space) when implementing the interfaces on objects. This improvement may be realized by reducing the size of interface lookup tables which map each interface to the object types which implement that particular interface.

Abstract: A technique for optimizing a program by reusing an execution result of a subclass test function. It includes a reusability determining unit to determine reusability of code of a subclass test function based on whether access to a global memory includes only access for reading out type information specified in a function call, a profiling unit configured to store an execution result of code determined to be reusable and specified information in a storage device in association with actually accessed type information, a reuse processing unit configured to reuse, in response to detection of a function call for calling the code determined to be reusable, the execution result on condition that the pieces of specified information specified in the function calls match, and a monitoring unit configured to monitor the type information associated with the execution result and prohibit reuse of the execution result if the type information is changed.

Abstract: An event execution system comprises an ordering component that receives multiple events and dynamically organizes the multiple events based at least in part upon a predefined organization of devices affected by the multiple events. The system can additionally include an execution component that executes the multiple events with respect to the devices according to the organization of the multiple events.

Abstract: A technique for compiling and running high-level program on heterogeneous computers may include partitioning a program code into two or more logical units, and compiling each of the logical units into one or more executable entities. At least some of the logical units are compiled into two or more executable entities, the two or more executable entities being different compilations of the same logical unit. The two or more executable entities are compatible to run on respective two or more platforms that have different architecture.

Abstract: A technique for optimizing a program by reusing an execution result of a subclass test function. It includes a reusability determining unit to determine reusability of code of a subclass test function based on whether access to a global memory includes only access for reading out type information specified in a function call, a profiling unit configured to store an execution result of code determined to be reusable and specified information in a storage device in association with actually accessed type information, a reuse processing unit configured to reuse, in response to detection of a function call for calling the code determined to be reusable, the execution result on condition that the pieces of specified information specified in the function calls match, and a monitoring unit configured to monitor the type information associated with the execution result and prohibit reuse of the execution result if the type information is changed.

Abstract: In one embodiment, the present invention includes a software-controlled method of forming instruction strands. The software may include instructions to obtain code of a superblock including a plurality of basic blocks, build a dependency directed acyclic graph (DAG) for the code, sort nodes coupled by edges of the dependency DAG into a topological order, form strands from the nodes based on hardware constraints, rule constraints, and scheduling constraints, and generate executable code for the strands and store the executable code in a storage. Other embodiments are described and claimed.

Abstract: A computer-implemented method for memory access monitoring, implemented by a managed runtime environment computer system including a controller that monitors application behavior and determines actions to be taken to change a behavior of an application, and a runtime, dynamic compiler that analyzes the application and generates code sequences to access a memory access monitoring (MAM) mechanism, includes determining monitor information of a plurality of fields of a memory block to drive an optimization of the application.

Abstract: Methods, systems, and apparatus, including computer program products, for inter-procedural optimization, are disclosed. In one aspect, a first executable program module is generated based on a plurality of source code modules. Profile information is collected for the plurality of source code modules by executing the first executable program module. Inter-procedural analysis for the plurality of source code modules is performed during execution of the first executable program module. The inter-procedural analysis is based on the collected profile information. IPO is performed based on the results from the inter-procedural analysis to generate a plurality of object code modules. A second executable program module is generated based on the plurality of object code modules.

Abstract: A mechanism is provided for path-sensitive analysis for reducing rollback overheads. The mechanism receives, in a compiler, program code to be compiled to form compiled code. The mechanism divides the code into basic blocks. The mechanism then determines a restore register set for each of the one or more basic blocks to form one or more restore register sets. The mechanism then stores the one or more register sets such that responsive to a rollback during execution of the compiled code. A rollback routine identifies a restore register set from the one or more restore register sets and restores registers identified in the identified restore register set.

Abstract: Mechanism that employs code cloning and specialized code execution for barriers to minimize runtime overhead. This is facilitated by duplicating code and inserting specializations of the barriers in the code copies. The mechanism is effective for garbage collection when the garbage collection executes through different phases, and the barrier behavior and overheads depend on these phases. The duplicated and specialized code enables the program to run efficiently by reducing the dynamic count of a phase check when the phase is well-known and phase checks can be avoided.

Abstract: Concepts and technologies are described herein for determining memory safety of floating-point computations. The concepts and technologies described herein analyze code to determine if any floating-point computations exist in the code, and if so, if the floating-point computations are memory safe. The analysis can include identifying floating-point instructions and conditional statements in the code. The code can be symbolically executed, and behavior of the floating-point instructions and the conditional statements can be monitored to determine if a floating point calculation is ever involved in computation of any memory address during the execution of the code.

Abstract: A method of aiding report construction based on inference of implicit application level relationships is provided herein. The method may include the following steps: analyzing a model of a software application to yield data elements associated with base objects of the software application and relationships between the data elements; generating a list of reportable objects comprising the base objects and objects associated with the data elements and their relationships; ordering the reportable objects based on at least one of: content and usage of the reportable objects, to yield an ordered list; and presenting the ordered list in a form usable for building a report on the software application, wherein at least one of: the analyzing, the generating, the ordering, and the presenting, is carried out by at least one processor.

Abstract: Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference.

Abstract: A partition-based method for diagnosing memory leaks in Java systems, comprising dividing heap memory of a Java virtual machine into a plurality of partitions based on a partition plan, wherein each partition has at least one partition owner; monitoring the status of the respective partitions to determine whether there is a partition in which the memory space is exhausted; and if there is a partition in which the memory space is exhausted, determining that the memory leak may occur in the partition and analyzing the partition to obtain leaked objects and objects related to the leaked objects. The present invention also provides a partition-based apparatus for diagnosing memory leak in Java systems.

Abstract: Systems and methods that add specifications to procedures in a garbage collector for indicating what each procedure does. Such annotations can be added in the source code, to indicate what the source code is to do when it runs—hence enabling an automatic verification of the garbage collector by a verification component. The specification can be presented as a logical formula that can be readily processed by a theorem prover, which is associated with the verification component. Such logical formulas can further employ regions to specify correctness of the garbage collector.

Abstract: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.

Abstract: A compiler may optimize source code and any referenced libraries to execute on a plurality of different processor architecture implementations. For example, if a compute node has three different types of processors with three different architecture implementations, the compiler may compile the source code and generate three versions of object code where each version is optimized for one of the three different processor types. After compiling the source code, the resultant executable code may contain the necessary information for selecting between the three versions. For example, when a program loader assigns the executable code to the processor, the system determines the processor's type and ensures only the optimized version that corresponds to that type is executed. Thus, the operating system is free to assign the executable code to any processor based on, for example, the current status of the processor (i.e.

Abstract: A method for performing a neighbor-flipping transformation is provided. In one embodiment, a graph analysis program for computing a function relating to nodes in a directed graph is obtained and analyzed for neighborhood iterating operations, in which a function is computed over sets of nodes in the graph. For any detected neighborhood iterating operation, the method transforms the iterating operation by reversing the neighbor node relationship between the nodes in the operation. The transformed operation computes the same value for the function as the operation prior to transformation. The method alters the neighbor node relationship automatically, so that a user does not have to recode the graph analysis program. In some cases, the method includes construction of edges in the reverse direction while retaining the original edges in addition to performing the transformation.

Abstract: A computer-implemented technique for analysis of software, is carried out using a semantic intensity calculation module, a coupling calculation module, and a software decomposition module. Software elements are identified in a computer program code, and respective roles of the software elements established. With the semantic intensity calculation module respective semantic intensity metrics are calculated for the software elements according to the roles thereof. With the coupling calculation module semantic intensity metrics are calculated to determine coupling factors between different software elements. With the software decomposition module the software elements are organized into distinct software components according to the coupling factors therebetween. Then, an optimized computer program code is generated from the software components.

Abstract: Systems and methods are provided for handling database deadlocks induced by database-centric applications (DCAs). SQL statements and transactions associated with the DCAs are analyzed and parsed to generate Petri net models. A supervisory modeler generates augmented Petri net models based on the Petri net models, which are used in generating supervisory control. The supervisory control is used in handling database deadlocks.

Abstract: A dynamic race detection system is provided that detects race conditions in code that executes concurrently in a computer system. The dynamic race detection system uses a modified software transactional memory (STM) system to detect race conditions. A compiler converts portions of the code that are not configured to operate with the STM system into pseudo STM code that operates with the STM system. The dynamic race detection system detects race conditions in response to either a pseudo STM transaction in the pseudo STM code failing to validate when executed or an actual STM transaction failing to validate when executed because of conflict with a concurrent pseudo STM transaction.

Abstract: A method apparatus and computer program product is disclosed for adding instrumentation to a body of code to enable generation of code coverage data for said body of code in which used instrumentation code is arranged to be optimized out by a compiler.

Abstract: A method for use in indicating an execution of application source code. Application object code is generated based on application source code. The application object code includes a plurality of object code portions of interest corresponding to a plurality of source code portions of interest within the application source code. For each execution of an object code portion of interest, an execution event is associated with the corresponding source code portion of interest. Source code portions of interest may be assigned an execution frequency based on a quantity of associated execution events.

Abstract: One or more embodiments provide a load balancing solution for improving the runtime performance of parallel HDL simulators. During compilation each process is analyzed to determine a simulation cost based on complexity of the HDL processes. During simulation, processes to be executed in the same simulation cycle are scheduled using the simulation costs computed at compile-time in order to reduce the delay incurred during simulation.

Abstract: A virtual machine executive (VME) system operating on a target platform that includes a virtual machine monitor (VMM) and a dynamic compiler, in particular, a trace compiler (TC). System embodiments include a virtual machine monitor configured to record a trace corresponding to a selected cycle, and configured to transform the trace into a representation of a trace tree; and a trace compiler cooperating with the virtual machine monitor to compile the representation of the trace tree into a compiled code segment of native machine code executable on the target platform, in which the trace is a linear instruction sequence traversing at least a portion of a method, a loop, or a branching node.

Abstract: A method, system, and article of manufacture are disclosed for transforming a definition of a process for delivering a service on a specified computing device. This service process definition is comprised of computer readable code. The method comprises the steps of expressing a given set of assumptions in a computer readable code; and transforming the definition by using a processing unit to apply the assumptions to the definition of the process to change the way in which the process operates. The definition of the process may be transformed by using factors relating to the specific context in or for which the definition is executed. Also, the definition may be transformed by identifying, in a flow diagram for the process, flows to which the assumptions apply, and applying program rewriting techniques to those identified flows.

Abstract: Methods and apparatus for preserving precise exceptions in code reordering by using control speculation are disclosed. A disclosed system uses a control speculation module to reorder instructions within an application program and preserve precise exceptions. Instructions, excepting and non-excepting, can be reordered by the control speculation module if the instructions meet certain conditions. When an excepting instruction is reordered, a check instruction is inserted into the program execution path and a recovery block is generated. The check instruction determines if the reordered excepting instruction actually needs to generate an exception. The recovery block contains instructions to revert the effects of code reordering. If the check instruction detects the need for an exception, the recovery block is executed to restore the architectural state of the processor and the exception is handled.

Abstract: An encryption method and device employing a modified low-resource AES algorithm. The algorithm in one embodiment has a 128-bit key and a 16-bit data type, along with optimization functions including function inlining, memory move reduction via multiple transformations on a given state during a given iteration of a main loop of the algorithm, pointer-based accessing of the state from a transformation function, and a global key schedule. Another embodiment of the invention is a low-power secure communication device comprising a ZigBee-compliant transceiver having a maximum over-the-air data rate of 250 kbps, and a 16-bit RISC encryption processor configured to implement an AES algorithm adapted to encrypt data at a faster rate than 250 kbps. The AES algorithm only requires about 5000 bytes of ROM and about 250 bytes of RAM.

Abstract: An efficient, logical and expressive type system supports the combination of refinement types and type membership expressions, as well as a top type that encompasses all valid values as members. A bidirectional type checking algorithm is provided for the type system including synthesis and checking steps to statically verify types of code based on the type system.

Abstract: Immutable structures are employed to effect immutable parsing. In particular, an immutable parsing configuration, comprising a stack and lookahead buffer, is utilized by a parser to perform lexical and syntactical analysis of an input stream and optionally output an immutable parse tree or the like. Performance with respect to the immutable structures can be optimized utilizing sharing and lazy computation. In turn, immutability benefits are afforded with respect to parsing including safe sharing amongst services and/or across multiple threads as well as history preservation, among other things.

Abstract: Prefetching irregular memory references into a software controlled cache is provided. A compiler analyzes source code to identify at least one of a plurality of loops that contain an irregular memory reference. The compiler determines if the irregular memory reference within the at least one loop is a candidate for optimization. Responsive to an indication that the irregular memory reference may be optimized, the compiler determines if the irregular memory reference is valid for prefetching. Responsive to an indication that the irregular memory reference is valid for prefetching, a store statement for an address of the irregular memory reference is inserted into the at least one loop. A runtime library call is inserted into a prefetch runtime library for the irregular memory reference. Data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked.