Abstract: An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth.

Abstract: A thyristor includes a base region, a pair of first doping regions, at least one second doping region, at least one third doping region, and a pair of metal layers. The first doping regions are formed in two opposite sides of the base region and touch the base region. The second doping region is formed between the base region and one of the first doping regions. The second doping region touches the base region and the first doping region. The third doping region is formed in one of the first doping regions and touches the first doping region. The type of the first doping region is different from the types of the second doping region, the third doping region, and the base region. The metal layers touch the first doping regions respectively. The first doping regions and the third doping region are located between the metal layers.

Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.

Abstract: An SCR apparatus includes an SCR structure and a first N injection region. The SCR structure includes a P+ injection region, a P well, an N well and a first N+ injection region, the first N injection region is located under an anode terminal of the P+ injection region of the SCR structure. A method for adjusting a sustaining voltage therefor is provided as well.

Abstract: In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (“CNT”) material above the substrate, wherein the CNT material comprises a single CNT. Numerous other aspects are provided.

Abstract: An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n? epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes.

Abstract: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.

Abstract: Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.

Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.

Abstract: A semiconductor device including an oxide semiconductor can have stable electric characteristics and high reliability. A transistor in which an oxide semiconductor layer containing indium, titanium, and zinc is used as a channel formation region and a semiconductor device including the transistor are provided. As a buffer layer in contact with the oxide semiconductor layer, a metal oxide layer containing an oxide of one or more elements selected from titanium, aluminum, gallium, zirconium, hafnium, and a rare earth element can be used.

Abstract: An SCR includes a first doped region of a first type having a first doping concentration. A first well of the first type and a first well of a second type are disposed in upper areas of the first doped region of the first type such that the first well of the second type is laterally spaced from the first well of the first type by a non-zero distance. A second doped region of the first type has a second doping concentration that is greater than the first doping concentration and is disposed in the first well of the second type to form an anode of the SCR. A first doped region of the second type is disposed in the first well of the first type and forms a cathode of the SCR.

Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.

Abstract: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.

Abstract: A driving device that drives a light emitting thyristor array includes: a first driving circuit operated by a second power source; a scanning circuit including plural stages of scanning thyristors and sequentially scanning the plural stages of light emitting thyristors, a second driving circuit operated by a second power source, generating first and second clock signals for driving the scanning circuit, and outputting the first and second clock signals from first and second clock terminals, respectively, a terminal of an odd numbered stage scanning thyristor is commonly connected to the first clock terminal, another terminal of an even numbered stage scanning thyristor is commonly connected to the second clock terminal, and a control terminal of a first stage scanning thyristor is connected to the second clock terminal via a first resistor.

Abstract: The semiconductor device includes a plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency. Any of the first flat plates is disposed above the first connecting wire, and any other of the first flat plates is disposed above the second connecting wire.

Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

Abstract: Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.

Abstract: A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.

Abstract: An electrostatic protection circuit in a semiconductor device includes a first first-conductivity type well extending in a first direction over a semiconductor substrate, a second first-conductivity type well extending in a second direction over the semiconductor substrate and perpendicular to the first direction with one end coupled to a first long side of the first first-conductivity type well, and a second-conductivity type well formed around the first first-conductivity type well and the second first-conductivity type well. It also includes a first high-concentration second-conductivity type region extending in the second direction on a surface of the second first-conductivity type well and a first high-concentration first-conductivity type region extending in the second direction on a surface of the second-conductivity type well while facing the first high-concentration second-conductivity type region.

Abstract: A structure for starting a semiconductor component including a porous silicon layer in the upper surface of a semiconductor substrate. This porous silicon layer is contacted, on its upper surface side, by a metallization and, on its lower surface side, by a heavily-doped semiconductor region.

Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.

Abstract: According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.

Abstract: The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.

Abstract: A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions.

Abstract: An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode.

Abstract: Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described.

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.

Abstract: A thyristor includes a base region, a pair of first doping regions, at least one second doping region, at least one third doping region, and a pair of metal layers. The first doping regions are formed in two opposite sides of the base region and touch the base region. The second doping region is formed between the base region and one of the first doping regions. The second doping region touches the base region and the first doping region. The third doping region is formed in one of the first doping regions and touches the first doping region. The type of the first doping region is different from the types of the second doping region, the third doping region, and the base region. The metal layers touch the first doping regions respectively. The first doping regions and the third doping region are located between the metal layers.

Abstract: According to one embodiment, a die package is provided comprising a first die structure with a first plurality of switching elements wherein controlled current input terminals of the first plurality of switching elements are electrically coupled by a common contact region and wherein controlled current output terminals of the first plurality of switching elements are insulated from each other; a second die structure with a second plurality of switching elements wherein controlled current output terminals of the second plurality of switching elements are coupled by a common contact region and wherein controlled current input terminals of the second plurality of switching elements are insulated from each other; and wherein, for each of the first plurality of switching elements, the output terminal of the switching element is coupled with the input terminal of at least one switching element of the second plurality of switching elements.

Abstract: A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.

Abstract: A latchup silicon controlled rectifier (SCR) includes a p+ region and an n+ region located in a p-well of the latchup SCR; and a p+ region and an n+ region located in a n-well of the latchup SCR, wherein the latchup SCR further comprises one of embedded silicon germanium (eSiGe) in the p+ region in the n-well of the latchup SCR and silicon carbide (SiC) in the n+ region in the p-well of the latchup SCR.

Abstract: A bi-directional triode thyristor (TRIAC) device for high voltage electrostatic discharge (ESD) protection may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates. The portion of the N-type well region that is interposed between the two P-type well regions may comprise one or more P-type portions, such as a P+ doped plate or a P-type implant.

Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.

Abstract: A semiconductor device includes a semiconductor body including a first surface having a normal direction defining a vertical direction, a first n-type semiconductor region arranged below the first surface and having a first maximum doping concentration and a second n-type semiconductor region arranged below the first n-type semiconductor region and including, in a vertical cross-section, two spaced apart first n-type portions each adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and having a first minimum distance to the first surface, and a second n-type portion adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and a second minimum distance to the first surface which is larger than the first minimum distance. A p-type second semiconductor layer forms a pn-junction with the second n-type portion.

Abstract: A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component. For this purpose the trench structure has a base (7) and a wall area (8) and is filled with a material (9) with a relatively high dielectric constant (?r). The base area (7) of the trench structure (5) is provided with a heavily doped semiconductor material (11) of the same conductivity type as the lightly doped semiconductor body areas (17), and/or having a metallically conductive material (12).

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Abstract: A semiconductor apparatus includes a semiconductor chip, a lead frame that has a first surface having the semiconductor chip mounted thereover and a second surface opposite to the first surface, a bonding wire that couples the semiconductor chip and the lead frame, and a high dielectric constant layer that is disposed over a surface of the lead frame opposite to a surface having the semiconductor chip mounted thereover and that has a relative permittivity of 5 or more. The lead frame includes a source electrode lead coupled to the source of a semiconductor device formed over the semiconductor chip and a source-wire junction at which the source electrode lead and the bonding wire are coupled together. The high dielectric layer is disposed in a region including at least a position corresponding to the source-wire junction over the second surface of the lead frame.

Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.

Abstract: This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

Abstract: Device structures, design structures, and fabrication methods for a silicon controlled rectifier. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. A doped region of a second conductivity type is formed in the well. A cathode of a silicon controlled rectifier and a cathode of a diode are formed in the device region. The silicon controlled rectifier comprises a first portion of the well and an anode comprised of a first portion of the doped region. The diode comprises a second portion of the well and an anode comprised of a second portion of the doped region.

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Abstract: An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.

Abstract: The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.

Abstract: A power amplifier includes: an input matching circuit including an inductor, the input matching circuit receiving an input signal and matching input impedances with each other; an amplifier amplifying the input signal that is passed through the input matching circuit; and a test circuit, wherein the test circuit includes: a capacitor connected to the inductor in the input matching circuit through first test switch; a negative resistance transistor provided between the inductor and first voltage source terminal with second test switch being interposed between the inductor and the negative resistance transistor; and a current source transistor provided between second voltage source terminal and the inductor, wherein, in testing, first and second test switches and the current source transistor are turned on to cause the inductor and the test circuit to form a oscillator and, in normal operation, first and second test switches and the current source transistor are turned off.

Abstract: A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions.

Abstract: An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device coupled in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal coupled to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, coupled between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal coupled to the control terminal; and a Zener diode, coupled between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.

Abstract: A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: A semiconductor device having high-aspect-ratio PN-junctions is provided. The semiconductor device includes a conducting layer. The semiconductor device further includes a plurality of first doped regions formed over the conducting layer. The sidewalls of the doped regions are doped to form PN-junctions. The semiconductor device also includes a plurality of second doped regions over the first doped regions.

Abstract: A method of forming an IC device including a latchup silicon controlled rectifier (SCR) includes forming a mask on a top surface of a substrate, wherein the mask covers a first portion of the substrate and exposes a second portion of the substrate that is located in one of an n-well and a p-well on the substrate; etching the exposed second portion of the substrate to form an etched area; forming a stress engineered junction of the latchup SCR by selective epitaxial deposition in the etched area; and removing the mask.