Abstract: An edge-emitting thyristor having an improved external luminous efficiency and a self-scanning light-emitting device array comprising the edge-emitting thyristor are disclosed. To improve the external luminous efficiency of an edge-emitting light-emitting thyristor, a structure where the current injected from an electrode concentrates on and near the edge of the light-emitting thyristor is adopted.

Abstract: A thyristor-based semiconductor device has a control port formed in a trench having a height-to-width aspect ratio that can be prohibitive to filling a bottom portion of the trench with an insulative material. According to an example embodiment of the present invention, a trench is formed in the substrate adjacent to a thyristor region, and a control port is formed near a bottom of the trench. An upper portion of the trench is then filled, thereby covering the control port. The control port is adapted to reduce the aspect ratio of a remaining portion of the trench over the control port, making it possible to fill trenches having a high height-to-width aspect ratio (e.g., at least 2:1). The thyristor control port is capacitively coupled to the thyristor region via a dielectric on a sidewall of the trench, and is configured and arranged to control current in the thyristor body via the capacitive coupling.

Abstract: A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor.

Abstract: A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual devices. Each T-RAM cell is planar and has a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate. The buried vertical thyristor is located beneath the horizontally stacked pseudo-TFT transfer gate. A method is also presented for fabricating the T-RAM array having the buried vertical thyristors, the horizontally stacked pseudo-TFT transfer gates and the planar cell structure.

Abstract: A structure and method for a silicon carbide (SiC) gate turn-off (GTO) thyristor device operable to provide an increased turn-off gain comprises a cathode region, a drift region having an upper portion and a lower portion, wherein the drift region overlies the cathode region, a gate region overlying the drift region, an anode region overlying the gate, and at least one ohmic contact positioned on each of the gate region, anode region, and cathode region, wherein the upper portion of the drift region, the gate region, and the anode region have a free carrier lifetime and mobility lower than a comparable SiC GTO thyristor for providing the device with an increased turn-off gain, wherein the free carrier lifetime is approximately 10 nanoseconds. The reduced free carrier lifetime and mobility are affected by altering the growth conditions, such as temperature under which epitaxy occurs.

Abstract: A gate driver includes a control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch. The gate control signal generator is provided proximate a high side of the gate driver. A first sub-circuit has a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay. A comparator is configured to receive signals from the high side. The comparator is provided proximate a low side of the gate driver.

Abstract: A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt that effects a leakage current in the thyristor. The thyristor includes a capacitively-coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region. In one implementation, the current shunt is located between the emitter and base region of one of the end portions of the thyristor and is configured and arranged to shunt low-level current therebetween.

Abstract: A semiconductor element has a semiconductor body of a first conductivity type. The semiconductor body has a zone of a second conductivity type embedded. Further regions of the second conductivity type surround the zone of the second conductivity type like a well. The further regions are interrupted in at least one location by a channel that is formed by the semiconductor body. The further regions are doped with a doping concentration that is high enough so that the further regions are not completely depleted of charge carriers when the semiconductor element is revere-biased.

Abstract: In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A pnpn thyristor element Thy1 and six pn diode elements D1, D2, D3, D4, D5, and D6 are formed in a semiconductor substrate of a first conductivity type, and separated into six regions by a diffusion layer of a second conductivity type which also functions as the anode of the thyristor element Thy1. A double isolation diffusion layer is disposed between the region of the thyristor element Thy1 and three pn diode elements D1 ·D2 and D6, and the region of the three remaining pn diodes D3, D4, and D5. Surface connection is performed to provide a balance type surge protection circuit.

Abstract: Each of outermost segments (OMSG) and innermost segments (IMSG) is utilized as a dummy segment. A top surface of a protruding portion (OMPP, IMPP) of each of the outermost segments (OMSG) and the innermost segments (IMSG) is covered with an insulating layer (1S+1P), and a clearance (CL) is provided between a top surface of the insulating layer (1S+1P) and a bottom surface (2BS) of a cathode strain relief plate. Each of all the other segments (SG) than the outermost and innermost segments has a protruding portion PP on which a cathode electrode (1K-AL) is formed. A thickness (T1) of the cathode electrode (1K-AL) is determined so as to allow a top surface of the cathode electrode (1K-AL) to be in contact with the bottom surface (2BS) of the cathode strain relief plate.

Abstract: A high frequency switch, has a transmitting terminal; a receiving terminal; an antenna terminal; a first diode having an anode electrically connected to the transmitting terminal and a cathode electrically connected to the antenna terminal; a second diode having an anode connected through a transmission line of ¼ wavelength to the antenna terminal which is electrically connected to the receiving terminal, and having the side of a cathode grounded; and a control terminal provided to a node between the transmitting terminal and the first anode, wherein the first and second diodes have a tradeoff relationship between ON resistance thereof and capacitance between the anode and the cathode, and the ON resistance of the first diode is lower than the ON resistance of the second diode, and the capacitance of the second diode in the OFF state is smaller than the capacitance of the first diode in the OFF state.

Abstract: In order to eliminate the difference in ESD resistance caused by polarities of excessive voltages applied to an external terminal and enhance ESD resistance of a semiconductor integrated circuit device to both the positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.

Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.

Abstract: A silicon controlled rectifier, which has a substrate and an overlying epitaxial layer that is formed on the substrate, is formed in the epitaxial layer to have a number of semiconductor regions with alternating dopant conductivity types where a number of the regions extend through the epitaxial layer to the substrate.

Abstract: An individual-well adaptive method of body bias control that mitigates the effects of D2D and WD process variations is shown. It is assumed that p-type transistors are grouped in sections. The bodies of all the p-type transistors within a section are connected to a single n-well. This section size can be small enough to provide fine-granular adjustments to the circuit without having any impact on area overhead. With a small amount of additional circuitry and routing, individual well biases can be intelligently adjusted resulting in closely controlled chip power and performance. Experimental results show that binning yields as low as 17% can be improved to greater than 90% using the proposed method.

Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device including a LOCOS structure and two p-type doping regions, which are positioned one above another therein to isolate cells so as to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n− drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n-drift layer; a pair of field oxide regions and termination region formed into the n− drift layer and each spaced from each other by the mesas, where the mesas have metal silicide layer formed thereon. A top metal layer formed on the field oxide regions and termination region and contact with the silicide layer.

Abstract: In order to provide a reliable surge protective component with a straightforward manufacturing process, first and second buried layers are diffused over the entire inside surfaces of a semiconductor substrate, and first and second base layers are then diffused over the entire inside surfaces of the first and second buried layers. First and second emitter layers are then partially diffused at the inside of the first and second base layers. The peripheries of the first and second emitter layers are then surrounded by first and second moats, the bottoms of which reach the first and second buried layers. A PN junction formed between the first and second base layers and first and second buried layers is then simply a planar junction.

Abstract: An electrostatic discharge (ESD) protection device, for protecting power lines of an integrated circuit. In one embodiment, the ESD protection device includes a first silicon controlled rectifier (SCR) coupled between a first power line and a second power line, and a second SCR coupled anti-parallel to the first SCR between the first and second power lines. A first trigger device is coupled to the first power line and a first trigger gate of the first SCR, and a second trigger device coupled to the second power line and a first trigger gate of the second SCR. The trigger devices and the SCRs provide power-down-mode-compatible operation of the power lines, as well as ESD protection.

Abstract: A pnpn thyristor element Thy1 and six pn diode elements D1, D2, D3, D4, D5, and D6 are formed in a semiconductor substrate of a first conductivity type, and separated into six regions by a diffusion layer of a second conductivity type which also functions as the anode of the thyristor element Thy1. A double isolation diffusion layer is disposed between the region of the thyristor element Thy1 and three pn diode elements D1 . D2 and D6, and the region of the three remaining pn diodes D3, D4, and D5. Surface connection is performed to provide a balance type surge protection circuit.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A silicon controlled rectifier for SiGe process. The silicon controlled rectifier comprises a substrate, a buried layer of a first conductivity type in the substrate, a well of the first conductivity type in the substrate and above the buried layer, a doped region of a second conductivity type in the well, a first conducting layer of the second conductivity type on the substrate, and a second conducting layer of the first conductivity type on the first conducting layer.

Abstract: A bipolar high-voltage power component, in particular an IGBT, includes a semiconductor body on which at least two mutually spaced apart electrodes are provided, between which a drift path is formed in a semiconductor region of a first conduction type. Floating zones of a second conduction type, opposite the first conduction type, are provided in the semiconductor region. When the power component is switched on or switched off, the floating zones respectively emit charge carriers of the second conduction type into the semiconductor region or take up the charge carriers from the semiconductor region. The floating zones are connected, through a respective MOS transistor with a channel of the second conduction type or a bipolar transistor with a base of the first conduction type, to active regions of the power component which are connected to the two electrodes.

Abstract: An electrical switch performs multi-polar switching. A HDFET structure has a source (2) at one terminal and two drains (3(a) and 3(b)) providing isolated terminals at the opposite end. The drains (3(a) and 3(b)) are separated by an insulator (8). N+ gates (6, 7) are at each side of a channel (5) linking the source (2) with the drains (3(a), 3(b)). Bias of the gates (6, 7) is controlled to control depletion regions (21, 22) to switch on or off current flow (A, B) between the source (2) and the drains (3(a), 3(b)).

Abstract: A gate electrode (1a) is formed on the outer peripheral step portion (1′) of a semiconductor substrate (1) so as to face a pressure-contact supporting block (6), and a convex contacting portion (1g) is formed on a predetermined position on the surface of the gate electrode to contact the pressure contact supporting block. The surface area of the gate electrode ranging from the inner periphery to a position adjacent to the convex contacting portion, is coated with an insulation film (1d). The convex contacting portion (1g) is formed of a convex portion integral with the gate electrode or formed of another gate electrode (1a′).

Abstract: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N -type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.

Abstract: A semiconductor component for switching high currents. The semiconductor component includes an LIGBT arrangement having island-shaped p-wells and specially designed cathode regions for improving the latch-up strength of the semiconductor component.

Abstract: An n− type layer 12 is epitaxially grown on one main surface (front surface) of an n+ type silicon substrate 11 and an anode electrode 13 is electrically in contact with the other main surface (rear surface) thereof. A p type region 14 is selectively formed in a surface layer of the n− type layer 12 and a n+ type region 15 is selectively formed in a surface layer of the p type region 14. A cathode electrode 17 is electrically in contact with a surface of the n+ type region 15.

Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a bottom drift layer, with a p-n junction formed below a gate adjacent to the bottom drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The bottom drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage-controlled device using an insulated gate for turn-on and turn-off.

Abstract: A switching device for switching a plurality of RF signal lines to deliver a selected one of the RF signals to a receiver has an isolation D/U characteristic as high as 40 dB or higher. The switching device includes a mounting board made of dielectric and a matrix switch mounted thereon and implemented by one or more of SWIC. The RF signal lines in the switching device has no crossing point therebetween on either side of the mounting board to achieve the high isolation D/U ratio or lower cross-talk.

Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.

Abstract: Each of outermost segments (OMSG) and innermost segments (IMSG) is utilized as a dummy segment. A top surface of a protruding portion (OMPP, IMPP) of each of the outermost segments (OMSG) and the innermost segments (IMSG) is covered with an insulating layer (1S+1P), and a clearance (CL) is provided between a top surface of the insulating layer (1S+1P) and a bottom surface (2BS) of a cathode strain relief plate. Each of all the other segments (SG) than the outermost and innermost segments has a protruding portion PP on which a cathode electrode (1K−AL) is formed. A thickness (T1) of the cathode electrode (1K−AL) is determined so as to allow a top surface of the cathode electrode (1K−AL) to be in contact with the bottom surface (2BS) of the cathode strain relief plate.

Abstract: Tunneling piezoelectric switch structures including high quality epitaxial layers of monocrystalline materials (26) grown overlying monocrystalline substrates (22) such as large silicon wafers are disclosed. The structures includes an accommodating buffer layer (24) spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer.

Abstract: A semiconductor device includes an N channel MOS transistor. The N channel MOS transistor includes a first P type buried layer that isolates an N− epitaxial region formed on a P type substrate (P-SUB) from another N− epitaxial region, a drain formed in an N well in the N− epitaxial region, a source formed in a P well surrounding side faces of the N well so as to be separated from the N well, and a gate formed on each upper layer portion of the drain and the source. The MOS transistor also includes a second P type buried layer formed below the N well and the P well so as to be joined to the P well, and an N+ buried layer formed so as to be joined to the P type buried layer and the P-SUB. The N− epitaxial region, the P-SUB, and the first P type buried layer are connected to ground potential.

Abstract: Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.

Abstract: An IGBT with monolithic integrated antiparallel diode has one or more emitter short regions forming the diode cathode in the region of the high-voltage edge. The p-type emitter regions of S the IGBT have no emitter shorts. The counterelectrode of the diode exclusively comprises p-type semiconductor wells on the front side of the device. Particularly in applications, such as lamp ballast, in which the diode of the IGBT is firstly forward-biased, hard commutation is not effected and the 10 current reversal takes place relatively slowly. The emitter short regions may be strips or points below the high-voltage edge. The horizontal bulk resistance is increased and the snapback effect is reduced without reducing the robustness in the edge region. In a second embodiment, the IGBT is produced 15 using thin wafer technology and the thickness of the substrate defining the inner zone is less than 200 &mgr;m. The thickness of the emitter region or of the emitter regions and short region(s) is less than 1 &mgr;m.

Abstract: A semiconductor device includes an active region with a main semiconductor device section, and a junction-termination region therearound. A first diffusion layer of a second conductivity type is formed in a surface of a first semiconductor layer of a first conductivity type, and extends from the active region into the junction-termination region. A second diffusion layer of the second conductivity type is formed in contact with the first diffusion layer, and extends in the junction-termination region. A first contact electrode is disposed in the active region and in contact with the first diffusion layer, and electrically connected to a first main electrode of the main semiconductor device section. A second contact electrode is disposed in the junction-termination region and in contact with the first diffusion layer, and surrounds the active region. A connection electrode electrically connects the first and second contact electrodes to each other.

Abstract: A power semiconductor switching device such as a power MOSFET that includes breakdown voltage enhancement regions formed by self-alignment.

Abstract: Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides a power semiconductor device including a semiconductive substrate having a surface; and a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent the surface.

Abstract: A plasma oscillation switching device of the present invention comprises semiconductor substrate 101; first barrier layer 103 that is composed of a III-V compound semiconductor and formed on the substrate; channel layer 104 that is composed of a III-V compound semiconductor and formed on the first barrier layer; second barrier layer 105 that is composed of a III-V compound semiconductor and formed on the channel layer; source electrode 107, gate electrode 109 and drain electrode 108 provided on the second barrier layer, wherein the first barrier layer includes n-type diffusion layer 103a, the second barrier layer includes p-type diffusion layer 105a, the band gap of the channel layer is smaller than the band gaps of the first and the second barrier layers, two-dimensional electron gas EG is accumulated at the conduction band at the boundary between the first barrier layer and the channel layer, two-dimensional hole gas HG is accumulated at the valence band at the boundary between the second barrier layer and

Abstract: An ESD protection circuit having a high triggering threshold. The ESD protection circuit comprises a semiconductor-controlled rectifier (SCR) and a bipolar-junction-transistor (BJT). The SCR comprises an anode, an anode gate, a cathode gate and a cathode. The anode is coupled to a first pad. The cathode gate and the cathode are coupled to a second pad. The BJT transistor is parasitic under a metal-on-semiconductor (MOS) transistor and has a collector and an emitter. Either the collector or the emitter is coupled to the anode gate, and the other is coupled only to the second pad. Current generated at the anode is shared by the BJT transistor. A larger current is required to trigger the SCR in the ESD protection circuit of the present invention and result in a latch-up. Thus, latch-up caused by accidental noise is prevented during normal power operations.

Abstract: A gate driver includes a gate control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch and a first sub-circuit having a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay.

Abstract: A method for manufacturing a semiconductor device with a substrate having a device layer and a backside electrode is disclosed. Here, a surface roughness of the substrate is defined as a ratio between a substantial area and a projected area. The method includes polishing and wet-etching a backside surface of the substrate mechanically with using predetermined abrasive grains so that a surface roughness of the backside surface of the substrate becomes to be equal to or larger than 1.04, and forming the backside electrode on the backside surface of the substrate after polishing and wet-etching the backside surface of the substrate.

Abstract: A structure and method for a voltage blocking device comprises a cathode region, a drift region positioned on the cathode region, a gate region positioned on the drift region, an anode region positioned on the gate region and a plurality of contacts positioned on each of the cathode region, the gate region, and the anode region, wherein the drift region comprises multiple epilayers having first doped type layers surrounding second doped type layers, wherein dopant concentrations of the first doped type layers are lower than dopant concentrations of the second doped type layers. The epilayers comprise at least one i-n-i layer and/or at least one i-p-i layer. Moreover, the multiple epilayers are operable to block voltages in the device.

Abstract: A diode includes a semiconductor substrate that is arranged between two metallic electrodes, having a strongly doped first zone that forms an ohmic transition to the first electrode, a weakly doped second zone, having the same conductivity type, that forms a rectifying transition to the second electrode, and a third zone that, having the same conductivity type, is doped more weakly than the second zone. The third zone separates the first and the second zones from one another, and the second zone is enclosed between the second electrode and the third zone.

Abstract: A preferably asymetrical thyristor (1) with at least one driver stage (20) for amplifying a control current (I) fed into the cathodal base (16) of the thyristor, in which, in the driver stage, the transistor gain factors &agr;npn and &agr;pnp are in each case greater than, preferably, in the thyristor and anode short circuits of the thyristor (174) have a smaller electrical conductivity in the driver stage than in the thyristor.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: A silicon controlled rectifier for SiGe process. The silicon controlled rectifier comprises a substrate, a buried layer of a first conductivity type in the substrate, a well of the first conductivity type in the substrate and above the buried layer, a doped region of a second conductivity type in the well, a first conducting layer of the second conductivity type on the substrate, and a second conducting layer of the first conductivity type on the first conducting layer.