Process tube for manufacturing semiconductor wafers

- Tokyo Electron Limited
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Description

FIG. 1 is a front view of the design for a process tube for manufacturing semiconductor wafers in accordance with the invention;

FIG. 2 is a rear view thereof;

FIG. 3 is a right side view thereof;

FIG. 4 is a left side view thereof;

FIG. 5 is a bottom view thereof;

FIG. 6 is a top view thereof; and,

FIG. 7 is a front perspective view thereof.

The broken line showings are for the purpose of illustrating environmental structure and forms no part of the claimed design.

Claims

The ornamental design for a process tube for manufacturing semiconductor wafers, as shown and described.

Referenced Cited
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Patent History
Patent number: D594488
Type: Grant
Filed: Oct 12, 2007
Date of Patent: Jun 16, 2009
Assignee: Tokyo Electron Limited (Tokyo)
Inventors: Masataka Toiya (Yamanashi), Yoshikatsu Mizuno (Yamanashi), Hisashi Inoue (Yamanashi)
Primary Examiner: Sandra Snapp
Assistant Examiner: Patricia Palasik
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/290,024