Abstract: The present disclosure provides a thin film transistor and method for repairing the same, GOA circuit and a display device, which aims to solve the problem that the source and/or drain of thin film transistor can not be repaired once it is short circuited with other conductive functional layers. The thin film transistor comprises a source, a drain, and a gate. The source and the drain have a comb shape and respectively comprise a plurality of comb-tooth portions and comb-handle portions for connecting each comb-tooth portion, and the gate is insulated from the source and the drain. Comb-tooth portions of the source are arranged by an interval with respect to comb-tooth portions of the drain. The comb-handle portion of the source and the gate do not overlap in their projections in the vertical direction, and the comb-handle portion of the drain and the gate do not overlap in their projections in the vertical direction.

Abstract: A method of repairing a display substrate includes electrically separating a defective pixel circuit from a pixel electrode and irradiating a laser beam on first and second intersection regions. The laser beam is irradiated on the first intersection region to weld a pixel connection part to a first repair line. The pixel connection part is connected to the pixel electrode at the first intersection region, and intersects the first repair line. The first repair line includes a first welding hole at the first intersection region. The laser beam is irradiated on the second intersection region to weld a dummy connection part of a dummy circuit to a second repair line. The second repair line intersects the dummy connection part at the second intersection region, and is separated from the pixel circuit. The second repair line includes a second welding hole at the second intersection region.

Abstract: In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state.

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract: A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop.

Abstract: A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line.

Abstract: A semiconductor device and method of forming the same including, in one embodiment, a substrate and a plurality of source and drain regions formed as alternating pattern on the substrate. The semiconductor device also includes a plurality of gates formed over the substrate between and parallel to ones of the plurality of source and drain regions. The semiconductor device also includes a first plurality of alternating source and drain metallic strips formed in a first metallic layer above the substrate and parallel to and forming an electrical contact with respective ones of the plurality of source and drain regions.

Abstract: A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. The active area defined by the switchable cells includes at least a first switchable region having a first transconductance and a second switchable region having a second transconductance which is different from the first transconductance.

Abstract: Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second buffer layer under the first sub stack. An upper layer of the first sub stack is exposed through a set of vias by first and second etching processes. The first etching process forms a first set of etch vias through the second sub stack and stops at or in the first buffer layer. The second etching process etches through the first buffer layer to the upper layer of the first sub stack. A third etching process etches through the first set of etch vias, through the first sub stack and stops at or in the second buffer layer. A fourth etching process and etches through the second buffer layer.

Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.

Abstract: An electrical device including a first semiconductor device in a first region of the SOI substrate and a second semiconductor device is present in a second region of the SOI substrate. The first semiconductor device comprises a first source and drain region that is present in the SOI layer of the SOI substrate, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer. The second semiconductor device comprises a second source and drain region present in a base semiconductor layer of the SOI substrate and a second gate structure, wherein a gate dielectric of the second gate structure is provided by a buried dielectric layer of the SOI substrate and a gate conductor of the second gate structure comprises a same material as the raised source and drain region.

Abstract: A NAND flash memory integrated circuit chip includes a cell area and a peripheral area with structures of different heights, with higher structures in the peripheral area to provide low resistance and lower structures in the memory array so that the risk of word line collapse is maintained at acceptable levels.

Abstract: Disclosed are a resistance-variable memory device including a carbide-based solid electrolyte membrane that has stable memory at a high temperature and a manufacturing method thereof. The resistance-variable memory device includes: a lower electrode, the carbide-based solid electrolyte membrane arranged on the lower electrode, and an upper electrode arranged on the solid electrolyte membrane. In addition, the method for manufacturing the resistance-variable memory device comprises: a step for forming the lower electrode on a substrate, a step for forming the carbide-based solid electrolyte membrane on the lower electrode, and a step for forming the upper electrode on the solid electrolyte membrane.

Abstract: Embodiments of the present disclosure provide an apparatus for providing a combined tap cell and spare cell in a logic design. An integrated circuit contains a plurality of logic cells that are arranged in a series of columns and rows and that include one or more transistors. A first cell includes a logic portion including one or more transistors, and a tap portion. The tap portion provides tap connectivity to the one or more transistors of the subset of the plurality of logic cells, and to the one or more transistors of the logic portion.

Abstract: A method for controlling charge of a battery includes: when charging a battery, monitoring a temperature of the battery in real time, and acquiring a corresponding dynamic factor according to the temperature of the battery, wherein the dynamic factor is used for characterizing a dynamically regulating component of a charge current coefficient during the charge process; calculating a maximum allowed charge current according to the dynamic factor and preset static factors; and controlling the charge of the battery according to the maximum allowed charge current. This enables adaptive charge management according to application scenarios, which effectively avoids the situation where the charge current of the battery is too high or too low, improves the environmental adaptability of battery charging, and further extends the service life of the battery and saves costs. Also provided is a method for controlling charge of a battery.

Abstract: A semiconductor device includes a first and a second active regions having a first conductive type and a second conductive type, respectively, being arranged in a first direction; a gate extending in the first direction; a first and a second channel regions defined under the gate in the first and the active regions, respectively; a first low-concentration doped region, having the second conductive type, formed at sides of the gate in the first active region and a first high-concentration doped region, having the second conductive type, formed at sides of the first low-concentration doped region in the first active region; and a second low-concentration doped region, having the first conductive type, formed at sides of the gate in the second active region and a second high-concentration doped region, having the first conductive type, formed at sides of the second low-concentration doped region in the second active region.

Abstract: Various embodiments provide a semiconductor structure having a common gate and fabrication method of the semiconductor structure. In an exemplary method, after forming a first metal gate and a second metal gate, a conductive material layer can be formed at least at the boundary between the first metal gate and the second metal gate. Thus, one end of the conductive material layer can be connected to a first metal gate electrode, and the other end of the conductive material layer can be connected to a second metal gate electrode. The resistance between the first metal gate electrode and the second metal gate electrode can be effectively reduced. Gate voltages of an NMOS transistor and a PMOS transistor of the common gate can be the same.

Abstract: A method for manufacturing a component built-in substrate is disclosed, which can attain high densities of components and wirings. The method includes: mounting electronic components on a predetermined member with its surface being provided with a first layer enabled to be exfoliated; stacking a second layer to fill the electronic components further on the first layer; exfoliating and removing the predetermined member from a stacked body configured by stacking the second layer on the first layer; and forming a via to penetrate the first layer and conduct to the electronic components from a surface of the surfaces of the stacked body, from which the predetermined member is removed.

Abstract: A nanoscale switching device has an active region containing a switching material capable of carrying a species of dopants and transporting the dopants under an electrical field. The switching device has first, second and third electrodes with nanoscale widths. The active region is disposed between the first and second electrodes. A resistance modifier layer, which has a non-linear voltage-dependent resistance, is disposed between the second and third electrodes.

Abstract: A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.

Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.

Abstract: A semiconductor device includes a substrate, a plurality of conductive pads formed in consecutive conductive layers, and a bump structure. The plurality of conductive pads is aligned and arranged one above another over the substrate. The plurality of conductive pads comprises a first conductive pad and a second conductive pad. The first conductive pad is above the second conductive pad. A redistribution layer extends the second conductive pad. The first conductive pad is not extended by a redistribution layer. The bump structure is formed directly on the first conductive pad and electrically coupled to the plurality of conductive pads.

Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.

Abstract: A 3D semiconductor device and a 3D logic array structure thereof are provided. The 3D semiconductor device includes an array structure, a periphery line structure and a 3D logic array structure. The array structure has Y contacts located at a side of the array structure. Y is within MN-1 to MN. Y, M and N are natural numbers. M is larger or equal to 2. The 3D logic array structure includes N sets of gate electrodes, an input electrode and Y output electrodes. Each set of the gate electrodes has M gate electrodes. The Y output electrodes connect the Y contacts. The M·N gate electrodes and the input electrode connect the periphery line structure.

Abstract: A circuit board comprising a circuit carrier, a cover layer composed of a nonconductive material, comprising an organic substance, arranged on the circuit carrier, a first metallization layer at least partly arranged on the cover layer, wherein the first metallization layer has a flexible region.

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.

Abstract: A stacked layer type semiconductor device includes N memories each including at least one main via and (N?1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1.

Abstract: Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed self-assembly (DSA), forming a metal layer over the DSA pre-patterned transistor layout, including: forming a plurality of horizontal metal lines; and forming a plurality of vertical metal segments discontinuous from and between adjacent horizontal metal lines; and forming one or more bridging dots each connecting one of the plurality of horizontal metal lines to one of the plurality of vertical metal segments, wherein locations of the bridging dots determine logic functions of resulting transistor cells.

Abstract: An integrated circuit with electrically programmable fuse circuitry coupled to a programming transistor is provided. The programming transistor may be a metal-oxide-semiconductor transistor that is separated from other circuitry in an integrated circuit substrate with shallow trench isolation. The electrically programmable fuse circuitry may be formed in a second layer above the integrated circuit substrate using a conductive material which may be tungsten-based. This second layer may further include interconnect wires made from the same conductive material. The electrically programmable fuse may be coupled to the programming transistor through vias and routing paths in a fourth layer above the integrated circuit substrate. The routing paths in the fourth layer may be made from a conductive material which may be different than the fuse conductive material used to form the programmable fuse circuitry.

Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.

Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.

Abstract: To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film of the abutting portion. Over sidewalls SW facing each other in the abutting portion between gate electrodes G2 and G5, a liner insulating film 6 and an interlayer insulating film 7 are formed. Between the sidewalls SW, the liner insulating film 6 formed on each of the side walls of the sidewalls SW are brought in contact with each other to close a space between the sidewalls SW to prevent a void from being generated inside the interlayer insulating film 7 and the liner insulating film 6.

Abstract: An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate.

Abstract: There is provided a wiring material including a core layer made of metal and a clad layer made of metal and a fiber in which the core layer is copper or an alloy containing copper and the clad layer is formed of copper or the alloy containing copper and the fiber having a thermal expansion coefficient lower than that of copper, the wiring material having a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, and the fiber in the clad layer is arranged so as to be parallel to the surface of the core layer.

Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

Abstract: A via-configurable logic block architecture for a Structured ASIC has a plurality of MOSFET transistor chains connected to one another through vias. In one embodiment there are three chains and the first transistor chain is a NFET transistor chain, the second transistor chain is a PFET transistor chain, and the third transistor chain is a NFET transistor chain. The first, second and third transistor chains are formed into devices made of transistors that are selected from a voltage threshold group consisting of LVT, SVT and HVT devices, where the first and third transistor chains are formed into devices from a voltage threshold group that is different from one another. In another embodiment transistor drive strength may be varied in the transistor chains of the logic block. In yet another embodiment both voltage threshold and drive strength may be varied together in a symmetrical manner.

Abstract: A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.

Abstract: A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.

Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.

Abstract: A this film transistor is provided. The thin film transistor includes a semiconductor layer including a source region, a drain region, and a channel region, wherein the channel region is provided between the source region and the drain region; and a gate electrode overlapping with the channel region, wherein the channel region includes at least a portion of a channel width that is configured to at least one of continuously decrease and continuously increase in a lengthwise direction.

Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).

Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. A substrate with plural metal gates formed thereon is provided, wherein the adjacent metal gates are separated by insulation. A sacrificial layer is formed for capping the metal gates and the insulation, and the sacrificial layer and the insulation are patterned to form at least an opening for exposing the substrate. A silicide is formed corresponding to the opening at the substrate, and a conductive contact is formed in the opening. The conductive contact has a top area with a second diameter CD2 for opening the insulation. A patterned dielectric layer, further formed on the metal gates, the insulation and the conductive contact, at least has a first M0 opening with a third diameter CD3 for exposing the conductive contact, wherein CD2>CD3.

Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.

Abstract: The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.

Abstract: A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity.

Abstract: Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.

Abstract: Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.