Junction Field Effect Transistor In Integrated Circuit Patents (Class 257/272)
  • Patent number: 5677041
    Abstract: A transistor device 10 is disclosed herein. A doped layer 14 of a radiation sensitive material is formed over a substrate 12. The radiation sensitive material 14 may be polyimide, polybenzimidazole, a polymer, an organic dielectrics, a conductor or a semiconductor and the substrate 12 may be silicon, quartz, gallium arsenide, glass, ceramic, metal or polyimide. A neutral (undoped) layer 16 of radiation sensitive material is formed over the doped layer 14. First and second source/drain regions 18 and 20 are formed in the neutral layer 16 and extend to a top portion of the doped layer 14. A gate region 22 is formed in a top portion of the neutral layer 16 between the first source/drain region 18 and second source/drain region 20 such that a channel region 24 is formed in the doped layer 14 beneath the gate region 22.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 14, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Michael C. Smayling
  • Patent number: 5648664
    Abstract: A BIFET vacuum tube replacement structure includes a plurality of devices that replicate the characteristics of a vacuum tube. The vacuum tube replacement structure has the same pin-out as the vacuum tube being replaced and so can be exchanged directly for a vacuum tube in an audio amplifier. The vacuum tube replacement structure is suitable for use in a wide range of audio amplifier applications without modification to the audio amplifiers. Further, there is no noticeable degradation to the human ear in the sound quality when the vacuum tube replacement structure is used in an audio amplifier in place of a vacuum tube. A unitary device that is a combination of a high impedance bipolar like transistor and a unipolar junction field effect transistor, that is referred to as a BIFET, is used in the vacuum tube replacement structure. In one embodiment, the bipolar like transistor is formed in combination with the gate of the unipolar junction field effect transistor.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: July 15, 1997
    Inventors: J. Kirkwood H. Rough, Adrian I. Cogan, Neill R. Thornton
  • Patent number: 5600160
    Abstract: A dual channel field-effect switching device is disclosed. The switching device includes two adjacent semiconductor regions of opposite polarity forming a PN junction therebetween. A gate structure overlying the semiconductor regions controls the presence of two electrically isolated conductive channels formed in selected portions of the semiconductor regions.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: February 4, 1997
    Inventor: Douglas D. Hvistendahl
  • Patent number: 5543643
    Abstract: A transistor circuit is formed on a substrate having source and drain electrodes and multiple current-controlling gates. The two current-controlling gates are separated by spacer oxide material. The first gate is an metal oxide semiconductor (MOS) gate that is insulated from the substrate by a layer of gate oxide. The second gate is a junction field effect transistor (JFET) gate contiguous to the MOS gate that is insulated from the MOS gate by a layer of spacer oxide.
    Type: Grant
    Filed: July 13, 1995
    Date of Patent: August 6, 1996
    Assignee: LSI Logic Corporation
    Inventor: Ashok K. Kapoor
  • Patent number: 5510632
    Abstract: A silicon carbide (SiC) junction field effect transistor (JFET) device is fabricated upon a substrate layer, such as a p type conductivity SiC substrate, using ion implantation for the source and drain areas. A SiC p type conductivity layer is epitaxially grown on the substrate. A SiC n type conductivity layer is formed by ion implantation or epitaxial deposition upon the p type layer. The contacting surfaces of the p and n type layers form a junction. A p+ type gate area supported by the n type layer is formed either by the process of ion implantation or the process of depositing and patterning a second p type layer. The source and drain areas are heavily doped to n+ type conductivity by implanting donor ions in the n type layer.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: April 23, 1996
    Assignee: General Electric Company
    Inventors: Dale M. Brown, Mario Ghezzo
  • Patent number: 5412234
    Abstract: It is possible to limit the voltage across a diode to the level of the pinch-off voltage of a JFET in an integrated circuit by connecting the diode in series with the JFET. As a result, the voltage offered through the JFET can be higher than the breakdown voltage of the diode, which is of particular importance in high-voltage ICs in which a highly doped buried zone is formed below the diode for reducing leakage currents to the substrate. According to the invention, the JFET together with at least one further circuit element is formed in a common island surrounded by an island insulation region. The gate of the JFET extends along the edge of the island and is separated from the relevant portion of the island insulation region substantially only by the source of the JFET. In the pinch-off condition, the gate divides the island into a high-voltage portion and a low-voltage portion which is coupled to the diode.
    Type: Grant
    Filed: August 26, 1994
    Date of Patent: May 2, 1995
    Assignee: U.S. Philips Corporation
    Inventors: Franciscus A. C. M. Schoofs, Adrianus W. Ludikhuize
  • Patent number: 5412235
    Abstract: In a semiconductor integrated circuit, an amplifier FET and a gate bias FET, having the same structure as the amplifier FET and a total gate width smaller than that of the amplifier FET, are disposed close to each other. The gate bias FET is a constituent of a gate bias circuit for the amplifier FET, and the current determined by the drain current of the gate bias FET, first and second resistors respectively connected to drain and source of the gate bias FET, and a diode connected in series to the first resistor is applied to the amplifier FET as a gate bias voltage. In this structure, if the DC characteristic of the amplifier FET varies from chip to chip, the DC characteristic of the gate bias FET formed in the vicinity of and simultaneously with the amplifier FET also varies.
    Type: Grant
    Filed: January 27, 1994
    Date of Patent: May 2, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuharu Nakajima, Hiroto Matsubayashi
  • Patent number: 5393998
    Abstract: The miniaturization of junction field effect transistors constituting memory cells and higher integration of a dynamic semiconductor memory device are attained. Word lines composed of a p-type impurity diffusion layer are formed on an n-type silicon substrate. An n-type impurity diffusion layer is formed within the p-type impurity diffusion layer. The n-type impurity diffusion layer constitutes two source-drain regions and a channel region, and the p-type impurity diffusion layer constitutes a gate region in each junction field effect transistor. The diffusion layer depth of the channel region is less than that of the source-drain regions. Bit lines are connected to one source-drain region, and storage nodes are connected to the other source-drain region. Each capacitor is made of a storage node, a dielectric film and a cell plate electrode.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: February 28, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuya Ishii, Tatsuo Shinohara
  • Patent number: 5338949
    Abstract: A JFET configuration is obtained whose pinch-off voltage can be set by means of mask dimensions, without process changes, and which is at the same time suitable for operation at very low and very high voltages by cascoding of a first JFET with a diffused or implanted channel which is pinched off in lateral direction, parallel to the surface of the semiconductor body, with a second JFET with a high breakdown voltage and a higher pinch-off voltage than the first JFET. To increase the breakdown voltage still further, the combination of the first and second JFET may be further cascoded, without process changes, with a third JFET which has a channel of the conductivity type opposite to that of the first and second JFET.
    Type: Grant
    Filed: April 12, 1993
    Date of Patent: August 16, 1994
    Assignee: U.S. Philips Corporation
    Inventor: Franciscus A. C. M. Schoofs
  • Patent number: 5324969
    Abstract: A field-effect transistor including a first channel layer, formed in contacting relationship with a gate electrode, and a second channel layer, formed on one side or both sides of the first channel layer in non-contacting relationship with the gate electrode, the carrier concentration in the second channel layer being higher than that in the first channel layer but lower than that in high-impurity concentration active layers forming drain and source regions. The field-effect transistor employs an offset gate configuration in which the gate electrode is formed in contacting relationship with the first channel layer at a position nearer to the high-impurity concentration active layer forming the source region than to the high-impurity concentration active layer forming the drain region.
    Type: Grant
    Filed: August 12, 1992
    Date of Patent: June 28, 1994
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeyuki Murai, Takayoshi Higashino, Masao Nishida
  • Patent number: 5323028
    Abstract: In a MOS controlled power device, or MOS composite a static induction thyristor, an static induction thyristor (SI thyristor) unit, a MOS transistor connected in cascode relation to the SI thyristor unit and a voltage regulation element are merged onto the single monolithic chip. The SI thyristor unit has a cathode region of first conductivity type having high impurity concentration, an anode and a gate regions of second conductivity type having high impurity concentration, and a channel region of first conductivity type having low impurity concentration. The MOS transistor has a drain region which is the same region as the cathode region, a well or a base of second conductivity type formed adjacent to the channel region of the SI thyristor unit, and a source region of first conductivity type having high impurity concentration. The source region is formed within the well or above the base.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: June 21, 1994
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Sohbe Suzuki
  • Patent number: 5311156
    Abstract: A DPDT switch includes first and second output signal electrodes opposite each other in an active region on a semiconductor substrate, a third output signal electrode opposite the second output signal electrode in the same active region, and first and second input signal electrodes disposed respectively between the first and second output signal electrodes and between the second and third output signal electrodes, and first control signal electrodes respectively disposed between the first input signal electrode and the first output signal electrode and between the second input signal electrode and the second output signal electrode for switching a signal between the input and output signal electrodes, and second control signal electrodes respectively disposed between the first input signal electrode and the second output signal electrode and between the second input signal electrode and the third output signal electrode for switching an input signal from the first and second input signal electrodes to the sec
    Type: Grant
    Filed: November 23, 1992
    Date of Patent: May 10, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Naoto Andoh
  • Patent number: 5309007
    Abstract: A field effect transistor having a buried gate, and one or more gates disposed along the channel between the source and drain, which cooperate to cause the electric field within the channel along its length to be more uniform, and have a lower field maximum. The geometry and/or doping of the channel can be varied to selectively vary the channel resistivity along its length, which also makes the field more uniform. Because of the more uniform field, electrons are exposed to a higher field strength nearer the source, and are accelerated to higher velocities more quickly, reducing the response time and increasing the frequency range of the transistor. Because the peak field is reduced, the transistor can carry more power without reaching breakdown potential within the channel.
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: May 3, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Galina Kelner, Michael Shur
  • Patent number: 5166768
    Abstract: A compound semiconductor integrated circuit device has a region implanted with an impurity for forming a carrier capture level in an element isolating region in a semi-insulating compound semiconductor substrate. The region includes at least a first region of relatively low implantation concentration of the impurity and a second region of relatively high implantation concentration of the impurity.
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: November 24, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuhiko Ito