Junction Field Effect Transistor In Integrated Circuit Patents (Class 257/272)
  • Publication number: 20130105866
    Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.
    Type: Application
    Filed: December 28, 2012
    Publication date: May 2, 2013
    Inventors: Shigeru KUSUNOKI, Shinichi Ishizawa
  • Patent number: 8421127
    Abstract: A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: April 16, 2013
    Assignee: Windbond Electronics Corp.
    Inventor: Wen-Yueh Jang
  • Patent number: 8415720
    Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 9, 2013
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Badih El-Kareh, Kyu Ok Lee, Joo Hyung Kim, Jung Joo Kim
  • Publication number: 20130083577
    Abstract: The present disclosure discloses an offline low voltage DC output circuit with integrated full bridge rectifiers. The offline low voltage DC output circuit comprises two depletion high voltage pass transistors and a bridge rectifier, wherein most of the voltage is dropped across the pass transistor device. In one embodiment, the offline low voltage DC output circuit further comprises a ballast resistor to minimize substrate injection.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Inventor: Joseph Urienza
  • Publication number: 20130056801
    Abstract: A junction field effect transistor comprising: a semiconductor substrate having a first conductivity type; a channel region having a second conductivity type different from the first conductivity type, and being formed in a surface of the semiconductor substrate; a first buried region having the second conductivity type, being formed within the channel region, and having an impurity concentration higher than the channel region; a first gate region having the first conductivity type, and being formed in a surface of the channel region; and first drain/source region and a second drain/source region both having the second conductivity type, which are formed each on an opposite side of the first gate region in the surface of the channel region, in which the first buried region is not formed below the second drain/source region, but is formed below the first drain/source region.
    Type: Application
    Filed: October 24, 2012
    Publication date: March 7, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: PANASONIC CORPORATION
  • Publication number: 20130049076
    Abstract: The present invention discloses a power device with integrated power transistor and Schottky diode and a method for making the same. The power device comprises a power transistor having a drain region, a Schottky diode in the drain region of the power transistor, and a trench-barrier near the Schottky diode. The trench-barrier is provided to reduce a reverse leakage current of the Schottky diode and minimizes the possibility of introducing undesired parasitic bipolar junction transistor in the power device.
    Type: Application
    Filed: August 22, 2011
    Publication date: February 28, 2013
    Inventor: Donald R. Disney
  • Publication number: 20130032863
    Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 7, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Marie Denison, Sameer Pendharkar, Philip L. Hower, John Lin, Robert A. Neidorff
  • Publication number: 20130032862
    Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.
    Type: Application
    Filed: August 1, 2011
    Publication date: February 7, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8368120
    Abstract: A hybrid device including a silicon based MOSFET operatively connected with a GaN based device.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: February 5, 2013
    Assignee: International Rectifier Corporation
    Inventors: Alexander Lidow, Daniel M. Kinzer, Srikant Sridevan
  • Patent number: 8362553
    Abstract: A method includes forming elongate structures on a first substrate, such that the material composition of each elongate structure varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices are then defined in the elongate structures. Alternatively, the first and second physically different sections may be defined in the elongate structures after they have been fabricated. The elongate structures may be encapsulated and transferred to a second substrate. The invention provides an improved method for the formation of a circuit structure that requires first and second physically different devices to be provided on a common substrate. In particular, only one transfer step is necessary.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: January 29, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Thomas Heinz-Helmut Altebaeumer, Stephen Day, Jonathan Heffernan
  • Publication number: 20130020615
    Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 24, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, David Horak, Sivananda K. Kanakasabapathy
  • Publication number: 20130015508
    Abstract: A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 17, 2013
    Applicant: WINBOND ELECTRONICS CORP.
    Inventor: Wen-Yueh Jang
  • Patent number: 8350304
    Abstract: A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: January 8, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Min Hu, Chung Yu Hung, Wing Chor Chan, Jeng Gong
  • Publication number: 20120319177
    Abstract: A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 20, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Masaru SAITO, Koji SONOBE
  • Patent number: 8324666
    Abstract: A semiconductor integrated circuit device includes a substrate, a well structure within the substrate, a first region, a second region, and multiple isolation regions within the well structure. The device further includes a channel region within the first region, a gate dielectric layer overlying the channel region, and a gate stack overlying the gate dielectric layer, the gate stack includes a silicide layer overlying a polysilicon layer. The device additionally includes LDD structures on sides of the channel region and spacers on sides of the gate stack. Furthermore, the device includes a source region and a drain region and a contact structure over the source region, and a junction between the contact structure and the source region being within the second region.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: JoBong Choi
  • Publication number: 20120286334
    Abstract: Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.
    Type: Application
    Filed: July 25, 2012
    Publication date: November 15, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Michael Sommer
  • Patent number: 8278691
    Abstract: There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: October 2, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Publication number: 20120241820
    Abstract: There are disclosed herein various implementations of semiconductor devices having passive oscillation control. In one exemplary implementation, such a device is implemented to include a III-nitride transistor having a source electrode, a gate electrode and a drain electrode. A damping resistor is configured to provide the passive oscillation control for the III-nitride transistor. In one implementation, the damping resistor includes at least one lumped resistor.
    Type: Application
    Filed: March 14, 2012
    Publication date: September 27, 2012
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventors: Michael A. Briere, Naresh Thapar
  • Publication number: 20120205725
    Abstract: Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.
    Type: Application
    Filed: April 21, 2012
    Publication date: August 16, 2012
    Applicant: IO SEMICONDUCTOR, INC.
    Inventors: Paul A. Nygaard, Stuart B. Molin, Michael A. Stuber
  • Patent number: 8232585
    Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: July 31, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Publication number: 20120175635
    Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
    Type: Application
    Filed: October 17, 2011
    Publication date: July 12, 2012
    Applicant: Infineon Technologies Austria AG
    Inventors: Rolf Weis, Franz Hirler, Matthias Stecher, Armin Willmeroth, Gerald Deboy, Martin Feldtkeller
  • Publication number: 20120175634
    Abstract: A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor.
    Type: Application
    Filed: January 7, 2011
    Publication date: July 12, 2012
    Inventor: Rolf Weis
  • Patent number: 8202772
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: June 19, 2012
    Assignee: SS SC IP, LLC
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Publication number: 20120146105
    Abstract: A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
    Type: Application
    Filed: February 10, 2012
    Publication date: June 14, 2012
    Applicant: Power Integrations, Inc.
    Inventors: Sujit Banerjee, Vijay Parthasarathy
  • Patent number: 8198698
    Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Maeda, Yasushi Sekine, Tetsuya Watanabe
  • Patent number: 8193565
    Abstract: A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert Kuo-Chang Yang, Muhammed Ayman Shibib, Richard A. Blanchard
  • Patent number: 8178911
    Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 15, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, Larson Lindholm
  • Patent number: 8134188
    Abstract: Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the source to the drain, and the transistors are matched one to another.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: March 13, 2012
    Assignee: AGERE Systems Inc.
    Inventors: Kenneth G. Richardson, Michael Straub
  • Patent number: 8110857
    Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: February 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
  • Patent number: 8097905
    Abstract: A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: January 17, 2012
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Hideaki Tsuchiko
  • Publication number: 20110316055
    Abstract: A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and second portions is separated from the support substrate by an electrically insulating material. The electrically insulating material is different from the material forming the support substrate. The first portion of the semi-conducting area is facing the first counter-electrode. The second portion of the semi-conducting area is facing the second counter-electrode.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 29, 2011
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Philippe CORONEL, Claire FENOUILLET-BÉRANGER, Stéphane DENORME, Olivier THOMAS
  • Patent number: 8058655
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 15, 2011
    Assignee: SS SC IP, LLC
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Patent number: 8048731
    Abstract: A method for reducing low frequency noise of a transistor operable at cryogenic temperatures includes a first step in which the transistor is illuminated with a light in a state that the transistor is activated and flowed current by supplying a power at a predetermined temperature, and a second step in which the transistor is operated at the predetermined temperature after the illumination of the light.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: November 1, 2011
    Assignees: National Institute of Information and Communications Technology, National Institutes of Natural Sciences
    Inventors: Mikio Fujiwara, Masahide Sasaki, Hiroshi Matsuo, Hirohisa Nagata
  • Patent number: 8049223
    Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.
    Type: Grant
    Filed: May 25, 2008
    Date of Patent: November 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Haruka Shimizu, Hidekatsu Onose
  • Publication number: 20110254059
    Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
    Type: Application
    Filed: June 23, 2011
    Publication date: October 20, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert R. Robison
  • Patent number: 8035139
    Abstract: A dynamic random access memory (DRAM) device can include a plurality of memory cells. Each memory cell can include a charge storing structure and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device can further include a plurality of sense amplifiers that each generates an output value in response to a signal received at respective sense amplifier inputs, and a plurality of bit lines, each bit line coupling a plurality of memory cells to at least one input of at least one of the sense amplifiers. A method can fabricate such DRAM devices.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: October 11, 2011
    Assignee: SuVolta, Inc.
    Inventor: Douglas B. Boyle
  • Patent number: 8026555
    Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: September 27, 2011
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, HsiangChih Sun
  • Publication number: 20110227135
    Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact, the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.
    Type: Application
    Filed: June 1, 2011
    Publication date: September 22, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
  • Publication number: 20110228575
    Abstract: A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.
    Type: Application
    Filed: March 22, 2011
    Publication date: September 22, 2011
    Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.
    Inventors: Masaru SAITO, Koji SONOBE
  • Publication number: 20110220973
    Abstract: A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions.
    Type: Application
    Filed: June 7, 2010
    Publication date: September 15, 2011
    Inventors: Chih-Min HU, Chung Yu HUNG, Wing Chor CHAN, Jeng GONG
  • Publication number: 20110210379
    Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.
    Type: Application
    Filed: April 13, 2011
    Publication date: September 1, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Badih El-Kareh, Leonard Forbes
  • Patent number: 8008731
    Abstract: An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first conductivity-type abutting the surface and spaced from the source region with a channel (5) therefrom, —an active gate (8) overlying the channel and insulated from the channel by a first dielectric material (9) forming the gate oxide of the IGFET device, —a dummy gate (10) positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: August 30, 2011
    Assignee: Acco
    Inventor: Denis Masliah
  • Publication number: 20110193142
    Abstract: A method of fabricating an LFCC device includes forming a first trench in a substrate that extends vertically from an upper surface to a depth within the substrate, the first trench having first sidewalls, a first bottom, and a pattern formed on the first sidewalls near the first bottom of the trench, and forming an oxide layer on the first sidewalls and first bottom of the first trench that leaves a second trench located within the first trench and is separated from the first trench by the oxide layer. The second trench has second sidewalls that are substantially vertical without showing the pattern and a second bottom that is substantially flat. The pattern compensates for the difference in oxidation rates between the bottom of the first trench and the first sidewalls. The LFCC structure includes a first trench with the pattern.
    Type: Application
    Filed: January 27, 2011
    Publication date: August 11, 2011
    Inventors: Matthew A. Ring, Henry G. Prosack, JR.
  • Patent number: 7994535
    Abstract: To improve the surge resistance of J-FET, a P-type epitaxial layer 2 and an N-type epitaxial layer 3 are formed on a P++-conductive substrate 1; N+-conductive source diffusion layer 4 and drain diffusion layer 5, and a p+-conductive gate diffusion layer 6 are formed in the N-type epitaxial layer 3; and a short-circuit preventing layer 8 of a reversed conduction-type diffusion layer is formed adjacent to the side walls of the source diffusion layer 4 and the drain diffusion layer 5. Having the constitution, the punch-through to be caused by surge voltage is prevented in the surface region of the device, and the surge resistance thereof is improved. Via the holes formed in a protective insulation film 9 on the surface of the device, a source electrode 10 connected to the source diffusion layer 4, and a drain electrode 11 connected to the drain diffusion layer 5 are formed on the surface side of the device.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: August 9, 2011
    Assignee: Panasonic Corporation
    Inventors: Hiroyuki Gunji, Tetsushi Otaki
  • Patent number: 7989284
    Abstract: A method for forming a memory device. The method provides a protective layer overlying a surface region of a substrate before threshold voltage implant. The method then includes depositing a photo resist layer and patterning the photo resist by selectively removing a portion of the photo resist to expose the protective layer overlying a first region while maintaining the photo resist overlying a second region. The method includes implanting impurities for threshold voltage adjustment into the first region while the second region is substantially free of the impurities for threshold voltage adjustment. The method also includes forming a source region and a drain region. The method further includes providing a conductive structure over the source region. A junction between the conductive structure and the source region is substantially within the second region. The method then provides a storage capacitor in electrical contact with the source region via the conductive structure.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: August 2, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: JoBong Choi
  • Patent number: 7989853
    Abstract: A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: August 2, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Sameer Pendharkar, Philip L. Hower, Marie Denison
  • Patent number: 7973344
    Abstract: Double gate JFET with reduced area consumption and fabrication method therefore. Double-gate semiconductor device including a substrate having a shallow trench isolator region comprising a first STI and a second STI, a channel region having a first and second channel edges, the channel region formed in the substrate and disposed between and in contact with the first STI and the second STI at the first and second channel edge. The first STI has a first cavity at the first channel edge, and the second STI has a second cavity at the second channel edge. The device further includes a gate electrode region comprising conductive material filling at least one of the first and second cavities. At least one of the first and second cavities is physically configured to provide electrical coupling of the gate electrode region to a back-gate P-N junction.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: July 5, 2011
    Assignee: SuVolta, Inc.
    Inventor: Srinivasan R. Banna
  • Patent number: 7968916
    Abstract: Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: June 28, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Jacob Robert Anderson, William Jones
  • Publication number: 20110147808
    Abstract: A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.
    Type: Application
    Filed: March 1, 2011
    Publication date: June 23, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Frederick G. Anderson, David S. Collins, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak
  • Patent number: 7964870
    Abstract: To provide a display device capable of reliably forming a resistive element formed on a substrate including pixels. A display device including at least a thin-film transistor and a resistive element on a substrate has a gate electrode, an insulating film, a semiconductor layer and a conductive layer which are sequentially stacked on the substrate, in which the resistive element is formed by using the semiconductor layer formed between end portions of wiring made of the conductive layer as a resistive body, and at least one conductive layer apart from the end portions is formed on the semiconductor layer between the end portions of wiring.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: June 21, 2011
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Tsuyoshi Uchida, Hiroshi Katayanagi