Abstract: The twist axle assembly includes a pair of spaced apart trailing arms and a twist beam of which extends in a first direction between the trailing arms. The twist beam includes a pair of end portions and a middle portion. The twist beam further has a pair of side walls and at least one additional wall that extends between the side walls. The side walls in the middle portion are generally parallel with the side walls of the end portions. The twist beam is generally hour-glass shaped with the middle portion having a first width and the end portions have a greater second width. The twist beam also tapers from the first width of the middle portion to the second widths of the end portions for gradually increasing a torsional stiffness from the middle portion to the end portions.

Abstract: The present disclosure discloses an array substrate, the array substrate comprises a substrate as well as a thin film transistor and a pixel electrode formed on the substrate, wherein the top of the thin film transistor is formed a floating gate electrode, at least portion of the floating gate electrode and the pixel electrode are made of the same material. The present disclosure also discloses a manufacturing method of an array substrate. Through this way, the present disclosure simultaneously forms a floating gate electrode in the manufacturing process of the pixel electrode, the pixel electrode and the floating gate electrode is formed by a mask, there is no need to add a mask, thus achieving the manufacture of the dual gate thin film transistor and the array substrate, briefing the process, reducing the production costs.

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

Abstract: A semiconductor device includes a semiconductor substrate, a tunnel dielectric disposed on the semiconductor substrate, a floating gate disposed on the tunnel dielectric, a control gate disposed on the floating gate, and an insulation layer disposed between the floating gate and the control gate. The semiconductor device further includes a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, and the spacer overlaps portions of the top surface of the floating gate.

Abstract: A method of forming a FG OTP/MTP cell with a P+ drain junction at the NCAP region and the resulting device are provided. Embodiments include forming MVPW regions laterally separated in a p-sub; forming a MVNW region in the p-sub between the MVPW regions; forming a first RX, a second RX, and a third RX in the MVPW and MVNW regions, respectively; forming a first and a second pair of floating gates separated over and perpendicular to the first and second RX and the second and third RX, respectively; forming a N+ source region between and adjacent to each FG of the first and the second pair in the second RX; and forming a pair of P+ drain regions in the second RX, each P+ drain region adjacent to a FG of the first pair and a FG of the second pair and remote from the N+ source region.

Abstract: In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.

Abstract: A method of manufacturing a semiconductor device having a memory cell for a split-gate MONOS memory with a halo region, which prevents miswriting in the memory cell and worsening of short channel characteristics. In the method, a first diffusion layer of a drain region and a second diffusion layer of a source region in the memory cell for the MONOS memory are formed in different ion implantation steps. The steps are carried out so that the first diffusion layer has a smaller formation depth than the second diffusion layer. After the formation of the layers, the impurities inside the first and second diffusion layers are diffused by heat treatment to form a first diffusion region and a second diffusion region.

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

Abstract: In one embodiment, a semiconductor device includes a substrate, and first to fourth interconnects provided on the substrate to be adjacent to one another. The device includes a first pad portion connected with the first or second interconnect, and a second pad portion adjacent to the first pad portion in a first direction. The device includes a third pad portion connected with the third or fourth interconnect, and adjacent to one of the first and second pad portions in a second direction, and a fourth pad portion adjacent to the third pad portion in the first direction, and adjacent to the other of the first and second pad portions in the second direction. The device includes one or more interconnects insulated from the first to fourth interconnects and the first to fourth pad portions, and provided between the first and second interconnects and the third and fourth interconnects.

Abstract: A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.

Abstract: Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a single polysilicon EEPROM and a double polysilicon EEPROM. The two-in-one hybrid EEPROM can be programmed and/or erased as a single polysilicon EEPROM and/or as a double polysilicon EEPROM. The hybrid EEPROM memory cell includes a programmable capacitor disposed on a substrate. The programmable capacitor includes a floating gate forming a first polysilicon layer, an oxide-nitride-oxide (ONO) layer having disposed over a first surface of the floating gate, and a control gate forming a second polysilicon layer with the control gate formed over a first surface of the ONO layer to form a hybrid EEPROM having a single polysilicon layer and a double polysilicon EEPROM. The single polysilicon EEPROM includes the first polysilicon layer and the double polysilicon EEPROM includes the first and second polysilicon layers.

Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.

Abstract: A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is provided. The memory cell is disposed on the substrate and has a channel region located in the substrate. The first doped region, the second doped region, and the third doped region are sequentially disposed in the substrate in an arrangement direction toward the channel region, and the first doped region is farthest from the channel region. The first doped region and the third doped region are of a first conductive type, and the second doped region is of a second conductive type.

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.

Abstract: A method for forming a semiconductor device structure includes providing a substrate having a first fin structure and a second fin structure that are capped by a patterned hard mask structure. A liner layer and an overlying insulating layer are formed between the first and second fin structures. A multi-step etching process including a first step of selectively removing the patterned hard mask structure and a second step of in-situ and selectively removing a portion of the insulating layer to form an isolation feature is performed. The process gas used in the multi-step etching process includes a first etching gas and a second etching gas. The flow rate of the first etching gas is greater than that of the second etching gas in the first step and the flow rate of the first etching gas is less than that of the second etching gas in the second step.

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

Abstract: Embodiments of the invention provide a method for treating a microelectronic substrate with dilute TMAH. In the method, a microelectronic substrate is received into a process chamber, the microelectronic substrate having a layer, feature or structure of silicon. A treatment solution is applied to the microelectronic substrate to etch the silicon, where the treatment solution includes a dilution solution and TMAH. A controlled oxygen content is provided in the treatment solution or in an environment in the process chamber to achieve a target etch selectivity of the silicon, or a target etch uniformity across the layer, feature or structure of silicon, or both by the treatment solution.

Abstract: A three dimensional ReRAM device includes an etch stop dielectric material layer overlying top surfaces of the dielectric rail structures and the dielectric pillar structures. The etch stop dielectric material layer includes openings in areas that overlie semiconductor pillars of the vertical select transistors. An array of metal nitride portions is located within the openings in the etch stop dielectric material layer. The etch stop dielectric material layer protects the underlying dielectric pillar structures during anisotropic etching steps without covering the metal nitride portions.

Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.

Abstract: Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a gate insulating film provided on a front surface of the silicon carbide semiconductor substrate and including any one or a plurality of an oxide film, a nitride film, and an oxynitride film, and a gate electrode containing poly-silicon and provided on the gate insulating film. A concentration of fluorine in the gate insulating film at an interface with the silicon carbide semiconductor substrate is equal to or higher than 1×1019 atoms/cm3.

Abstract: A semiconductor memory device according to an embodiment includes: first and second memory columnar bodies aligned in a second direction intersecting a first direction, the first and second memory columnar bodies respectively including a semiconductor layer and extending in the first direction; a bit line disposed above the first and second memory columnar bodies; and a first connecting line disposed between the first and second memory columnar bodies and the bit line in the first direction and electrically coupled to the semiconductor layers of the first and second memory columnar bodies and the bit line, the first connecting line extending linearly in the second direction, and a center line widthwise of the first connecting line being in a position displaced in a third direction, the third direction intersecting the first and second directions, from positions of centers of the first and second memory columnar bodies.

Abstract: A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.

Abstract: A semiconductor device includes a plurality of trenches extending into a semiconductor substrate. Each trench comprises a plurality of enlarged width regions distributed along the trench. At least one electrically conductive trench structure is located in each trench. The semiconductor device comprises an electrically insulating layer arranged between the semiconductor substrate and an electrode structure. The semiconductor device comprises a vertical electrically conductive structure extending through the electrically insulating layer. The vertical electrically conductive structure forms an electrically connection between the electrode structure and an electrically conductive trench structure located in a first trench of at a first enlarged width region.

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. The semiconductor structure is disposed on the substrate and has a plurality of openings penetrating through the semiconductor structure and extending into the substrate. The semiconductor structure includes a substrate, a stacked structure and an epitaxial layer. The stacked structure includes insulating layers and gate layers stacked alternatively. Each of the plurality of openings includes a first portion located above the surface of the substrate and a second portion located below the surface of the substrate. The aspect ratio of the second portion is more than 1. The epitaxial layer is disposed in each of the plurality of openings. The top surface of the epitaxial layer is between the top surface and the bottom surface of the i-th insulating layer as counted upward from the substrate, wherein i?2.

Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively disposed on the silicon substrate and connected to each other. A limiting block is disposed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer blanketly covering the first structure, the second structure and the limiting block, in which the BARC layer comprises a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are disposed on the external surface of the BARC layer.

Abstract: A semiconductor substrate (1) includes a region (AR3) between a region (AR1) and a region (AR2), a control gate electrode (CG) is formed on an upper surface (TS1) of the region (AR1), and a memory gate electrode (MG) is formed on an upper surface (TS2) of the region (AR2). The upper surface (TS2) is lower than the upper surface (TS1), and the region (AR3) has a connection surface (TS3) connecting the upper surface (TS1) and the upper surface (TS2). An end (EP1) of the connection surface (TS3) which is on the upper surface (TS2) side is arranged closer to the memory gate electrode (MG) than an end (EP2) of the connection surface (TS3) which is on the upper surface (TS1) side, and is arranged lower than the end (EP2).

Abstract: A manufacturing method of a Flash wafer, comprises: fabricating a Flash wafer containing a cell area, a logical area and a capacitance area; adjusting the height of the silicon oxide filled shallow trench in the logical area and the capacitance area; sequentially depositing a silicon nitride layer and a silicon oxide layer on the upper surface of the Flash wafer, and sequentially removing the silicon oxide layer and the silicon nitride layer on the upper surface of the cell area and on the upper surface of the floating gate in the logical area and the capacitance area; adjusting the height of the silicon oxide filled shallow trench in the cell area and the capacitance area; depositing an interlayer dielectric layer on the surface of the Flash wafer; removing the rest part in the logical area by protecting the cell area and the capacitance area with a mask.

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

Abstract: A semiconductor device includes a stack structure located on a substrate and includes a first region, in which sacrificial layers and insulating layers are alternately stacked, and a second region, in which conductive layers and insulating layers are alternately stacked. The stack structure also includes a first slit insulating layer located at a boundary between the first region and the second region, wherein the first slit insulating layer penetrates the stack structure and extends in one direction. The stack structure further includes a plurality of slit insulating patterns located in the second region, wherein the plurality of slit insulating patterns penetrate the stack structure and are arranged along the one direction. At least one conductive layer among the conductive layers is bent between the first slit insulating layer and the slit insulating patterns.

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

Abstract: A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell.

Abstract: A method of forming a NAND flash memory includes forming a conductive area in a substrate, the conductive area extending along a direction that is perpendicular to the direction along which NAND strings extend, the conductive area connecting terminals of NAND strings. Discrete contact areas in the conductive area are contacted by discrete contact plugs, each contact plug contacting a corresponding contact area in the conductive area.

Abstract: A method for fabricating a memory device is provided. The method for fabricating a memory device includes forming a first dielectric layer over a substrate and forming a floating gate layer over the first dielectric layer. The method further includes forming a hard mask layer over the floating gate layer and etching the hard mask layer to form a recess in the hard mask layer. The method further includes patterning a portion of the hard mask layer under the recess to form a recessed feature having a first tip corner and etching the recessed feature and the floating gate layer to form a floating gate having a second tip corner. The method further includes depositing a second dielectric layer over the floating gate and forming a control gate partially over the floating gate and separating from the floating gate by the second dielectric layer.

Abstract: A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Abstract: A method includes patterning a substrate to form a nanowire over the substrate, applying a plurality of doping processes to the nanowire to form a first drain/source region at a lower portion of the nanowire, a second drain/source region at an upper portion of the nanowire and a channel region, wherein the channel region is between the first drain/source region and the second drain/source region, depositing a first dielectric layer along sidewalls of the channel region, depositing a control gate layer over the first dielectric layer, wherein the control gate layer surrounds a lower portion of the channel region, depositing a second dielectric layer along the sidewalls of the channel region and over the control gate layer and forming a floating gate region surrounding an upper portion of the channel region.

Abstract: A power chip includes: a first power switch, formed in a wafer region and having a first metal electrode and a second metal electrode; a second power switch, formed in the wafer region and having a third metal electrode and a fourth metal electrode, wherein the first and second power switches respectively constitute an upper bridge arm and a lower bridge arm of a bridge circuit, and the first and second power switches are alternately arranged along at least one dimension direction; and a metal region, at least including a first metal layer, a second metal layer and a third metal layer that are stacked in sequence, each metal layer including a first strip electrode, a second strip electrode and a third strip electrode, and strip electrodes with the same voltage potential in two adjacent metal layers are electrically coupled.

Abstract: A method of fabricating asymmetric vertical field effect transistors (VFETs) includes forming mandrels above a substrate comprising a first semiconductor material. A first set of spacers is formed adjacent to each side of the mandrels, and trenches are formed in portions of the substrate that are not below one of the mandrels or one of the first set of spacers. The method also includes filling the trenches with a second semiconductor material that is different from the first semiconductor material and forming a second set of spacers adjacent to each respective one of the first set of spacers. The second set of spacers is above the second semiconductor material. A plurality of fins is formed such that each one of the plurality of fins includes a portion of the substrate and a portion of the second semiconductor material. Gates are formed between each adjacent pair of fins.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate comprising an active region, and successive layers of a tunnel oxide layer, a floating gate, a gate dielectric layer, a control gate overlying each other. A first portion of the tunnel oxide layer disposed on an edge of the active region has a thickness that is greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region. Such features ensure efficient reduction of read disturb errors of a Flash memory device.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned back-plane and well contacts for a fully depleted silicon on insulator device and methods of manufacture. The structure includes a back-plane, a p-well and an n-well formed within a bulk substrate; a contact extending from each of the back-plane, the p-well and the n-well; a gate structure formed above the back-plane, the p-well and the n-well; and an insulating spacer isolating the contact of the back-plane from the gate structure.

Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a vertical three-dimensional semiconductor device and a method for manufacturing such a device. In one aspect, the vertical three-dimensional semiconductor device has a source layer formed over a substrate. A horizontal stack of alternating electrically isolating layers and electrically conductive gate layers are formed over the source layer, wherein one of the electrically isolating layers contacts the source layer. A vertical channel structure extends vertically through the horizontal stack of alternating layers. A drain is formed over the horizontal stack of alternating layers and over the vertical channel structure. The source layer is configured to inject charge carriers into the vertical channel structure, and the metal drain is configured to extract charge carriers from the vertical channel structure.

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

Abstract: A nonvolatile memory (NVM) cell includes a semiconductor substrate having a first OD region and a second OD region for forming an erase gate (EG) region. The second OD region is spaced apart from the first OD region and is separated from the first OD region by a trench isolation region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is also disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A first floating gate extension continuously extends from the floating gate to the second OD region. The first floating gate extension comprises a P+ doped segment and an N+ doped segment with a P+/N+ interface therebetween.