Abstract: A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.

Abstract: A manufacturing method of a semiconductor device in which the threshold voltage is adjusted is provided. The semiconductor device includes a first semiconductor, an electrode electrically connected to the first semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the first semiconductor. By performing heat treatment at higher than or equal to 125° C. and lower than or equal to 450° C. and, at the same time, keeping a potential of the gate electrode higher than a potential of the electrode for 1 second or more, the threshold voltage is increased.

Abstract: A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through fast operation of the SRAM are disclosed. A non-volatile semiconductor memory device can achieve reduction in a voltage necessary for a programming operation to program SRAM data to the non-volatile memory unit. Thus, a first access transistor, a second access transistor, a first load transistor, a second load transistor, a first drive transistor, and a second drive transistor included in the SRAM connected with the non-volatile memory unit can each include a gate insulating film having a thickness less than or equal to 4 nm, which achieves fast operation of the SRAM at a lower power supply voltage.

Abstract: A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the isolation structure adjacent an interface between the fin and the isolation structure. The liner layer includes a material different than the isolation structure. A sacrificial gate structure is formed above a portion of the fin and includes a sacrificial gate insulation layer and a sacrificial gate structure. The sacrificial gate structure is removed. The sacrificial gate insulation layer is removed selectively to the liner layer. A replacement gate structure is formed above a portion of the fin in a cavity defined by removing the sacrificial gate structure.

Abstract: Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an embodiment, an MTP memory cell includes a semiconductor substrate, a p-well formed in the semiconductor substrate, and an n-well formed in the semiconductor substrate and isolated from the p-well. The MTP memory cell further includes a p-channel transistor disposed over the n-well and including a transistor gate. Also, the MTP memory cell includes a p-channel capacitor disposed over the p-well and including a capacitor gate. The capacitor gate is coupled to the transistor gate.

Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

Abstract: In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication geometry for each memory cell not to exceed a predetermined aspect ratio. The present implementation allows independent optimization of the thickness of silicide layer in the memory cells region and the non-memory cell region. In particular, in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slit contact for components having the upper poly layer in contact with a lower poly layer (a floating gate poly).

Abstract: A method of forming a semiconductor device includes receiving a structure having a substrate, a gate trench over the substrate, and a dielectric layer over the substrate and surrounding the gate trench. The method further includes forming a gate dielectric layer in the gate trench, forming a barrier layer in the gate trench and over the gate dielectric layer, and treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer. The method further includes forming an n-type work function metal layer over the treated barrier layer.

Abstract: The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

Abstract: A structure and method of making a semiconductor device includes a single-gated vertical field effect transistor (VFET), that has a first fin on a first bottom source/drain region, a gate of a first work force metal (WFM) surrounding the first fin, and a single gate contact connected to the first WFM. Also included is a double-gated VFET, that has a second fin on a second bottom source/drain region, a first gate of the first WFM disposed on a first side of the second fin, a second wider gate of a second WFM disposed on a second side of the second fin, a first gate contact contacting the first narrow gate, and a second gate contact contacting the second wider gate of the second WFM on the second side.

Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

Abstract: A pair of floating gates disposed to be spaced apart from each other by a first distance and a pair of spacer insulating films disposed on each of the pair of floating gates are provided in a memory region. Also, a pair of floating gates disposed to be spaced apart from each other by a second distance and a pair of spacer insulating films disposed on each of the pair of floating gates are provided in a monitor region. Then, the second distance is smaller than the first distance. Thus, by narrowing a distance between the floating gates in the monitor region, a tapered portion can be provided on a side surface portion of the floating gate in the monitor region. Then, by checking this tapered portion, it is possible to understand the shape of the floating gate in the memory region.

Abstract: A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.

Abstract: A semiconductor substrate of any one of a first conductivity type and a second conductivity type includes a first main surface and a second main surface. A first semiconductor layer of the first conductivity type is provided on the first main surface. A second semiconductor layer of the second conductivity type is provided on the first main surface. A first electrode is electrically connected to the first semiconductor layer. A second electrode is electrically connected to the second semiconductor layer. An insulating layer comprises silicon nitride and is arranged between the first semiconductor layer and the second semiconductor layer in an overlap region where the second semiconductor layer is provided above the first semiconductor layer. An anti-diffusion film is arranged between the insulating layer and the first semiconductor layer and is configured to prevent nitrogen from diffusing from the insulating layer into the first semiconductor layer.

Abstract: The present disclosure provides a bottom electrode substrate for a segment-type electrophoretic display. The bottom electrode substrate includes a flexible substrate, a first conductive layer, an insulating layer, a second conductive layer and a segment-type electrode. The first conductive layer is disposed on the flexible substrate. The insulating layer covers the first conductive layer and the flexible substrate, wherein the insulating layer has at least one opening exposing a part of the first conductive layer. The second conductive layer is filled in the opening and in contact with the exposed first conductive layer. The segment-type electrode covers the second conductive layer and the insulating layer, and is in contact with the second conductive layer. A method for manufacturing the bottom electrode substrate is also provided herein.

Abstract: A method of forming a thick EG polysilicon over the FG and resulting device are provided. Embodiments include forming a CG on a substrate; forming an STI between a logic region and the CG; forming a polysilicon EG through the CG and CG HM; forming a polysilicon structure over the logic and STI; forming and overfilling with polysilicon a WL trench through the CG and CG HM, between the EG and STI; forming a buffer oxide in the polysilicon structure over the logic region and part of the STI; recessing the buffer oxide and etching back the polysilicon overfill down the CG HM; forming a second buffer oxide over the EG and logic region; recessing the WL polysilicon; removing the first and second buffer oxides; forming a mask with an opening over a center of the WL, the STI, and a majority of the logic region; and removing exposed polysilicon.

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each of the strings of series-connected memory cells is selectively connected to the same data line through a respective plurality of select gates connected in series between that string and the data line. One select gate of each of the pluralities of select gates has a threshold voltage within a first range of threshold voltages, and each remaining select gate of each of the pluralities of select gates has a threshold voltage within a second range of threshold voltages mutually exclusive from the first range of threshold voltages. Each of the select gates having a threshold voltage within the first range of threshold voltages has its control gate isolated from any of the other select gates having a threshold voltage within the first range of threshold voltages.

Abstract: A memory system is configured to store information using a hybrid volatile and nonvolatile memory device. The memory system, in one aspect, includes memory components, a drain select gate (“DSG”) transistor, and a capacitor component. Each memory component, in one example, includes a source terminal, a gate terminal, a drain terminal, and a nonvolatile cell. The memory components are organized in a string formation and the components are interconnected between source terminals and drain terminals. The drain terminal of DSG transistor is coupled to the source terminal of a memory component and the gate terminal of DSG transistor is coupled to a DSG signal. The drain terminal of the capacitor is coupled to the source terminal of the first DSG transistor. The capacitor component is configured to perform a dynamic random-access memory (“DRAM”) function.

Abstract: In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor substrate, a first substrate area in the semiconductor substrate, a first cell unit in the first substrate area, the first cell unit including a first memory cell and a first transistor, and the first transistor having a control terminal connected to a first word line, using the first substrate area as a channel and supplying a read current or a write current to the first memory cell, and a substrate potential setting circuit setting the first substrate area to a first substrate potential when the read current is supplied to the first memory cell, and setting the first substrate area to a second substrate potential different from the first substrate potential when the write current is supplied to the first memory cell.

Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

Abstract: An Ultra Thin Body and Box (UTBB) fully depleted silicon on insulator (FDSOI) field effect transistor (FET) employing a split gate topology is provided. A gate dielectric layer is disposed beneath a gate structure and in contact with a channel layer of the device. The gate dielectric layer contains two portions, a thin portion and a thick portion. The thin portion is arranged and configured to reduce a trans-conductance of the device, while a thick portion is arranged and configured to increase the break down voltage of the device. The device further contains a bulk region that can be electrically connected to voltage source to provide control over the threshold voltage of the device.

Abstract: A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.

Abstract: A split-gate flash memory cell (cell) that can be formed by a method including self-aligned patterning for the select gates includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second FG are on the semiconductor surface. A common source/drain is between the first and second FG. A first select gate and a second select gate are on a select gate dielectric layer that is between a first BL source/drain in the semiconductor surface and the first FG and between a second BL source/drain and the second FG, respectively. The first select gate and the second select gate are spacer-shaped.

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first dielectric layer, a charge trapping layer, a ferroelectric material layer, and a gate layer. The first dielectric layer is disposed on the substrate, the charge trapping layer is disposed on the first dielectric layer, the ferroelectric material layer is disposed on the charge trapping layer, and the gate layer is disposed on the ferroelectric material layer.

Abstract: A semiconductor memory device includes a first floating gate and a second floating gate of conductivity types with different polarities. Injection of electrons into the first floating gate via a tunnel insulating film is stored through a decrease in holes in a valence band of the second floating gate, and ejection of electrons from the first floating gate via the tunnel insulating film is stored through an increase in holes in the valence band of the second floating gate.

Abstract: A reduced size non-volatile memory cell array is achieved by forming first trenches in an insulation layer in the row direction, filling the first trenches with insulation material, forming second trenches in the insulation layer in the column direction, forming the STI isolation material in the second trenches, and forming the source regions through the first trenches. Alternately, the STI isolation regions can be made continuous, and the source diffusion implant has sufficient energy to form continuous source line diffusions that each extend across the active regions and under the STI isolation regions. This allows control gates of adjacent memory cell pairs to be formed closer together.

Abstract: Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region. At least first and second memory cells are formed on the memory cell region. Each of the memory cells is formed by forming a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Re-oxidized layers which extend from top to bottom of the control gate are formed on sidewalls of the control gate. First source/drain (S/D) region is formed adjacent to the second gate and second S/D region is formed adjacent to the first gate. The first and second gates are coupled in series and the second S/D region is a common S/D region for adjacent first and second memory cells. An erase gate is formed over the common S/D region.

Abstract: A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of active layers stacked on the semiconductor substrate, and a gate structure overlapping the plurality of active layers. The gate structure includes a side gate region overlapping sides of the plurality of active layers and a top gate region overlapping a top of an uppermost active layer.

Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor substrate, a first substrate area in the semiconductor substrate, a first cell unit in the first substrate area, the first cell unit including a first memory cell and a first transistor, and the first transistor having a control terminal connected to a first word line, using the first substrate area as a channel and supplying a read current or a write current to the first memory cell, and a substrate potential setting circuit setting the first substrate area to a first substrate potential when the read current is supplied to the first memory cell, and setting the first substrate area to a second substrate potential different from the first substrate potential when the write current is supplied to the first memory cell.

Abstract: Described is a 6T SRAM cell which comprises: a first n-type transistor with a gate terminal coupled to word-line, source/drain terminal coupled to a first bit-line and drain/source terminal coupled to a first node; and a second n-type transistor with a source terminal coupled to a first supply node, a drain terminal coupled to the first node, and a gate terminal for coupling to multiple terminals, wherein the gate terminal includes a capacitor to increase coupling capacitance of the second n-type transistor. Described is a method which comprises: forming a metal gate in a first direction; forming a first spacer in the first direction on one side of the metal gate, the first spacer having a first dimension; and forming a second spacer in the first direction on another side of the metal gate, the second spacer having a second dimension which is substantially different from the first dimension.

Abstract: A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.

Abstract: A memory array provided on a semiconductor substrate includes: (a) channel structures arranged in multiple layers above the semiconductor substrate, each channel structure extending along a first direction substantially parallel a surface of the semiconductor substrate; (b) gate structures each extending along a second direction substantially transverse to the first direction and each being adjacent one of the channel structures, separated therefrom by a layer of memory material; and (c) conductors provided to connect the gate structures with circuitry fabricated in the semiconductor substrate, wherein at each location where one of the gate structure adjacent one of the channel structures, a portion of the gate structure, a portion of the channel structure and the layer of memory material constitute a memory cell of the memory array. Two or more memory cells sharing a channel structure are connected in series to form a NAND string.

Abstract: A semiconductor device includes a gate structure on a substrate; a protection layer on the gate structure; a source/drain region adjacent to the gate structure; and an interconnect plug on the source/drain region. The gate structure includes a gate electrode including a top surface; and a sidewall spacer interfacing a sidewall of the gate electrode. The protection layer covers at least a first portion of the top surface and the sidewall spacer. The protection layer is interposed between the interconnect plug and the gate electrode.

Abstract: A semiconductor memory device includes a plurality of word lines stacked in a first direction; a semiconductor pillar extending through the plurality of word lines in the first direction; a source line electrically connected to the semiconductor pillar; and a transistor arranged in the first direction with the plurality of word lines. The transistor includes a gate electrode, source and drain regions positioned on both sides of the gate electrode respectively. The source line is positioned between the transistor and the plurality of word lines, and is electrically connected to one of the source and drain regions.

Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.

Abstract: Semiconductor devices and methods of forming the same include forming semiconductor fins on a semiconductor substrate. A bottom source/drain region is formed in the semiconductor substrate. First charged dielectric spacers are formed on sidewalls of the semiconductor fins. A gate stack is formed over the bottom source/drain region. Second charged dielectric spacers are formed on sidewalls of the fin above the gate stack. The fins are recessed to a height below a top level of the second charged dielectric spacers. A top source/drain region is grown from the recessed fins.

Abstract: A semiconductor memory device according to an embodiment includes: a pair of insulating members separated from each other, the pair of insulating members extending in a first direction; a plurality of electrode films and a plurality of inter-layer insulating films disposed between the pair of insulating members and stacked alternately along a second direction, the second direction intersecting the first direction; a plurality of semiconductor pillars extending in the second direction and piercing the plurality of electrode films and the plurality of inter-layer insulating films; and a charge storage film disposed between one of the semiconductor pillars and one of the electrode films. An end portion on one of the insulating members side of a first electrode film of the electrode films is thicker than a central portion of the first electrode film between the pair of insulating members.

Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

Abstract: A method of forming a thin film includes forming an interface layer stack on a semiconductor substrate. Forming the interface layer stack may include performing a first surface treatment on the semiconductor substrate under a reducing atmosphere. Forming the interface layer stack may include performing a second surface treatment on the semiconductor substrate. The first surface treatment may be performed under a reducing atmosphere and the second surface treatment may be performed under a nitridation atmosphere. The first surface treatment may include forming a lower interface layer on a surface of the semiconductor substrate and the second surface treatment may include forming an upper interface layer. The first surface treatment may include selectively removing at least one oxide material from a native oxide film on the semiconductor substrate.

Abstract: A method for forming a semiconductor device includes forming a fin extending upwards from a semiconductor substrate and forming a sacrificial layer on sidewalls of a portion of the fin. The method further includes forming a spacer layer over the sacrificial layer and recessing the portion of the fin past a bottom surface of the sacrificial layer. The recessing forms a trench disposed between sidewall portions of the spacer layer. At least a portion of the sacrificial layer is removed, and a source/drain region is formed in the trench.

Abstract: A method includes providing a semiconductor structure having a gate structure arrangement provided over a substrate. The gate structure arrangement includes one or more first gate structures and has a first sidewall and a second sidewall on opposite sides of the gate structure arrangement. A second gate structure is formed including a first portion at the first sidewall, a second portion at the second sidewall and a third portion connecting the first and second portions. Each of the first, second and third portions of the second gate structure includes a first part over the gate structure arrangement and a second part over a portion of the substrate adjacent the gate structure arrangement. After the formation of the second gate structure, one or more sections of the second gate structure are removed, wherein the first and second portions of the second gate structure are separated from each other.

Abstract: A computer-implemented method capable of preparing a design rule indicative of a terminal metal area size of a transistor, minimizing a plasma-induced charging effect to the transistor in a plasma-based process for a dielectric layer performed on a metal layer above the transistor, is provided. The method includes a non-transitory computer readable medium, a design rule generator engine possessing a capability of accurately and swiftly simulating, evaluating and delivering design solutions for interconnect metals and dielectrics while largely saving test chip layout space, and performing the design-for-manufacturing process based on minimized plasma-induced charging effect to the transistor of the integrated circuit design. The disclosed method is applicable to all metal layers in the plasma-based process.

Abstract: Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.

Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.

Abstract: After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a portion of a second semiconductor fin located in a memory device region of the substrate, in which each of the first sacrificial gate stack and the second sacrificial gate stack includes, from bottom to top, a tunneling oxide portion, a floating gate electrode, a control oxide portion, a gate conductor and a gate cap, an entirety of the first sacrificial gate stack is removed to provide a first gate cavity, and only the gate cap and the gate conductor are removed from the second sacrificial gate stack to provide a second gate cavity. Next, a high-k gate dielectric and a gate electrode are formed within each of the first gate cavity and the second gate cavity.

Abstract: An EPROM cell includes a semiconductor substrate, having source and drain regions, a floating gate, including a semiconductive polysilicon layer electrically interconnected with a first metal layer, and a control gate, including a second metal layer. The floating gate is disposed adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, and the second metal layer of the control gate is capacitively coupled to the first metal layer with a second dielectric layer therebetween.

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate; wherein the gate stack includes a high k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer, wherein the gate stack has a convex top surface.