Abstract: A MOSFET structure and a manufacturing method thereof are provided. The structure includes a substrate, a well region of a first conductivity type, a first trench formed on a surface of the well region of the first conductivity type and extending downwards to a well region of a second conductivity type, a source disposed in the well region of the second conductivity type and under the first trench, a gate oxide layer disposed on an inner surface of the first trench, a polysilicon gate disposed on the gate oxide layer, a conductive plug extending downwards from above the first trench and being in contact with the well region of the second conductivity type after extending through the source, an insulation oxide layer filled in the first trench between the conductive plug and the polysilicon gate, and a drain disposed outside the first trench and obliquely above the source.

Abstract: An FET comprises a source, a drain, a channel, and a gate encompassing the channel. The channel has a first region that is thinner than in a second region. The Threshold Voltage, Vth, is larger in the first region than in the second region causing an asymmetric Vth across the length of the channel. Modeling has shown that the Vth increases along the channel from about 50 milliVolts (mV) for N-FETs (about 55 mV for a P-FETs) to about 125 mV for N-FETs (about 180 mV for P-FETs) as the channel width decreases from 4 nanometers (nm) to 2 nm.

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Abstract: A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a P-type doped semiconductor layer above the memory stack, an N-well in the P-type doped semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the P-type doped semiconductor layer, a conductive layer in contact with upper ends of the plurality of channel structures, at least part of which is on the P-type doped semiconductor layer, a first source contact above the memory stack and in contact with the P-type doped semiconductor layer, and a second source contact above the memory stack and in contact with the N-well.

Abstract: A transistor comprises semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section thereby having an elevationally-extending stem and a base extending horizontally from a lateral side of the stem above a bottom of the stem. The semiconductor material of the stem comprises an upper source/drain region and a channel region there-below. The transistor comprises at least one of (a) and (b), where (a): the semiconductor material of the stem comprises a lower source/drain region below the channel region, and (b): the semiconductor material of the base comprises a lower source/drain region. A gate is operatively laterally adjacent the channel region of the stem. Other embodiments are disclosed, including arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor. Methods are disclosed.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor strip over a substrate. The semiconductor strip includes a first semiconductor stack and a second semiconductor stack over the first semiconductor stack. A dummy gate stack is formed to cross the semiconductor strip. The dummy gate stack is replaced with a first metal gate stack and a second metal gate stack. The first metal gate stack is in contact with the first semiconductor layer of the first semiconductor stack and the second metal gate stack is in contact with the first semiconductor layer of the second semiconductor stack.

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, such that the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first part of a terrace region including a set of stepped surfaces which extend in a first horizontal direction, and performing a second set of offset layer patterning processing steps to form a second part of the terrace region and to form a stepped vertical cross-sectional profile for patterned surfaces of the vertically alternating sequence along a second horizontal direction which is perpendicular to the first horizontal direction.

Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

Abstract: A method including forming a first insulating film over a first fin structure. The method further includes removing the first insulating film to expose a portion of the first fin structure. The method further includes forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.

Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion.

Abstract: A method is presented for integrating a resistive random access memory (ReRAM) device with vertical transistors on a single chip. The method includes forming a vertical field effect transistor (FET) including an epitaxial tip defining a drain terminal and forming the ReRAM device in direct contact with the epitaxial tip of the vertical FET such that a current conducting filament is formed at the epitaxial tip due to electric field enhancement.

Abstract: A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.

Abstract: A semiconductor die includes a plurality of alternating stacks of insulating layers and electrically conductive layers that are located over a substrate and that laterally extend along a first horizontal direction and that are laterally spaced apart along a second horizontal direction which is perpendicular to the first horizontal direction, a plurality of sets of memory stack structures extending through the plurality of alternating stacks, and a plurality of nested seal ring structures which include a first seal ring structure comprising having a first seal ring width between an inner sidewall and an outer sidewall thereof, and a second seal ring structure having a second seal ring width between an inner sidewall and an outer sidewall thereof, such that the first seal ring width is less than the second seal ring width.

Abstract: A method for manufacturing a power semiconductor device includes forming a drift region in a substrate, forming a trench in the drift region, forming a gate insulating layer in the trench, depositing a conductive material on the substrate, forming a gate electrode in the trench, forming a body region in the substrate, forming a highly doped source region in the body region, forming an insulating layer that covers the gate electrode, etching the insulating layer to open the body region, implanting a dopant into a portion of the body region to form a highly doped body contact region, so that the highly doped source region and the highly doped body contact region are alternately formed in the body region; and forming a source electrode on the highly doped body contact region and the highly doped source region.

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes the following steps. A fin structure having a base and a plurality of fin portions extending away from the base is provided. A portion of the fin structure in a first region is removed to form a first trench in the base and a first bump formed in the first trench. A first oxide layer is formed in the first region. The first oxide layer is removed.

Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.

Abstract: The invention discloses a NOR-type memory device and a method of fabricating such NOR-type memory device. The NOR-type memory device according to a preferred embodiment of the invention includes a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of multi-layer stripes, a plurality of memory cells, a plurality of first sub-bit lines, a plurality of second sub-bit line, a plurality of word lines, an insulating layer, a plurality of grounded via contacts, and a grounding layer. The first isolation stripes and the second isolation stripes extend in a longitudinal direction defined by the semiconductor substrate. Each memory cell corresponds to one of the columns and one of the rows defined by the semiconductor substrate. The memory cells on one side of each first isolation stripe and the memory cells on the other side of said one first isolation stripe are staggeredly arranged.

Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.

Abstract: A bi-directional semiconductor switching device is formed by forming first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second. FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.

Abstract: Semiconductor devices and methods of forming the same include forming a gate stack over a semiconductor fin. An interlayer dielectric is formed to a height of the gate stack. The interlayer dielectric is etched away in regions outside of junction regions for the semiconductor fin to form first gaps. A dielectric cap is formed over the gate stack and in the first gaps. The remaining interlayer dielectric is etched away to expose a source and drain region of the semiconductor fin. A conductive junction is formed on the semiconductor fin.

Abstract: A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins and silicon-germanium caps from the silicon-germanium cap layer and the substrate, where at least two of the at least four vertical fins is in a first subset and at least two of the at least four vertical fins is in a second subset, forming a silicon-germanium doping layer on the plurality of vertical fins and silicon-germanium caps, removing the silicon-germanium doping layer from the at least two of the at least four vertical fins in the second subset, and removing the silicon-germanium cap from at least one of the at least two vertical fins in the first subset, and at least one of the at least two vertical fins in the second subset.

Abstract: The semiconductor device of the present invention includes a semiconductor layer which includes an active portion and a gate finger portion, an MIS transistor which is formed at the active portion and includes a gate trench as well as a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench at the gate finger portion, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region which is formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.

Abstract: A stack of sacrificial layers is formed in a set of N levels. A first etch-trim mask having spaced apart first and second open etch regions is formed over the set. Two levels are etched through using the first etch-trim mask in each of M etch-trim cycles, where M is (N?1)/2 when N is odd and (N/2)?1 when N is even. One level is etched through using the first etch-trim mask in one etch-trim cycle when N is even. The first etch-trim mask is trimmed to increase the size of the first and second open etch regions, in each of etch-trim cycles C(i) for i going from 1 to T?1, where T is (N?1)/2 when N is odd and N/2 when N is even. A second etch mask is formed over the set, covering one of the open etch regions. One level is etched through using the second etch mask.

Abstract: A semiconductor device for suppressing a variation in characteristics caused by a current flowing at the time of breakdown is disclosed. The first power MOS transistor Q 1 and the column CLM are formed in the first element region FCM defined in the epitaxial layer NEL, and the second power MOS transistor Q 2 is formed in the second element region RCM. The first power MOS transistor Q 1 includes a first trench gate electrode TGE1, and the second power MOS transistor Q 2 includes a second trench gate electrode TGE2. The depth GDP1 of the first trench gate electrode TGE1 is shallower than the depth GDP2 of the second trench gate electrode TGE2.

Abstract: A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.

Abstract: The semiconductor device includes: a first channel pattern including a first horizontal part, vertical parts extending from the first horizontal part, a connection part extending from the first horizontal part in a direction opposite to the vertical parts, and a second horizontal part extending from the connection part in a direction parallel to the first horizontal part; a first gate stack enclosing the vertical parts of the first channel pattern and disposed over the first horizontal part; a well structure disposed under the second horizontal part, and including a first conductivity type impurity; and a first well contact line directly contacting with the second horizontal part and the well structure to couple the second horizontal part of the first channel pattern with the well structure.

Abstract: Provided herein is a method of manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: alternately stacked first material layers and second material layers on a lower structure; forming first holes passing through the first material layers and the second material layers, each of the first holes defining a channel region; removing the second material layers through the first holes such that interlayer spaces between the first material layers are formed; and forming, through the first holes, conductive patterns which fill respective interlayer spaces.

Abstract: A three-dimensional (3D) semiconductor memory device may include a stack structure including gate electrodes sequentially stacked on a substrate, and a vertical channel penetrating the stack structure. The gate electrodes may include a ground selection gate electrode, a cell gate electrode, a string selection gate electrode, and an erase gate electrode, which are sequentially stacked on the substrate.

Abstract: In one embodiment, a method of forming a semiconductor device may include extending a gate conductor of a transistor to overlie a boundary of a well region in which the transistor is formed. The gate conductor may extend to make electrical contact with a gate conductor of a 2nd transistor that is formed external to the well region. A contact conductor may be applied to electrically and physically contact the first and 2nd gate conductors and to also overlie the boundary of the well region.

Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

Abstract: A semiconductor device comprises a first source/drain region arranged on a semiconductor substrate, a second source/drain region arranged on the semiconductor substrate, a bottom spacer arranged on the first source/drain region, and a bottom spacer arranged on the second source/drain region. A first gate stack having a first length is arranged on the first source/drain region. A second gate stack having a second length is arranged on the second source/drain region, the first length is shorter than the second length. A top spacer is arranged on the first gate stack, and a top spacer is arranged on the second gate stack.

Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.

Abstract: An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.

Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin, a gate structure, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin and a second semiconductor fin extend upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The shallow trench isolation (STI) oxide has a horizontal portion extending along a top surface of the substrate and vertical portions extending upwardly from the horizontal portion along the first and second semiconductor fins. The dielectric layer has a horizontal portion extending along a top surface of the horizontal portion of the STI oxide and vertical portions extending upwardly from the horizontal portion of the dielectric layer to a position higher than top ends of the vertical portions of the STI oxide.

Abstract: A semiconductor device structure may include a substrate having a substrate base comprising a first dopant type; a semiconductor layer disposed on a surface of the substrate base, the semiconductor layer comprising a second dopant type and having an upper surface; and a semiconductor plug assembly comprising a semiconductor plug disposed within the semiconductor layer, the semiconductor plug extending from an upper surface of the semiconductor layer and having a depth at least equal to a thickness of the semiconductor layer, the semiconductor plug having a first boundary, the first boundary formed within the semiconductor layer, and having a second boundary, the second boundary formed within the semiconductor layer and disposed opposite the first boundary, wherein the first boundary and second boundary extend perpendicularly to the surface of the substrate base.

Abstract: A transistor device includes at least one transistor cell, having, in a semiconductor body, a source region of a first doping type in a body region of a second doping type, a drain region, and a drift region of the first doping type adjoining the body region and arranged between the body region and the drain region. A low-resistance region of the second doping type in the body region adjoins the source region. A gate electrode dielectrically insulated from the source and body regions by a gate dielectric is arranged above a first surface of the semiconductor body. A length of an overlap between the source region and the gate electrode is larger than 70 nanometers. A doping profile of the low-resistance region along a line that is vertical to the first surface and goes through an edge of the gate electrode has a maximum of higher than 1E19 cm?3.

Abstract: A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.

Abstract: A method of forming a vertical fin field effect transistor device is provided. The method includes forming a vertical fin and fin template on a bottom source/drain layer, wherein the fin template is on the vertical fin. The method further includes forming a gate structure on the vertical fin and fin template, and forming a top spacer layer on the gate structure. The method further includes removing the fin template to form an opening in the top spacer layer, and removing a portion of a gate electrode of the gate structure to form a cavity; and removing a portion of a gate dielectric layer of the gate structure to form a groove around the vertical fin.

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.

Abstract: Disclosed are a switching atomic transistor with a diffusion barrier layer and a method of operating the same. By introducing a diffusion barrier layer in an intermediate layer having a resistance change characteristic, it is possible to minimize variation in the entire number of ions in the intermediate layer involved in operation of the switching atomic transistor or to eliminate the variation to maintain stable operation of the switching atomic transistor. In addition, it is possible to stably implement a multi-level cell of a switching atomic transistor capable of storing more information without increasing the number of memory cells. Also, disclosed are a vertical atomic transistor with a diffusion barrier layer and a method of operating the same. By producing an ion channel layer in a vertical structure, it is possible to significantly increase transistor integration.

Abstract: A method of forming a semiconductor structure includes forming a fin in a film stack disposed over a top surface of a substrate, the film stack comprising a first semiconductor layer, a second semiconductor layer and a channel layer. The method also includes forming an oxide layer disposed over the top surface of the substrate surrounding the fin, the oxide layer covering sidewalls of the first semiconductor layer and the second semiconductor layer, performing a channel release to remove the second semiconductor layer, and performing an oxidation to form a non-uniform thickness of an additional oxide layer along a length of the fin, the non-uniform thickness providing a vertical compressive strain that induces lateral tensile strain in the channel layer. The channel layer comprises an n-type field-effect transistor (NFET) channel.

Abstract: Vertical field effect transistor (VFET) structures and methods of fabrication include a bottom spacer having a uniform thickness. The bottom spacer includes a bilayer portion including a first layer formed of an oxide, for example, and a second layer formed of a nitride, for example, on the first layer, and a monolayer portion of a fourth layer of a nitride for example, immediately adjacent to and intermediate the fin and the bilayer portion.

Abstract: Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less than a second gate length of a second gate in a second vertical fin FET. A difference in gate lengths between different vertical fin FETs can be precisely fabricated by using atomic layer silicon germanium epitaxy. Gate length offset is formed at a bottom source/drain junction region of each vertical fin FET transistor, which allows downstream processing for all vertical fin FET transistors to be the same.

Abstract: A semiconductor device, a method of manufacturing the same and an electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device may include a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence on the substrate, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a channel region close to its peripheral surface and a body region disposed on an inner side of the channel region.

Abstract: A method includes: forming first and second trenches in a semiconductor body; forming a first material layer on the semiconductor body in the first and second trenches such that a first residual trench remains in the first trench and a second residual trench remains in the second trench; removing the first material from the second trench; and forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench. The first material layer includes dopants of a first doping type and the second material layer includes dopants of a second doping type. The method further includes diffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region.

Abstract: A vertical-type nonvolatile memory device is provided in which differences between the sizes of channel holes in which channel structures are formed are reduced. The vertical-type nonvolatile memory device includes a substrate having channel hole recess regions in a surface thereof. Channel structures vertically protrude from the surface of the substrate on ones of the channel hole recess regions, and memory cell stacks including insulating and conductive layers are alternately stacked along sidewalls of the channel structures. A common source line extends along the surface of the substrate on other ones of the channel hole recess regions in a word line recess region, which separates adjacent memory cell stacks. Related fabrication methods are also discussed.