Gate Electrode Self-aligned With Groove Patents (Class 257/332)
  • Patent number: 8633072
    Abstract: Provided is a method of manufacturing a semiconductor device. The method may include etching a first conductive type semiconductor substrate to form a first trench, forming a second trench extending from the first trench, diffusing impurities into inner walls of the second trench to form a second conductive type impurity region surrounding the second trench, forming a floating dielectric layer covering inner walls of the second trench and a floating electrode filling the second trench, and forming a gate dielectric layer covering inner walls of the first trench and a gate electrode filling the first trench.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 21, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Kyoung Il Na
  • Publication number: 20140008721
    Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 9, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Andrea Filippini, Luca Ferrario, Marcello Mariani
  • Patent number: 8618626
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: December 31, 2013
    Assignee: PFC Device Corporation
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Patent number: 8618600
    Abstract: Integrated circuits including a buried wiring lien. One embodiment provides a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate. A gate wiring line may be buried below the main surface and a section of the gate wiring line may form the gate electrode. Above the gate wiring line, a buried contact structure is formed that is adjacent to and in direct contact with the first or a second active area.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: December 31, 2013
    Assignee: Qimonda AG
    Inventor: Stafan Slesazeck
  • Patent number: 8618598
    Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
  • Patent number: 8618594
    Abstract: The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Shinbori, Yoshito Nakazawa
  • Patent number: 8618601
    Abstract: A semiconductor device formed on a semiconductor substrate having a substrate top surface, includes: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region, at least a portion of the source region extending above the dielectric material; a contact trench that allows contact such as electrical contact between the source region and the body region; and a metal layer disposed over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: December 31, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: John Chen
  • Patent number: 8618605
    Abstract: A semiconductor device includes a first gate electrode buried within a semiconductor substrate, a second gate electrode buried within a silicon growth layer disposed on the semiconductor substrate, and a bit line disposed on an interlayer insulating layer disposed on the semiconductor substrate between the first gate electrode and a second gate electrode. Therefore, the number of gates disposed in an active region is increased so that a total memory capacity of the semiconductor device, thereby reducing fabrication cost and improving productivity.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: December 31, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong Won Seo
  • Patent number: 8617953
    Abstract: Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a semiconductor substrate that includes a pair of opposed side walls and a floor extending between the opposed side walls. A dielectric layer may be deposited on the side walls and the floor of the recess. A conductive film may be formed on the dielectric layer and processed to selectively remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: December 31, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8598655
    Abstract: A semiconductor device includes a first transistor with a first drift zone, and a plurality of second transistors, each second transistor comprising a source region, a drain region and a gate electrode. The second transistors are electrically coupled in series to form a series circuit that is electrically coupled to the first transistor, the first and the plurality of second transistors being at least partially disposed in a semiconductor substrate including a buried doped layer, wherein the source or the drain regions of the second transistors are disposed in the buried doped layer.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: December 3, 2013
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Till Schloesser, Rolf Weis, Ralf Rudolf
  • Patent number: 8598623
    Abstract: A termination structure for a semiconductor device includes an array of termination cells formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In other embodiments, semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 3, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Patent number: 8592898
    Abstract: A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The shallow trenches and the deep trenches are parallel to each other. A layer of conductive material is deposited over the first region and a second region of the substrate. The layer of conductive material is etched to define lines separated by gaps over the first region of the substrate, and active device elements over the second region of the substrate. The second region of the substrate is masked and the lines are removed from the first region of the substrate. Elongate trenches are etched where the lines were removed while the second region of the substrate is masked.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8592895
    Abstract: A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: November 26, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hamza Yilmaz, Daniel Calafut, Steven Sapp, Nathan Kraft, Ashok Challa
  • Publication number: 20130307067
    Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.
    Type: Application
    Filed: August 5, 2013
    Publication date: November 21, 2013
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8581314
    Abstract: Provided are semiconductor devices that may include a substrate provided with a transistor, an insulating layer disposed on the substrate, the insulating layer including a contact hole exposing a portion of the transistor, a spacer disposed on an inner sidewall of the contact hole, and a contact plug disposed in the contact hole. Here, a space defined by the spacer may increase in width from a bottom side thereof to a top side thereof.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: November 12, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Jongchul Park, Sangsup Jeong, Byung-Jin Kang
  • Patent number: 8581336
    Abstract: A trench MOSFET rectifier includes oxide layers having different thicknesses formed in different regions of the devices. The rectifying device also includes a source region of first conductivity type at a surface of each mesa region and a body region of a second conductivity type beneath each source region. The rectifying device also includes a dielectric layer lining the bottom and sidewall surfaces of the trenches, the portion of the dielectric layer on the bottom surface being thicker than the portion on the sidewall surface. A doped region underlies each of the first plurality of trenches. A polycrystalline silicon region filling each of the first plurality of trenches to form a gate region in each trench. A conductive material fills a plurality of contact trenches and forms ohmic contacts with the source region, body region, and gate region.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: November 12, 2013
    Inventors: Tao Long, Yiming Wang, Zhongyuan Jin
  • Publication number: 20130292760
    Abstract: The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
  • Patent number: 8575624
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahisa Kanemura, Masaki Kondo
  • Patent number: 8575690
    Abstract: A super-junction trench MOSFET is disclosed for high voltage device by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. Meanwhile, at least one trenched gate and multiple trenched source-body contacts are formed in each unit cell between the pair of deep trenches.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: November 5, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8575613
    Abstract: A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 8564058
    Abstract: A super-junction trench MOSEET is disclosed for high voltage device by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches in each unit cell for super-junction. Meanwhile, at least one trenched gate and multiple trenched source-body contacts are formed in each unit cell between the pair of deep trenches.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: October 22, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8564052
    Abstract: A trench MOSFET comprising a plurality of transistor cells, multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in active area. In some preferred embodiments, the trench MOSFET further comprises a gate metal runner surrounding outside the source metal and extending to the gate metal pad. Furthermore, the termination area further comprises an EPR surrounding outside the trenched floating gates.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: October 22, 2013
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8564060
    Abstract: There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: October 22, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Haruka Shimizu, Natsuki Yokoyama
  • Patent number: 8563390
    Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoungsoo Kim, Yoonkyung Choi, Eun Young Lee, Sungil Jo
  • Patent number: 8564053
    Abstract: A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprise an EPR surrounding outside the multiple trenched floating gates in the termination area.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: October 22, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8564048
    Abstract: Embodiments of the invention relate to field effect transistors. The field effect transistor includes a gate electrode for providing a gate field, a first electrode including a conductive material having a low carrier density and a low density of electronic states, a second electrode, and a semiconductor. Contact barrier modulation includes barrier height lowering of a Schottky contact between the first electrode and the semiconductor. In some embodiments of the invention, a vertical field effect transistor employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: October 22, 2013
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Andrew Gabriel Rinzler, Bo Liu, Mitchell Austin McCarthy, John Robert Reynolds, Franky So
  • Patent number: 8558305
    Abstract: An embodiment of a method for manufacturing a power device integrated on a semiconductor substrate. The method includes photo-lithography and etching of an epitaxial layer for the formation of at least one deep trench; deposition of a dielectric layer with partial filling of the at least one trench; complete filling of the at least one trench with a layer of sacrificial material; selective etching of the dielectric layer with consequent retrocession below the layer of sacrificial material; selective etching of the layer of sacrificial material with consequent formation of an empty region within the at least one trench; and growth of a layer of gate oxide; formation of at least one gate region, of at least one buried source region, of at least one body region and of at least one source region.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: October 15, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventor: Fabio Zara
  • Patent number: 8552492
    Abstract: A trench gate transistor whose gate changes the depth thereof intermittently in the gate width direction, has a first offset region and a second offset region formed below the source and drain, respectively. The sum of length measurements of the underlying portion of the second offset region measured from the lower corner of the trench in a direction parallel to the substrate and in a direction perpendicular to the substrate is 0.1 ?m or greater.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: October 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhiko Sanada, Hiroshi Kawaguchi
  • Patent number: 8552535
    Abstract: A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Peter A. Burke, Brian Pratt, Prasad Venkatraman
  • Patent number: 8546876
    Abstract: A device may include a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may also include another channel, a source disposed near a distal end of a first leg, and a drain disposed near a distal end of a second leg. The column gate may extend between the first leg and the second leg. The channel of the second transistor may be connected to the channel of the first transistor, and the data element may be connected to the source or the drain. Methods, systems, and other devices are contemplated.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: October 1, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8541835
    Abstract: A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Dechao Guo, Marwan H. Khater, Christian Lavoie, Zhen Zhang
  • Patent number: 8541834
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a control electrode, a first main electrode, an internal electrode, and an insulating region. The control electrode is provided inside a trench. The first main electrode is in conduction with the third semiconductor region. The internal electrode is provided in the trench and in conduction with the first main electrode. The insulating region is provided between an inner wall of the trench and the internal electrode. The internal electrode includes a first internal electrode part included in a first region of the trench and a second internal electrode part included in a second region between the first region and the first main electrode. A spacing between the first internal electrode part and the inner wall is wider than a spacing between the second internal electrode part and the inner wall.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuro Nozu
  • Patent number: 8536643
    Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura
  • Patent number: 8530292
    Abstract: A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: September 10, 2013
    Assignees: STMicroelectronics (Grenoble 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Yves Morand, Thierry Poiroux, Jean-Charles Barbe
  • Patent number: 8530312
    Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Filippini, Luca Ferrario, Marcello Mariani
  • Patent number: 8519473
    Abstract: A vertical transistor component is produced by providing a semiconductor body with a first surface and a second surface, producing at least one gate contact electrode in a trench, the trench extending from the first surface through the semiconductor body to the second surface, and producing at least one gate electrode connected to the at least one gate contact electrode in the region of the first surface.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: August 27, 2013
    Assignee: Infineon Technologies AG
    Inventors: Andreas Peter Meiser, Markus Zundel, Christoph Kadow
  • Patent number: 8518777
    Abstract: A method of forming an accumulation-mode field effect transistor includes forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type. The channel region may extend from a top surface of the semiconductor region to a first depth within the semiconductor region. The method also includes forming gate trenches in the semiconductor region. The gate trenches may extend from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth. The method also includes forming a first plurality of silicon regions of a second conductivity type in the semiconductor region such that the first plurality of silicon regions form P-N junctions with the channel region along vertical walls of the first plurality of silicon regions.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: August 27, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Praveen Muraleedharan Shenoy
  • Patent number: 8519477
    Abstract: A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The multiple trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area. The trench MOSFET further comprises at least one trenched channel stop gate around outside of the trenched floating gates and connected to at least one sawing trenched gate extended into scribe line for prevention of leakage path formation between drain and source regions.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 27, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8519456
    Abstract: A solid-state image pickup device in which electric charges accumulated in a photodiode conversion element are transferred to a second diffusion layer through a first diffusion layer.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: August 27, 2013
    Assignee: Sony Corporation
    Inventors: Atsushi Masagaki, Ikuhiro Yamamura
  • Patent number: 8502281
    Abstract: An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Holger Kapels
  • Patent number: 8502306
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and a first semiconductor element provided on the semiconductor substrate. The first semiconductor element includes: a first semiconductor; a second semiconductor layer; a third semiconductor layer; a first insulating layer; a first base region; a first source region; a first gate electrode; a first drift layer; a first drain region; a first source; and a first drain electrode. A concentration of an impurity element of the first conductivity type included in the first drift layer is lower than a concentration of an impurity element of the first conductivity type included in the first semiconductor layer. The concentration of the impurity element of the first conductivity type included in the first drift layer is higher than a concentration of an impurity element of the first conductivity type included in the second semiconductor layer.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuaki Yamaura
  • Patent number: 8497550
    Abstract: A DRAM memory cell includes: a first finFET structure; and a second finFET structure adjacent to the first finFET structure. The second finFET structure includes: a source follower transistor in a first fin of the second finFET structure; an access transistor in a second fin of the second fin FET structure; a write word line; and a read word line stacked above the write word line. When the read word line is fired high, the source follower transistor enables data to be read from the first finFET structure.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: July 30, 2013
    Assignee: Nanya Technology Corp.
    Inventor: Werner Juengling
  • Patent number: 8497551
    Abstract: The process methods and structures mentioned above for creating a trench MOSFET enables self-aligned contacts to be formed to allow decreasing pitch size for trench MOSFET. The self-aligned contacts are formed by etching exposed silicon areas without using lithographical mask and alignment. As a result, the allowance for alignment can be saved and the pitch size can be decreased.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: July 30, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Alex Kalnitsky, Hsiao-Chin Tuan, Kuo-Ming Wu, Wei Tsung Huang
  • Patent number: 8492845
    Abstract: A structure and methods of making the structure. The structure includes: first and a second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the substrate; a first gate electrode extending over the first semiconductor region and the region of the trench isolation; a second gate electrode extending over the second silicon region and the region of the trench isolation; a trench in the trench isolation; and a strap in the trench connecting the first and second gate electrodes.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8492830
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate having a gate groove and first to third grooves, the first to third grooves being formed on a bottom surface of the gate groove and the third groove being formed between the first and second grooves, and a gate electrode having a first gate portion formed in the first groove, a second gate portion formed in the second groove, a third gate portion formed in the third groove, and a fourth gate portion formed in the gate groove. A cell transistor having the gate electrode has a first channel region formed in the semiconductor substrate between the first and third gate portions and a second channel region formed in the semiconductor substrate between the second and third gate portions.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kajiyama
  • Publication number: 20130181284
    Abstract: A method for producing a semiconductor component is described. The method includes providing a semiconductor body having a first surface and being comprised of a first semiconductor material extending to the first surface. At least one trench extends from the first surface into the semiconductor body and includes a gate electrode insulated from the semiconductor body and arranged below the first surface. The method further includes: forming a second insulation layer on the first surface with a recess that overlaps in projection onto the first surface with the conductive region; forming a mask region in the recess; etching the second insulation layer selectively to the mask region and the semiconductor body to expose the semiconductor body at the first surface; depositing a third insulation layer on the first surface; and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the a least one trench is exposed at the first surface.
    Type: Application
    Filed: January 16, 2012
    Publication date: July 18, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Martin Poelzl
  • Patent number: 8487369
    Abstract: A semiconductor device includes: a plurality of first trenches formed inside a plurality of active regions; a plurality of buried gates configured to partially fill insides of the plurality of the first trenches; a plurality of second trenches formed to be extended in a direction crossing the plurality of the buried gates; and a plurality of buried bit lines configured to fill the plurality of the second trenches.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: July 16, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Su-Young Kim
  • Patent number: 8476702
    Abstract: A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: July 2, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Naoki Izumi
  • Patent number: 8476701
    Abstract: A semiconductor device includes a transistor that has a trench formed in an element forming region of a substrate, a gate insulating film formed on side faces and a bottom face of the trench, a gate electrode formed on the gate insulating film so as to bury the trench, a source region formed on one side in the gate longitude direction, which is formed on the surface of the substrate, and a drain region formed on the other side in the gate longitude direction. Here, the gate electrode is formed so as to be exposed also on the substrate outside the trench, and the gate electrode is disposed so as to cover upper portions of both ends of the trench and so as to form at least one concave portion having a depth reaching the substrate in a center portion.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 2, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takehiro Ueda, Hiroshi Kawaguchi
  • Patent number: 8455946
    Abstract: A lateral stack-type super junction power semiconductor device includes a semiconductor substrate; an epitaxial stack structure on the semiconductor substrate, having a first epitaxial layer and a second epitaxial layer; a drain structure embedded in the epitaxial stack structure and extending along a first direction; a plurality of gate structures embedded in the epitaxial stack structure and arranged in a segmental manner along the first direction; a source structure between the plurality of gate structures; and an ion well encompassing the source structure.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: June 4, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang