Abstract: A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.

Abstract: A semiconductor device includes a semiconductor substrate, a first diffusion region, a gate insulating film, a gate electrode, a second diffusion region and a contact plug. The semiconductor substrate includes a base and at least a pillar. The first diffusion region is disposed in the base. The gate insulating film covers a side surface of the pillar. The gate electrode is separated from the pillar by the gate insulating film. The second diffusion region is disposed in an upper portion of the pillar. The contact plug is connected to the second diffusion region. The contact plug is connected to the entirety of the top surface of the pillar.

Abstract: A trench gate transistor whose gate changes depth intermittently in the gate width direction, has a first offset region and a second offset region formed below the source and drain, respectively. The first offset region and the second offset region are shallower where they contact the device isolation film than is the device isolation film in those areas. The first and second offset regions nevertheless extend below the bottom of the trench.

Abstract: The invention provides various embodiments of a memory cell formed on a semiconductor-on-insulator (SeOI) substrate and comprising one or more FET transistors. Each FET transistor has a source region and a drain region at least portions of which are arranged in the thin layer of the SeOI substrate, a channel region in which a trench is made, and a gate region formed in the trench. Specifically, the source, drain and channel regions also have portions which are arranged also beneath the insulating layer of the SeOI substrate; the portion of channel region beneath the insulating layer extends between the portions of the source and drain regions also beneath the insulating layer; and the trench in the channel region extends into the depth of the base substrate beyond the insulating layer. Also, methods for fabricating such memory cells and memory arrays including a plurality of such memory cells.

Abstract: An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region.

Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.

Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

Abstract: A semiconductor memory device includes a plurality of active pillars protruding from a semiconductor substrate, a first gate electrode disposed on at least one sidewall of the active pillar, a first gate insulating layer being disposed between the active pillar and the first gate electrode, a second gate electrode disposed on at least one sidewall of the active pillar over the first gate electrode, a second gate insulating layer being disposed between the active pillar and the second gate electrode, first and second body regions in the active pillar adjacent to respective first and second respective electrodes, and first through third source/drain regions in the active pillar arranged alternately with the first and second body regions.

Abstract: A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

Abstract: A first semiconductor element portion for switching a first current includes a first channel surface having a first plane orientation. A first region of a semiconductor layer includes a first trench having the first channel surface. A first gate insulating film covers the first channel surface with a first thickness. A second semiconductor element portion for switching a second current smaller than the first current includes a second channel surface having a second plane orientation different from the first plane orientation. A second region of the semiconductor layer includes a second trench having the second channel surface. A second gate insulating film covers the second channel surface with a second thickness larger than the first thickness.

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract: A method for fabricating a semiconductor apparatus including a buried gate removes factors deteriorating the operational reliability of the semiconductor device such as the electrical connection between a contact and a word line, and increases a processing margin when forming the contact disposed on a source/drain region. The method includes forming a recess in a semiconductor substrate, forming a gate in a lower portion of the recess, forming a first insulation layer over the gate, growing silicon over the first insulation layer in the recess, and depositing a second insulation layer over the semiconductor substrate and in the remaining portion of the recess.

Abstract: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.

Abstract: A semiconductor component includes at least one field effect transistor disposed along a trench in a semiconductor region and has at least one locally delimited dopant region in the semiconductor region. The at least one locally delimited dopant region extends from or over a pn junction between the source region and the body region of the transistor or between the drain region and the body region of the transistor into the body region as far as the gate electrode, such that a gap between the pn junction and the gate electrode in the body region is bridged by the locally delimited dopant region.

Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

Abstract: There is embodied a high-reliability high-voltage resistance compound semiconductor device capable of improving the speed of device operation, being high in avalanche resistance, being resistant to surges, eliminating the need to connect any external diodes when applied to, for example, an inverter circuit, and achieving stable operation even if holes are produced, in addition to alleviating the concentration of electric fields on a gate electrode and thereby realizing a further improvement in voltage resistance. A gate electrode is formed so as to fill an electrode recess formed in a structure of stacked compound semiconductors with an electrode material through a gate insulation film, and a field plate recess formed in the structure of stacked compound semiconductors is filled with a p-type semiconductor, thereby forming a field plate the p-type semiconductor layer of which has contact with the structure of stacked compound semiconductors.

Abstract: A semiconductor structure comprises a drift region of a first conductivity type in a semiconductor region. A well region of a second conductivity type is over the drift region. A source region of the first conductivity type is in an upper portion of the well region. A heavy body region of the second conductivity type extends in the well region. The heavy body region has a higher doping concentration than the well region. A first diffusion barrier region at least partially surrounds the heavy body region. A gate electrode is insulated from the semiconductor region by a gate dielectric.

Abstract: A semiconductor device includes a drain region comprising an epitaxial layer, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, and an active region contact electrode disposed within the active region contact trench. The active region contact trench has a first width associated with a first region that is in proximity to a bottom portion of the body and a second width associated with a second region that is in proximity to a bottom portion of the source. The first width is substantially different from the second width.

Abstract: A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate.

Abstract: A semiconductor structure has a substrate with a first main surface and a second main surface, the substrate comprising a gate electrode region, a channel region, wherein a conductive channel can be generated, and a gate electrode insulation between the gate electrode region and the channel region. Further, a field electrode region with a curved external surface is provided for increasing a breakdown voltage of the semiconductor structure, wherein the field electrode region has an extension in every direction in parallel to the first main surface, which is lower than a maximum extension in the one direction perpendicular to the second main surface.

Abstract: A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a stripe shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 ?m or more.

Abstract: A power MOSFET is described. A trench is in a body layer and an epitaxial layer. An isolation structure is on the substrate at one side of the trench. An oxide layer is on the surface of the trench. A first conductive layer fills the trench and extends to the isolation structure. A dielectric layer is on the first conductive layer and isolation structure and has an opening exposing the first conductive layer. At least one source region is in the body layer at the other side of the trench. A second conductive layer is on the dielectric layer and electrically connected to the source region while electrically isolated from the first conductive layer by the dielectric layer. A third conductive layer is on the dielectric layer and electrically connected to the first conductive layer through the opening of the dielectric layer. The second and third conductive layers are separated.

Abstract: This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first active pillars by etching a substrate using a hard mask layer as an etching barrier, forming a gate conductive layer surrounding sidewalls of the first active pillars and the hard mask layer, forming a word line conductive layer filling gaps defined by the gate conductive layer, forming word lines and vertical gates by simultaneously removing portions of the word line conductive layer and the gate conductive layer on the sidewalls of the hard mask layer, forming an inter-layer dielectric layer filling gaps formed by removing the word line conductive layer and the gate conductive layer, exposing surfaces of the first active pillars by removing the hard mask layer, and growing second active pillars over the first active pillars.

Abstract: A power semiconductor device having a self-aligned structure and super pinch-off regions is disclosed. The on-resistance is reduced by forming a short channel without having punch-through issue. The on-resistance is further reduced by forming an on-resistance reduction implanted drift region between adjacent shield electrodes, having doping concentration heavier than epitaxial layer without degrading breakdown voltage with a thick oxide on bottom and sidewalls of the shield electrode. Furthermore, the present invention enhance the switching speed comparing to the prior art.

Abstract: A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.

Abstract: A semiconductor device includes a first conductive type semiconductor substrate; a first conductive type semiconductor region provided thereon in which first conductive type first pillar regions and second conductive type second pillar regions alternately arranged; second conductive type second semiconductor regions provided on second pillar regions in an element region to be in contact with first pillar regions therein; gate electrodes each provided on adjacent second semiconductor regions and on one of the first pillar region interposed therebetween; third semiconductor regions functioning as a first conductive type source region provided in parts of the second semiconductor regions located under side portions of the gate electrodes; and a second conductive type resurf region which is a part of a terminal region surrounding the element region and which is provided on first pillar regions and second pillar regions in the part of the terminal regions.

Abstract: Provided is a semiconductor device which can relax the electric field in the junction termination region, and can achieve a high breakdown voltage. The semiconductor device includes an element region (51) and a junction termination region (52). The element region includes: a first semiconductor region (2) of a first conductivity type; a second semiconductor region (4) of a second conductivity type; a third semiconductor region (10) of the first conductivity type; a trench (35) passing through the second semiconductor region and the third semiconductor region and has a bottom surface which reaches the first semiconductor region (2); a gate insulating film (12) formed on the side surface and a bottom surface of the trench; and a gate electrode (8) embedded in the trench.

Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.

Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.

Abstract: The trench type semiconductor device includes a gate insulating film placed on the bottom surface and the sidewall surface of the trench formed from the surface of a first base layer; a gate electrode placed on the gate insulating film and fills up into a trench; an interlayer insulating film covering the gate electrode; a second base layer placed on the surface of the first base layer, and is formed more shallowly than the bottom surface of the trench; a source layer placed on the surface of the second base layer; a source electrode connected to the second base layer in the bottom surface of a self-aligned contact trench formed in the second base layer by applying the interlayer insulating film as a mask, and is connected to the source layer in the sidewall surface; a drain layer placed at the back side of the first base layer; and a drain electrode placed at the drain layer, for achieving the minute structure by the self-alignment, reducing the on resistance, and improving the breakdown capability, and prov

Abstract: A power supply circuit includes first and second switching MOSFETS. A semiconductor device, including the second switching MOSFET, has a plurality of transistor cell regions disposed in a semiconductor substrate. A source electrode of the second MOSFET is disposed over a main surface of the semiconductor substrate and is in contact with a top surface of a source region in each of the plurality of transistor cell regions. A drain electrode of the second MOSFET is disposed over a back surface of the semiconductor substrate and is electrically connected to the semiconductor substrate. A Schottky cell region is disposed between the plurality of transistor cell regions in the semiconductor substrate. The source electrode is in contact with a part of the main surface of the semiconductor so as to form a Schottky junction in the Schottky cell region.

Abstract: A planar double-gate transistor is manufactured wherein crystallisation inhibitors are implanted into the channel region (16) of a semiconductor wafer (10), said wafer having a laminate structure comprising an initial crystalline semiconductor layer (14) adjacent an amorphous semiconductor layer (12). Upon heating, partial re-growth of the amorphous semiconductor layer is restricted in the channel area thus allowing for the thickness of the source/drain extension regions to be increased whilst maintaining a thin channel. Any remaining amorphous material is selectively removed leaving a cavity to allow for the forming of gate electrodes (30,32) on opposing sides of the channel region. The invention can be exploited to a greater extent by providing an amorphous layer on both sides of the initial crystalline semiconductor layer thus providing for re-growth limitation in two directions.

Abstract: A semiconductor device comprises an insulated gate field effect transistor and a protection diode. The insulated gate field effect transistor has a gate electrode formed on a gate insulating film, a source and a drain. The source and the drain are formed in a first area of a semiconductor substrate. A first silicon oxide film is formed on a second area of the semiconductor substrate adjacent to the first area. The first silicon oxide film is thicker than the gate insulating film and contains larger amount of impurities than the gate insulating film. A poly-silicon layer is formed on the first silicon oxide film. The protection diode has a plurality of PN-junctions formed in the poly-silicon layer. The protection diode is connected between the gate electrode and the source so as to prevent breakdown of the gate insulating film.

Abstract: A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease.

Abstract: Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET 1203. A switching node metal layer couples the drain of the source-side-gate TMOSFET to the source of the drain-side-gate TMOSFET so that the TMOSFETs are packaged as a stacked or lateral device.

Abstract: A field effect transistor (FET) includes a plurality of trenches extending into a silicon layer, each trench having upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches. Source regions that are self-aligned to corresponding trenches extend in the body regions adjacent opposing sidewalls of each trench, and have a conductivity type opposite that of the body regions.

Abstract: A semiconductor device includes: a semiconductor layer; a first conductivity type region of a first conductivity type formed in a base layer portion of the semiconductor layer; a body region of a second conductivity type formed in the semiconductor layer to be in contact with the first conductivity type region; a trench formed by digging the semiconductor layer from the surface thereof to pass through the body region so that the deepest portion thereof reaches the first conductivity type region; a gate insulating film formed on the bottom surface and the side surface of the trench; a gate electrode buried in the trench through the gate insulating film; a source region of the first conductivity type formed in a surface layer portion of the semiconductor layer on a side in a direction orthogonal to the gate width with respect to the trench to be in contact with the body region; and a high-concentration region of the second conductivity type, formed in the body region on a position opposed to the trench in the d

Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of the surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: A semiconductor power device includes a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate, and a plurality of stripe-shaped sinker trenches each extending between two adjacent groups of the plurality of groups of stripe-shaped gate trenches. The plurality of stripe-shaped sinker trenches extend from a top surface of the silicon region through the silicon region and terminate within the substrate. The plurality of stripe-shaped sinker trenches are lined with an insulator along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.

Abstract: To realize forming a trench MOSFET in which a depth of a P-body is changed on the same surface as a CMOS by employing steps with good controllability and without greatly increasing the number of manufacturing steps, provided is a trench MOSFET including an extended body region (10), which is a part of a P-body region (4) and is provided in a vicinity of a deep trench (5) with a distance, the extended body region (10) being diffused deeper than the P-body region (4).

Abstract: Provided is a self aligned filed effect transistor structure. The self aligned field effect transistor structure includes: an active region on a substrate; a U-shaped gate insulation pattern on the active region; and a gate electrode self-aligned by the gate insulation pattern and disposed in an inner space of the gate insulation pattern.

Abstract: A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type recess gate formed in each gate forming area of the active region and having the shape of a bulb on the lower end portion of the sidewall thereof facing the source forming area; and source and drain areas respectively formed on the surface of the substrate on both sides of the asymmetric bulb-type recess gate.

Abstract: A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.

Abstract: A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed.

Abstract: A gate of a trench type MOSFET device and a method of forming a gate. A gate of a trench type MOSFET device may include a gate oxide film formed on and/or over a trench type gate poly such that parasitic capacitance may be produced in a gate poly. An electric field may be substantially uniformly formed in a MESA region surrounding a gate poly. An overcurrent may be substantially prevented from flowing into a MOS channel around a gate. A gate oxide film may be substantially prevented from being destroyed and/or leakage may be substantially prevented. Reliability of a device may be maximized.

Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.

Abstract: An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer.