Abstract: A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating the metal catalyst layer, and using a vapor deposition process to deposit a copper seed layer onto the metal catalyst layer. The vapor deposition process may include PVD, CVD, or ALD. An electroplating process or an electroless plating process may then be used to deposit a bulk copper layer onto the copper seed layer to fill the trench. A planarization process may follow to form the final interconnect structure.

Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.

Abstract: A semiconductor device includes a first semiconductor layer that is formed on a first insulating layer; a second insulating layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the second insulating layer; a first gate electrode that is formed on the second semiconductor layer; first conductive-source and drain layers that are formed in the second semiconductor layer and are arranged at sides of the gate electrode; and a first wiring layer that connects the first gate electrode to the first semiconductor layer.

Abstract: Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.

Abstract: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.

Abstract: A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created in the epitaxial silicon layer at the bottom of the central shallow trench. First and third doped layers are created in the epitaxial silicon layer adjacent to the central shallow trench. An oxide layer is then deposited to fill the three trenches. The second doped layer is diffused vertically down to the substrate. The first and third doped layers are diffused vertically down to the second doped layer. Lateral diffusion of the first and third doped layers is constrained by the oxide layer in the three trenches.

Abstract: A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.

Abstract: A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region having a second stress different than the first stress is also located in the isolation trench. The first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa.

Abstract: A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

Abstract: The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends between the first STI region and the collection region and undercuts a portion of the active base region with an undercut angle of not more than about 90°. For example, the second STI region may a substantially triangular cross-section with an undercut angle of less than about 90°, or a substantially rectangular cross-section with an undercut angle of about 90°. Such a second STI region can be fabricated using a porous surface section formed in an upper surface of the collector region.

Abstract: According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.

Abstract: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.

Abstract: The distance between a substrate contact portion and an active region in a p-type MIS transistor is greater than the distance between a substrate contact portion and an active region in an n-type MIS transistor. Alternatively, the length of a protruding part of a gate electrode of the p-type MIS transistor that protrudes from the p-type MIS transistor's active region toward the p-type MIS transistor's substrate contact portion is shorter than the length of a protruding part of a gate electrode of the n-type MIS transistor that protrudes from the n-type MIS transistor's active region toward the n-type MIS transistor's substrate contact portion. Alternatively, a part of the p-type MIS transistor's substrate contact portion that is located opposite the p-type MIS transistor's gate electrode has a lower impurity concentration than the other part thereof.

Abstract: A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that includes a constricted current passage between the gate and the source/drain region.

Abstract: A metal-oxide-semiconductor transistor device comprises a semiconductor substrate comprising an active region and an insulation region, a selective epitaxial layer between the active region and a gate structure, wherein a peripheral portion of the epitaxial layer is over a peripheral portion of the insulation region, such that the width of the channel is increased and a drain current is improved.

Abstract: A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surfaces thereof, and includes a conductive fill material therein. Bottom portions of the pair of deep trenches are merged with one another so as to provide an electrically conductive path therethrough.

Abstract: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.

Abstract: The semiconductor device whose yield and reliability improved, and its manufacturing method are offered. A resist layer is formed so that the silicon nitride film and filling insulating film in region A may be covered. Then, in order to adjust the height position of the upper surface of a filling insulating film, a plasma etch back or fluoric acid is performed. Thereby, the filling insulating film on the silicon nitride film in region B is removed. Therefore, the problem that the residue of a filling insulating film remains on the silicon nitride film in region B is solved.

Abstract: A semiconductor device includes: a P-type semiconductor layer formed in a surface region of a semiconductor substrate; a first gate insulating film formed on the P-type semiconductor layer; a first gate electrode; and a first source region and a first drain region formed in the P-type semiconductor layer to interpose a region under the first gate electrode in a direction of gate length. The first gate electrode includes: a first silicide film formed on the first gate insulating film and containing nickel silicide having a first composition ratio of nickel to silicon as a main component; a conductive film formed on the first silicide film; and a second silicide film formed on the conductive film and containing nickel silicide having a second composition ratio of nickel to silicon as a main component. The second composition ratio is larger than the first composition ratio.

Abstract: In one embodiment, a semiconductor device is formed having charge compensation trenches in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.

Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.

Abstract: A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.

Abstract: Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

Abstract: A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.

Abstract: A capacitance device includes a dielectric film, the first electrode and the second electrode. One of the two electrodes is divided into a plurality of electrode portions. Each of the divided electrode portions is connected with each other through switching transistors so that appropriate portions contributing to the capacitance can be selected. The device can vary its capacitance with high accuracy.

Abstract: A pixel cell having a halogen-rich region localized between an oxide isolation region and a photosensor. The halogen-rich region prevents leakage from the isolation region into the photosensor, thereby suppressing dark current in imagers.

Abstract: A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.

Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or different crystal orientations. The present integrated circuit is made by forming a substrate with SOI and bulk regions separated by an embedded sidewall spacer (made of dielectric). The sidewall spacer is etched, forming a trench that is subsequently filled with epitaxial material. After planarizing, the substrate has SOI and bulk regions with a continuous semiconductor surface. A butted P-N junction and silicide layer can provide electrical connection between the SOI and bulk regions.

Abstract: The invention includes methods in which common processing steps are utilized during fabrication of components of a memory array region of a semiconductor substrate and components of a peripheral region proximate the memory array region, and yet the components of the peripheral region are built for different performance characteristics than the components of the memory array region. The methods can include laterally recessing nitride-containing masking structures associated with the peripheral region to a greater extent than nitride-containing masking structures associated with the memory array region, followed by thermal oxidation of the substrate to form dielectric material adjacent the masking structures.

Abstract: A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densificiation of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.

Abstract: An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.

Abstract: In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a bottom portion and first and second trench sidewalls. At least one trench sidewall is adjacent a doped region. The at least one sidewall adjacent a doped region has a higher impurity dopant concentration than impurity doped regions surrounding the at least one trench isolation region.

Abstract: A semiconductor device includes a silicon substrate, a strain-inducing layer, a silicon layer, a FET, and an isolation region. On the silicon substrate, the strain-inducing layer is provided. On the strain-inducing layer, the silicon layer is provided. The strain-inducing layer induces lattice strain in a channel region of the FET in the silicon layer. The silicon layer includes the FET. The FET includes a source/drain region, an SD extension region, a gate electrode and a sidewall. The source/drain region and the strain-inducing layer are spaced from each other. Around the FET, the isolation region is provided. The isolation region penetrates the silicon layer so as to reach the strain-inducing layer.

Abstract: A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

Abstract: The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine dopant, a germanium dopant, or a phosphorous dopant. The low compressive stress STI films will generally exhibit a compressive stress of less than 180 MPa, and preferably less than about 170 MPa. In certain embodiment, the STI films of the invention will exhibit a compressive stress less than about 100 MPa. Further, in certain embodiments, the low compressive stress STI films of the invention will comprise between about 0.1 and 25 atomic % of the stress-lowering dopant.

Abstract: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device. In embodiments, a transistor including the gate electrode and a source/drain may be formed between isolation layers and a contact may be connected to the source/drain. A barrier layer may be formed at a boundary between the isolation layer and the source/drain and may physically isolate the isolation layer from the source/drain.

Abstract: Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the heavily doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

Abstract: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Abstract: A semiconductor device (101) is provided herein which comprises a substrate (103) comprising germanium. The substrate has source (107) and drain (109) regions defined therein. A barrier layer (111) comprising a first material that has a higher bandgap (Eg) than germanium is disposed at the boundary of at least one of said source and drain regions. At least one of the source and drain regions comprises germanium.

Abstract: A pad oxide film and a silicon nitride film are formed on a semiconductor substrate. Next, after the patterning of the silicon nitride film, by etching the pad oxide film and the substrate, a first trench is formed in a first region and a second trench is formed in a second region. After that, by performing side etching of the pad oxide film of the first region while protecting the second region with a resist, a gap is formed between the substrate and the silicon nitride film. Subsequently, the inner surfaces of the first and second trenches are oxidized. At this time, a relatively large volume of oxidizing agent (oxygen) is supplied to a top edge portion of the first trench, and the curvature of the corner of the substrate increases.

Abstract: A method for forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate adjacent the gate. A facet is formed in at least one of the source/drain junctions of the integrated circuit.

Abstract: There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.

Abstract: A semiconductor device has p-channel field effect transistors disposed in a lattice shape. In order to generate compression stress in the channel of a p-channel field effect transistor, a long active region of a plurality of transistors is divided for each gate electrode and a sufficiently thin shallow trench isolation (STI) is formed between adjacent gate electrodes. The drain current characteristics can be improved.

Abstract: A MOS image pick-up device including a semiconductor substrate, an imaging region formed on the semiconductor substrate by arraying plural unit pixels, and a peripheral circuit region including a driving circuit for operating the imaging region formed on the semiconductor substrate; the unit pixels include a photodiode, MOS (metal-oxide-semiconductor) transistors and a first device-isolation portion, the peripheral circuit region includes a second device-isolation portion for isolating devices in the driving circuit; wherein each of the first device-isolation portion and the second device-isolation portion is at least one portion selected from an electrically insulating film formed on the substrate in order not to erode the substrate, a electrically insulating film formed on the substrate so as to erode the substrate to a depth ranging from 1 nm to 50 nm, and an impurity diffusion region formed within the substrate. The MOS image pick-up device is incorporated in a camera.

Abstract: A MOSFET transistor structure is formed in a substrate of semiconductor material having a first conductivity type. The MOSFET transistor structure includes an active region that is surrounded by a perimeter isolation dielectric material formed in the substrate to define a continuous sidewall interface between the sidewall dielectric material and the active region. Spaced-apart source and drain regions are formed in the active region and are also spaced-apart from the sidewall interface. A conductive gate electrode that is separated from the substrate channel region by intervening gate dielectric material includes a first portion that extends over the substrate channel region and a second portion that extends continuously over the entire sidewall interface between the isolation dielectric material and the active region.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.