Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: A semiconductor device disclosed herein comprises: an element isolation insulator which is formed on the surface side of a semiconductor substrate to provide electrical insulation from other elements, a height of a surface of the element isolation insulator being equal to or lower than that of a surface of the semiconductor substrate; a stopper which is formed of a material different from that of the element isolation insulator and which is at a predetermined distance from the semiconductor substrate so as to protrude from the surface of the element isolation insulator; and an elevated source/drain which is formed on a source region and a drain region so as to be elevated from the surface of the semiconductor substrate.

Abstract: A method of improving transistor carrier mobility by adjusting stress through recessing shallow trench isolation is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide layer is formed on the source/drain region. A recess is formed by etching the dielectric so that the surface of the dielectric is substantially lower than the surface of the substrate. Recessing the STI removes the compressive stress applied to the channel region by the STI material. A contact etch stop layer (CESL) is formed over the gate electrode, spacers, source/drain regions and the dielectric. The CESL applies a desired stress to the channel region. Trench liners are optionally formed to provide a stress to the channel region. A spacer can optionally be formed in the STI recess.

Abstract: An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Abstract: Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

Abstract: A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are laminated in this order. The element isolation structure is composed of a trench, a semiconductor film, and first and second insulating films. The trench extends through the semiconductor layer and extends to the inside of the compound semiconductor layer. The semiconductor film is provided on the surface of the trench, and the first insulating film is provided on the semiconductor film. The second insulting film is provided on the first insulating film and fills the trench.

Abstract: A method for manufacturing a metal-oxide-semiconductor transistor prevents the occurrence of a contact spiking phenomenon. The method includes forming a metal thin film and an isolation oxidation film on a semiconductor substrate, and selectively etching the isolation oxidation film such that the isolation oxidation film is left remaining only over a field oxidation film; heat treating the semiconductor substrate to form silicide by the metal thin film in gate, source, and drain regions; removing portions of the metal thin film that is not formed into silicide, that is, removing unreacted metal thin film; removing the isolation oxidation film left remaining on the field oxidation film; and heat treating the semiconductor substrate in an oxygen environment to form the unreacted metal thin film remaining on the field oxidation film into a metal oxidation film. The present invention is related also to a semiconductor device that employs a metal-oxide-semiconductor transistor made using the method.

Abstract: A semiconductor device including a source region and a drain region spaced from each other by a predetermined interval and formed on a main surface of a semiconductor substrate. A gate electrode is formed on the semiconductor substrate. A trench is filled with insulation material and formed in the main surface of the semiconductor substrate between a location under the gate electrode and at least one of the source region and the drain region with a predetermined depth. An LDD is formed along the trench and has an impurity concentration that is lower than that of the source region and the drain region.

Abstract: A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

Abstract: A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO2 interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si—SiO2 interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.

Abstract: Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposited thereon, defines the process stack. The dopant is selected having the same n- or p-typing as the substrate. Through etching, the first and second layers of the process stack become pulled back from a trench wall of the substrate to form the implant region. Occupation of the implant region by the dopant prevents undesirable transistor leakage because the electrical characteristics of the implant region are so significantly changed, in comparison to central areas of the substrate underneath the first layer, that the threshold voltage of the implant region is raised to be about equivalent to or greater than the substantially uniform threshold voltage in the central area.

Abstract: The present invention provides a SiGe-based bulk integration scheme for generating FinFET devices on a bulk Si substrate in which a simple etch, mask, ion implant set of sequences have been added to accomplish good junction isolation while maintaining the low capacitance benefits of FinFETs. The method of the present invention includes providing a structure including a bottom Si layer and a patterned stack comprising a SiGe layer and a top Si layer on the bottom Si layer; forming a well region and isolation regions via implantation within the bottom Si layer; forming an undercut region beneath the top Si layer by etching back the SiGe layer; and filling the undercut with a dielectric to provide device isolation, wherein the dielectric has an outer vertical edge that is aligned to an outer vertical edge of the top Si layer.

Abstract: Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.

Abstract: A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semico

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract: A method of forming an oxide region in a semiconductor device includes the steps of forming a plurality of trenches in a semiconductor layer of the device, the trenches being formed in close relative proximity to one another, and oxidizing the semiconductor layer such that an insulating layer is formed on at least sidewalls and bottom walls of the trenches. The trenches are configured such that the insulating layer formed as a result of the oxidizing step substantially fills the trenches and substantially consumes the semiconductor layer between corresponding pairs of adjacent trenches. In this manner, a substantially continuous oxide region is formed throughout the plurality of trenches.

Abstract: A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

Abstract: A memory device is provided. The memory device comprises a substrate, first isolation structures, stacked device structures, and second isolation structures. The substrate comprises a memory cell area and a periphery area having trenches therein. Each stacked device structure is disposed between two neighboring trenches over the substrate. The stacked device structure comprises a gate dielectric layer and a gate layer. The gate dielectric layer covers part of the substrate. The second isolation structures are disposed between neighboring stacked device structures. The second isolation structure comprises a liner and an isolation layer. The liner is disposed on the sidewalls of the gate dielectric layer, the surface of the trenches, and the surface of the substrate not covered by the dielectric layer. The liner over the surface of the substrate not covered by the dielectric layer has a round curve. The isolation layer covers the liner, and fills the trenches.

Abstract: A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal ring region about a periphery of an integrated circuit region. In one embodiment, the substrate contact includes a contact trench extending through a shallow trench isolation region and an insulator overlying the semiconductor substrate and outside the integrated circuit region. The contact trench is substantially filled with a conductive material thereby allowing the semiconductor substrate to be electrically connected with a metal interconnect within the seal ring region.

Abstract: A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the substrate, to provide a layer offset (28) between the driver device area and power device area. An epi region of uniform thickness is formed over the driver device and power device areas. A portion of the epi layer is removed to provide another layer offset (70). An oxide layer (68) of uniform thickness is formed over the epi region. The oxide layer is planarized to remove oxide layer over the N+ layer. An oxide-filled trench (80) is formed between the driver device and the power device. The oxide-filled trench extends down to the oxide layer to isolate the driver device from the power device.

Abstract: A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The first and third transistors share a common n-type channel MOS region and the second and fourth transistors share a common p-type channel MOS region. The semiconductor device has a wire connecting the n-type channel MOS region and the p-type channel MOS region. The wire has a width greater than a distance between the first and second adjacent gate electrodes, and a portion of the wire is disposed right above a portion of at least one of the first and second gate electrodes with an insulating film interposed therebetween.

Abstract: To reduce the on-resistance in a semiconductor device, such as a trench lateral power MOSFET, a trench etching region forms a mesh pattern in which a first trench section, formed in an active region, and a second trench section, formed in a gate region for leading out gate polysilicon to a substrate surface, intersect each other. An island-like non-trench region, which is left without being subjected to etching, is divided into a plurality of smaller regions by one or more third trench section that connect with the first and second trench sections that form the mesh pattern. In each non-trench region, a contact section for connecting a drain region (or a source region) and an electrode is formed so as to be spread over all of the smaller regions in the non-trench region.

Abstract: An inventive method for fabricating a semiconductor device includes the steps of: a) forming trenches in an actual element region and a dummy pattern region of a substrate by using a mask; b) depositing an insulator over the substrate, thereby forming an insulating film that fills at least the trenches; and c) removing a portion of the insulating film protruded from the trenches, thereby forming, in the trenches within the actual element region, a first embedded insulating film for isolation, and forming a second embedded insulating film in the trenches within the dummy pattern region. The dummy pattern region has dummy patterns in which no trenches are formed, and the widthwise size of each dummy pattern is four times or less of the depth of a portion of each trench provided in the substrate.

Abstract: A semiconductor device with p-channel MOS transistor having: a gate insulating film of nitrogen-containing silicon oxide; a gate electrode of boron-containing silicon; side wall spacers on side walls of the gate electrode, comprising silicon oxide; an interlayer insulating film having a planarized surface; a wiring trench and a contact via hole formed in the interlayer insulating film; a copper wiring pattern including an underlying barrier layer and an upper level copper region, and filled in the wiring trench; and a silicon carbide layer covering the copper wiring pattern. A semiconductor device has the transistor structure capable of suppressing NBTI deterioration.

Abstract: A semiconductor memory device provides non-volatile memory with a memory array having an alternating Vss interconnection. Using the alternating Vss interconnection, a low implant dosage is added to a region proximate to the lower areas of an STI region, such as beneath the STI region, to ameliorate the problem of low Vss conductivity by providing an adequate number of multiple current paths over several Vss lines. However, non-adjacent STI regions, rather than adjacent STI region, receive the implant. Alternating Vss lines are interconnected by thus implanting under every other STI region. This alternating Vss interconnection imparts an adequately high Vss conductivity, yet without diffusion areas merging to isolate the associated memory device or contaminating the drains and maintains scalability.

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.

Abstract: On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain field limiting layer and a source/drain region are formed. The one and another MOS transistors are connected in series through the source/drain region common to the two transistors. Accordingly, a semiconductor device can be provided in which increase in pattern layout area is suppressed when elements including a high-breakdown voltage MOS transistor are to be connected in series.

Abstract: A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.

Abstract: A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.

Abstract: A method for making an integrated circuit includes forming spaced-apart trenches on a surface of a single crystal silicon substrate, lining the trenches with a silicon oxide layer, forming a first polysilicon layer over the silicon oxide layer, forming a second polysilicon layer over the first polysilicon layer, and removing a thickness of the single crystal silicon substrate to expose tubs of single crystal silicon in the second polysilicon layer.

Abstract: A semiconductor device comprising a buried insulating film formed in a substrate; a protective film formed on the buried insulating film covering corresponding diffusion regions of a P-type MISFET and a N-type MISFET, wherein the protective film is etch resistant to a hydrofluoric acid based solution; and a wiring layer formed on the protective film and being electrically connecting the diffusion regions of the P-type MISFET and the N-type MISFET.

Abstract: An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.

Abstract: A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.

Abstract: Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.

Abstract: A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.

Abstract: There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (11), trilayer well regions (12, 14, 16; 13, 15, 16) are formed, and DTMOS' (29, 30) and substrate-bias variable transistors (27, 28) are provided in the shallow well regions (16, 17). Large-width device isolation regions (181, 182, 183) are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region (18) is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors (27, 28) of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.

Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions.

Abstract: The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a semiconductor substrate having a gate formed there over. The semiconductor device further includes an isolation region having at least one source/drain region formed there over.

Abstract: A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

Abstract: A method according to some embodiments of the invention includes forming a first gate pattern on a first region of a semiconductor substrate. The first gate pattern is formed to have a first gate insulating layer pattern, a first lower gate conductive layer pattern and a gate etching stopper layer pattern which are sequentially stacked. A second gate pattern is formed on a second region spaced apart from the first region to define a border region between the first and second regions. The second gate pattern is formed to have a second gate insulating layer pattern and a second lower gate conductive layer pattern, which are sequentially stacked. Thus, some embodiments may prevent two different gate conductive layers from overlapping with each other in the border region. Accordingly, semiconductor memory devices according to some embodiments of the invention do not have undesired active regions formed in the border region.

Abstract: A method and apparatus for forming shallow and deep isolation trenches in a substrate so that the shallow and deep isolation trenches are aligned without mis-registration. The method includes forming a plurality of shallow trenches, covering a portion of the plurality of shallow trenches, then etching the uncovered shallow trenches to create deeper trenches.

Abstract: In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and n+ source regions are formed on the p-well regions, respectively. A gate electrode is formed through a gate insulation film on a part of each p-well region and that of each n+ source region. The gate electrode is covered with an insulation film. On the insulation film, a source electrode is formed so that the n-channel MOSFET includes body diodes BD imbedded therein. A drain electrode is formed on the single crystal semiconductor substrate. A cluster-containing layer is implanted in the single crystal semiconductor substrate as a gettering layer so that the cluster-containing layer contains a cluster of nitrogen.

Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

Abstract: A semiconductor device includes a silicon oxide film (2) formed in a predetermined region on a single crystalline silicon substrate (1) and a gate dielectric film (3) as a thermal oxide film formed by performing thermal oxidation on the surface of the substrate (1) in a region adjacent to the silicon oxide film (2). A polycrystalline silicon (5) (or amorphous silicon) having an oxidized surface is formed on the border between the silicon oxide film (2) and gate dielectric film (3).

Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

Abstract: A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.