Abstract: A solid state image pickup device which can prevent color mixture by using a layout of a capacitor region provided separately from a floating diffusion region and a camera using such a device are provided. A photodiode region is a rectangular region including a photodiode. A capacitor region includes a carrier holding unit and is arranged on one side of the rectangle of the photodiode region as a region having a side longer than the one side. In a MOS unit region, an output unit region including an output unit having a side longer than the other side which crosses the one side of the rectangle of the photodiode region is arranged on the other side. A gate region and the FD region are arranged between the photodiode region and the capacitor region.

Abstract: A device includes a substrate carrying an array of diodes, organized in rows and columns, and a peripheral substrate contact is arranged on at least one side of the array. The substrate includes one or more buried conducting lines electrically connected to the peripheral substrate contact and being positioned between at least two neighbouring columns of diodes and/or between at least two neighbouring rows of diodes.

Abstract: An imaging unit comprising an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside. An imaging apparatus comprises an imaging unit that includes an imaging chip and a mounting substrate that has the imaging chip mounted thereon and includes a first metal layer for outputting a signal generated by the imaging chip to the outside.

Abstract: The present invention relates to a photodetector for detecting an infrared-light emission having a given wavelength (?) comprising a multilayer with: a layer (11) of a partially absorbent semiconductor; a spacer layer (12) made of a material that is transparent to said wavelength; and a structured metallic mirror (13), the distance (g) between the top of said mirror and said spacer layer being smaller than ? and said mirror comprising a network of holes defining an array of metallic reliefs with a pitch P of between 0.5 ?/nSC and 1.5 ?/nSC, where nSC is the real part of the refractive index of the semiconductor, a relief width L of between 9P/10 and P/2 and a hole depth h of between ?/100 and ?/15.

Abstract: One of disclosed embodiments provides a photoelectric conversion device, comprising a member including a first surface configured to receive light, and a second surface opposite to the first surface, and a plurality of photoelectric conversion portions aligned inside the member in a depth direction from the first surface, wherein at least one of the plurality of photoelectric conversion portions other than the photoelectric conversion portion positioned closest to the first surface includes, on a boundary surface thereof with the member, unevenness having a difference in level larger than a difference in level of unevenness of the photoelectric conversion portion positioned closest to the first surface, and wherein the boundary surface having the unevenness is configured to localize or resonate light incident on the member from a side of the first surface around the boundary surface having the unevenness.

Abstract: A signal charge collecting region is disposed inside a charge generating region so as to be surrounded by the charge generating region, and collects signal charges from the charge generating region. An unnecessary charge collecting region is disposed outside the charge generating region so as to surround the charge generating region, and collects unnecessary charges from the charge generating region. A transfer electrode is disposed between the signal charge collecting region and the charge generating region, and causes the signal charges from the charge generating region to flow into the signal charge collecting region in response to an input signal. An unnecessary charge collecting gate electrode is disposed between the unnecessary charge collecting region and the charge generating region, and causes the unnecessary charges from the charge generating region to flow into the unnecessary charge collecting region in response to an input signal.

Abstract: A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.

Abstract: An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even in a case that the insulating film provided between adjacent pixels is formed by a coating method, there is a problem that thin portions are partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the first polarity charge layer.

Abstract: A method and structure of an image sensor device including a read out integrated circuit (ROIC) and a photodiode array (PDA). An embodiment may include a package substrate having a recess and a raised pedestal within the recess; a read out integrated circuit (ROIC) physically attached to the raised pedestal; a photodiode array (PDA) physically attached to the ROIC and electrically coupled therewith; and a printed circuit board (PCB) within the recess in the package substrate, wherein the PCB has an opening therein and the raised pedestal at least partially extends through the opening in the PCB.

Abstract: A solid-state imaging element includes a pixel having a photoelectric conversion section and a side pinning layer. The photoelectric conversion section is formed in a semiconductor substrate. The side pinning layer is formed on a side of the photoelectric conversion section. The side pinning layer is formed by performing ion implantation in a state of a trench being open, the trench being formed in a part on a side of a region in which the photoelectric conversion section is formed.

Abstract: A pixel is provided with a photodiode region which includes a photoelectric conversion portion for receiving light and generating electrons, and a charge storage portion for storing electric charge. The pixel is configured in such a manner that an electron exclusion region is provided in the photodiode region with the diameter of a circle having the maximum diameter among circles that can exist in the surface of a region through which electrons can pass in the photodiode region as the width of an electron passage region in the photodiode region, and the width of the electron passage region is smaller than when the electron exclusion region is not provided.

Abstract: An image sensor may include a semiconductor substrate, a plurality of light receiving devices formed within the semiconductor substrate, and a plurality of device isolation films for isolating the light receiving devices from each other. When an arrangement direction of a pixel array may be formed by arranging the light receiving devices is a horizontal direction, the pixel array may be formed by alternately arranging a first type light receiving device and a second type light receiving device having different horizontal lengths.

Abstract: An image sensor pixel includes one or more photodiodes disposed in a semiconductor layer. Pixel circuitry is disposed in the semiconductor layer coupled to the one or more photodiodes. A passivation layer is disposed proximate to the semiconductor layer over the pixel circuitry and the one or more photodiodes. A contact etch stop layer is disposed over the passivation layer. One or more metal contacts are coupled to the pixel circuitry through the contact etch stop layer. One or more isolation regions are defined in the contact etch stop layer that isolate contact etch stop layer material through which the one or more metal contacts are coupled are coupled to the pixel circuitry from the one or more photodiodes.

Abstract: A photoelectric conversion portion, a charge holding portion, a transfer portion, and a sense node are formed in a P-type well. The charge holding portion is configured to include an N-type semiconductor region, which is a first semiconductor region holding charges in a portion different from the photoelectric conversion portion. A P-type semiconductor region having a higher concentration than the P-type well is disposed under the N-type semiconductor region.

Abstract: The bolometric sensing circuit includes a pixel array comprising pixels, each pixel comprising a sensor configuration to comprise a light receiving portion to convert incident photons into heat and a sensing portion integrated with the light receiving portion and having a resistance varying according to the converted heat; an output portion to output a common mode voltage that represents a voltage of the sensing portion from which accumulated heat has been removed in response to a heat removing voltage to thermally reset the sensing portion, and output a sensed voltage that represents a voltage of the sensing portion which has accumulated heat for an integration period after being thermally reset; and a processor to subtract the common mode voltage from the sensed voltage to produce a signal voltage that represents a change in resistance of the sensing portion due to the heat accumulated for the integration period.

Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.

Abstract: To provide a connection structure of a wiring cable and a connection method of a wiring cable which enable the downsizing of a head part. The connection structure includes: a semiconductor chip having a plurality of imaging elements formed on a front surface and a plurality of connection pads formed on a rear surface; and a wiring cable in which a plurality of wires are integrally formed and from whose end surface the plural wires are exposed, wherein the plural connection pads of the semiconductor chip and the plural wires exposed from the end surface are connected.

Abstract: A solid state imaging device 1 is provided with a photoelectric conversion portion 2 having a plurality of photosensitive regions 7, and a potential gradient forming portion 3 having an electroconductive member 8 arranged opposite to the photosensitive regions 7. A planar shape of each photosensitive region 7 is a substantially rectangular shape. The photosensitive regions 7 are juxtaposed in a first direction intersecting with the long sides. The potential gradient forming portion 3 forms a potential gradient becoming higher along a second direction from one of the short sides to the other of the short sides of the photosensitive regions 7. The electroconductive member 8 includes a first region 8a extending in the second direction and having a first electric resistivity, and a second region 8b extending in the second direction and having a second electric resistivity smaller than the first electric resistivity.

Abstract: This invention relates to multiband detector and multiband image sensing devices, and their manufacturing technologies. The innovative detector (or image sensing) provides significant broadband capability covering the wavelengths from within ultra-violet (UV) to long-Infrared, and it is achieved in a single element. More particularly, this invention is related to the multiband or dual band detectors, which can not only detect the broad spectrum wavelengths ranges from within as low as UV to the wavelengths as high as 25 ?m, but also band selection capability. This invention is also related to the multiband detector arrays or image sensing device for multicolor imaging, sensing, and advanced communication.

Abstract: An imaging device includes: a plurality of first absorption layers that absorb an infrared ray with a given wavelength range, and generate pixel signals of a plurality of pixels, respectively; at least one second absorption layer that absorbs an infrared ray with a wavelength range which is different from the given wavelength range of the first absorption layers, and generates a pixel signal common to the pixels; a plurality of first electrodes that take out the pixel signals from the first absorption layers, respectively; and a second electrode that takes out the pixel signal from the at least one second absorption layer.

Abstract: A stacked photodiode structure comprises a first-conductivity-type substrate, a second-conductivity-type well region and a first-conductivity-type well region. The first-conductivity-type substrate has a first surface for light incidence and a grounding terminal. The second-conductivity-type well region is formed in the first-conductivity-type substrate and adjacent to the first surface. The first-conductivity-type well region is formed in the second-conductivity-type well region and adjacent to the first surface. A PN junction between the first-conductivity-type well region and the second-conductivity-type well region generates free electrons responsive to visible light spectrum. A PN junction between the second-conductivity-type well region and the first-conductivity-type substrate generates free holes and free electrons responsive to mainly IR light.

Abstract: A detecting element has an absorbing section where a temperature rises according to an amount of electromagnetic waves which are absorbed and a detecting section where characteristics change according to an amount of heat which is transmitted from the absorbing section. A method for manufacturing the detecting element includes: forming the detecting section on a substrate; forming a protective film which covers the detecting section; forming a hollow space portion in a region which overlaps with the detecting section of the substrate in a planar view after the forming of the protective film; and forming the absorbing section by applying a liquid body, which contains a material constituting the absorbing section, in a region on the protective film on an opposite side from the detection section, which overlaps with the detecting section in a planar view, and solidifying the liquid body after the forming of the hollow space portion.

Abstract: A CMOS pixel is disclosed. The CMOS pixel includes a semiconductor substrate; a sense node formed in the semiconductor substrate and positioned substantially in the center of the CMOS pixel; a transfer gate formed about the sense node; and at least one photodiode formed about the transfer gate. A reset transistor, a source follower transistor, and a row select transistor are located substantially to one side of the CMOS pixel substantially adjacent to the photodiode. The sense node is operable to be floating. An implant may be formed about the photodiode configured to step potential in a direction toward the sense node.

Abstract: An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes.

Abstract: A solid-state imaging device includes a semiconductor layer where a pixel is formed in a pixel region and a semiconductor element is formed in a side opposite to where incident light is incident, a wiring layer provided on the semiconductor layer to cover the semiconductor element, a support substrate provided to oppose the wiring layer in a wiring layer surface opposite to the semiconductor layer, and an adhesion layer which adheres the wiring layer and the support substrate, where the wiring layer includes a pad electrode and an opening is formed so the pad electrode is exposed, a convex section is provided where the pad electrode is formed in at least a wiring layer surface opposing the support substrate or a support substrate surface opposing the wiring layer, and the adhesion layer is formed thinner at the formation portion of the pad electrode than a portion of the pixel region.

Abstract: In a solid-state imaging device, an amplification transistor amplifies a signal generated by a photoelectric conversion unit and outputs the amplified signal. An analog memory accumulates the amplified signal output from the amplification transistor. A select transistor electrically connects the analog memory to a vertical signal line and selects any one of a first state in which the amplified signal accumulated in the analog memory is output to the vertical signal line and a second state in which the analog memory is electrically disconnected from the vertical signal line. A differential amplification circuit includes a first input terminal connected to a reference voltage and a second input terminal connected to the vertical signal line.

Abstract: An image sensor having small pixels with high charge storage capacity, low dark current, no image lag, and good blooming control may be provided. The high charge storage capacity is achieved by placing a p+ type doped layer under the pixel charge storage region with an opening in it for allowing photo-generated charge carriers to flow from the silicon hulk to the charge storage well located near the surface of the photodiode. A compensating n-type doped implant may be formed in the opening. Image lag is prevented by placing a p? type doped region under the p+ type doped photodiode pinning layer and aligned with the opening. Blooming control is achieved by adjusting the length of the transfer gate in the pixel and thereby adjusting the punch-through potential under the gate.

Abstract: A solid-state image pickup device includes a photoelectric conversion portion, a charge holding portion configured to include a first-conductivity-type first semiconductor region, and a transfer portion configured to include a transfer gate electrode that controls a potential between the charge holding portion and a sense node. The charge holding portion includes a control electrode. A second-conductivity-type second semiconductor region is disposed on a surface of a semiconductor region between the control electrode and the transfer gate electrode. A first-conductivity-type third semiconductor region is disposed under the second semiconductor region. The third semiconductor region is disposed at a deeper position than the first semiconductor region.

Abstract: There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers.

Abstract: The present disclosure provides various embodiments of an image sensor device. An exemplary image sensor device includes an image sensing region disposed in a substrate; a multilayer interconnection structure disposed over the substrate; and a color filter formed in the multilayer interconnection structure and aligned with the image sensing region. The color filter has a length and a width, where the length is greater than the width.

Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. An contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the contact etch stop layer.

Abstract: An apparatus includes a three dimensional array of light receptors disposed within a substrate having a light receiving surface, where light receptors disposed closer to the light receiving surface are responsive to light having shorter wavelengths than light receptors disposed further from the light receiving surface, and where each light receptor is configured to output a binary value and to change state between an off-state and an on-state by the absorption of at least one photon.

Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.

Abstract: One or more embodiments of techniques or systems for mitigating dark current of an image sensor are provided herein. Generally, a silicon interface, such as an edge of a dielectric region or an edge between a back side interface (BSI) region and a pass region, is a source of electrons or holes which cause dark current. In some embodiments, the image sensor includes a surface protect region. For example, the surface protect region is doped with a first doping type and a photo-diode of the image sensor is doped with the same first doping type. In this manner, the surface protect region acts as an electron magnet or a hole magnet for electrons or holes from the silicon interface, thus mitigating electrons or holes from the silicon interface from being collected by the photo-diode, for example.

Abstract: According to an aspect of the invention, an imaging device includes a plurality of photoelectric conversion elements and a read-out portion. The photoelectric conversion elements are arranged above a substrate. The read-out portion reads out signal corresponding to charges which are generated from each of the photoelectric conversion elements. Each of the photoelectric conversion elements includes a first electrode that collects the charge, a second electrode that is disposed opposite to the first electrode, a photoelectric conversion layer that generates the charges and disposed between the first electrode and the second electrode, and an electron blocking layer that is disposed between the first electrode and the photoelectric conversion layer. Distance between the first electrodes of adjacent photoelectric conversion elements is 250 nm or smaller. Each of the electron blocking layers has a change in surface potential of ?1 to 3 eV from a first face to a second face.

Abstract: In a photoelectric conversion device capable of adding signals of photoelectric conversion elements included in each of photoelectric conversion units, each of the photoelectric conversion elements includes a first semiconductor region of a first conductivity type for collecting a signal charge, a second semiconductor region of a second conductivity type is arranged between the photoelectric conversion elements arranged adjacent to each other and included in the photoelectric conversion unit, and a third semiconductor region of the second conductivity type is arranged between the photoelectric conversion elements arranged adjacent to each other among the plurality of photoelectric conversion elements and included in different photoelectric conversion units arranged adjacent to each other. An impurity concentration of the second semiconductor region is lower than an impurity concentration of the third semiconductor region.

Abstract: An optical sensor chip device and a corresponding production method. The optical sensor chip device includes a substrate having a front side and a rear side; at least one first optical sensor chip for acquiring a first optical spectral range, the chip being attached to the substrate; and a first sealed cavern fashioned above an upper side of the first optical sensor chip. The first optical sensor chip is situated on a first side of the first cavern, and a first optical device is situated on an opposite, second side of the first cavern.

Abstract: A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.

Abstract: A fully depleted “diode passivation active passivation architecture” (DPAPA) produces a photodiode structure which includes a substrate, a highly-doped buffer layer of a first carrier doping type above the substrate, a low-doped or undoped semiconductor active layer of the first carrier doping type above the buffer layer, a low-doped or undoped passivation layer above the active layer, the passivation layer having a wider band gap than the active layer; and a junction layer of a carrier doping type opposite the first carrier doping type above the passivation layer such that a pn junction is formed between the junction layer and the passivation and active layers, the junction creating a depletion region which expands completely through the passivation and active layers in response to a reverse bias voltage. The fully depleted structure substantially eliminates Auger recombination, reduces dark currents and enables cryogenic level performance at high temperatures.

Abstract: An apparatus and method to decrease light saturation in a photosensor array and increase detection efficiency uses a light distribution profile from a scintillator-photodetector geometry to configure the photosensor array to have a non-uniform sensor cell pattern, with varying cell density and/or varying cell size and shape. A solid-state photosensor such as a SiPM sensor having such a non-uniform cell structure realizes improved energy resolution, higher efficiency and increased signal linearity. In addition the non-uniform sensor cell array can have improved timing resolution due to improvements in statistical fluctuations. A particular embodiment for such photosensors is in PET medical imaging.

Abstract: A semiconductor chip is specified that has a contact layer that is not optimum for many common applications. For example, the contact layer is too thin to tolerate an operating current intended for the semiconductor chip without considerable degradation. Also specified is an optoelectronic component in which the semiconductor chip can be integrated so that the suboptimal quality of the contact layer is compensated for. In the component the semiconductor chip is applied to a carrier body so that the contact layer is arranged on a side of the semiconductor body that is remote from the carrier body. The semiconductor chip and the carrier body are at least partly covered with an electrically isolating layer, and an electrical conductor applied to the isolating layer extends laterally away from the semiconductor body and contacts at least a partial surface of the contact layer. In addition, an advantageous process for producing the component is specified.

Abstract: An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a directional light sensor. The directional light sensor includes a plurality of photodetectors located on the major surface. The directional light sensor also includes one or more barriers, wherein each barrier is positioned to shade one or more of the photodetectors from light incident upon the integrated circuit from a respective direction. The directional light sensor is operable to determine a direction of light incident upon the integrated circuit by comparing an output signal of at least two of the photodetectors.

Abstract: Nanostructures are joined using one or more of a variety of materials and approaches. As consistent with various example embodiments, two or more nanostructures are joined at a junction between the nanostructures. The nanostructures may touch or be nearly touching at the junction, and a joining material is deposited and nucleates at the junction to couple the nanostructures together. In various applications, the nucleated joining material facilitates conductivity (thermal and/or electric) between the nanostructures. In some embodiments, the joining material further enhances conductivity of the nanostructures themselves, such as by growing along the nanostructures and/or doping the nanostructures.

Abstract: The invention describes the solid-state image sensor array and in particular describes in detail the junction gate BCMD pixel sensor array that can be used in the back side illuminated mode as well as in the front side illuminated mode. The pixels generally do not need addressing transistors and the reset is accomplished in a vertical direction to the junction gate, so no additional reset transistor is needed for this purpose. As a result of this innovation the pixel maintains large charge storage capacity when its size is reduced, has low noise due to the nondestructive charge readout, and no RTS noise. The pixel interface generated dark current is also drained to the gate, so the image sensor array operates with very low dark current noise even at high temperatures. The junction gate also serves as a drain for the overflow charge.

Abstract: An L.E.D. lamp assembly (20) includes an electrically insulative coating (24) disposed on a thermally conductive substrate (22). A plurality of light emitting diodes (26) are secured to the coating (24) and a circuit (40) is adhesively secured to the coating (24) in predetermined spaced lengths (42) along the coating (24) to establish discrete and electrically conductive spaced lengths (42) with the light emitting diodes (26) disposed between the spaced lengths (42). LED electrical leads (32) are secured to the spaced lengths (42) of the circuit (40) to electrically interconnect the light emitting diodes (26). The circuit (40) includes a foil tape (46) having an electrically conductive tape portion (48) and a coupling portion (50) disposed on the tape portion (48) for securing the foil tape (46) to the insulated substrate (22).

Abstract: A solid-state imaging apparatus is disclosed in which, in a first unit cell, light is collected to maximize an amount of light received when the light is incident at a first angle-of-incidence, and in a second unit cell adjacent to the first unit cell, light is collected to maximize an amount of light received when the light is incident at a second angle-of-incidence, the amount of light received when the light is incident at a third angle-of-incidence on the first unit cell is equal to the amount of light received when the light is incident at the third angle-of-incidence on the second unit cell, the first angle-of-incidence is greater than the third angle-of-incidence by a predetermined amount, and the second angle-of-incidence is smaller than the third angle-of-incidence by the predetermined amount.

Abstract: In various embodiments, image sensors incorporate multiple output structures by including multiple sub-arrays, at least one of which includes a region of active pixels, a dark pixel region that is fanned and/or slanted, a dark pixel region that is unfanned and unslanted, a horizontal CCD, and an output structure for conversion of charge to voltage.

Abstract: The present invention relates to an image sensor in which substrates are stacked, wherein a substrate-stacked image sensor according to the present invention is configured such that a first photodiode is formed on a first substrate, a second photodiode is formed on a second substrate, the two substrates are aligned with and bonded to each other to electrically couple the two photodiodes to each other, thereby forming a complete photodiode within one pixel.

Abstract: Capacitance between a detection capacitor and a reset transistor is the largest among the capacitances between the detection capacitor and transistors placed around the detection capacitor. In order to reduce this capacitance, it is effective to reduce the channel width of the reset transistor. It is possible to reduce the effective channel width by distributing, in the vicinity of the channel of the reset transistor and the boundary line between an active region and an element isolation region, ions which enhance the generation of carriers of an opposite polarity to the channel.