Abstract: A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules.

Abstract: In one general aspect, an apparatus can include a semiconductor die, a substrate, and a leadframe coupled to the substrate and defining an opening. The apparatus can include a one-body clip having a first portion disposed within the opening and coupled to the semiconductor die. The one-body clip can have a second portion disposed within the same opening and coupled to the substrate.

Abstract: A semiconductor chip (6) is disposed on the insulation substrate (2). A lead frame (8) is bonded to an upper surface of the semiconductor chip (6). A sealing resin (12) covers the semiconductor chip (6), the insulation substrate (2), and the lead frame (8). A stress mitigation resin (13) having a lower elastic modulus than that of the sealing resin (12) is partially applied to an end of the lead frame (8).

Abstract: A power semiconductor device is such that a notch provided, along a longitudinal end face of an inner lead, in a region of a lead frame to which the inner lead is bonded. A resistor is disposed, adjacent to the inner lead, on the same side as the notch with respect to the inner lead, and a distance between the inner lead and the notch is set to be smaller than a distance between the inner lead and the resistor, and thereby the inner lead, even when shifted in position, comes into no contact with the resistor. Because of this, it is no more necessary that a space be provided around the inner lead taking into consideration a positional shift of the inner lead, and it is possible to secure the heat release area of power semiconductor chips accordingly, and thus to obtain the small-sized and high-powered power semiconductor device.

Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.

Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.

Abstract: A circuit device includes a first conductive plate and a second conductive plate each having a belt-shaped portion arranged side-by-side with each other, a third conductive plate having a belt-shaped portion is arranged side-by-side with and spaced apart from the other side portion of the first conductive plate, a first circuit component having a first terminal connected to the first conductive plate and a second terminal connected to the second conductive plate, a second circuit component having a first terminal connected to the first conductive plate and a second terminal connected to the third conductive plate, a first external connection portion provided at the belt-shaped portion of the first conductive plate, and a second external connection portion provided at the belt-shaped portion of the second conductive plate or a third external connection portion provided at the belt-shaped portion of the third conductive plate.

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

Abstract: A package and a corresponding method are described. The method includes: providing a processed first wafer having front and back sides and including power semiconductor dies implemented within the wafer by processing its front side, each die having a first load terminal at the front side and a second load terminal at the back side; providing an unprocessed second wafer made of an electrically insulating material and having first and second opposing sides; forming a plurality of recesses within the second wafer; filling the plurality of recesses with a conductive material; forming a stack by attaching, prior or subsequent to filling the recesses, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.

Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.

Abstract: A current sensor device may include a routable molded lead frame that includes a molded substrate. The current sensor device may include a conductor and a semiconductor chip mounted to the molded substrate. The semiconductor chip may include a magnetic field sensor that is galvanically isolated from the conductor by the molded substrate and is configured to sense a magnetic field created by current flowing through the conductor. The current sensor device may include one or more leads configured to output a signal generated by the semiconductor chip. The one or more leads may be galvanically isolated from the conductor by the molded substrate.

Abstract: A chip-on-film package including a flexible substrate, first test pads, second test pads, first connecting wires, second connecting wires and a chip is provided. The flexible substrate includes at least one segment. Each segment has a central portion and a first side portion and a second side portion located at two opposite sides of the central portion. The chip disposed on the central portion includes first connecting pads and second connecting pads. The first test pads and the second test pads are disposed on the first side portion. Two ends of each of the first connecting wires are connected to the corresponding first connecting pad and the corresponding first test pad. Two ends of each of the second connecting wires are connected to the corresponding second connecting pad and the corresponding second test pad. Each of the second connecting wires includes a first section located at the second side portion.

Abstract: A sensor comprises a housing; and a lead frame comprising at least three elongated leads having an exterior portion extending from the housing; and a magnetic sensor circuit disposed in the housing, and connected to the lead frame. The housing comprises two recesses arranged on two opposite sides of the housing for allowing the sensor to be mounted to a support. The lead frame may further comprise a plurality of tabs disposed between the elongated leads, for use as test pins. A component assembly comprising said sensor mounted on a support between deformable protrusions. A method of making said component assembly, comprising the step of positioning said component on the support between said protrusions, and deforming said protrusions such that they are at least partially disposed within the recesses.

Abstract: A wiring structure includes at least one upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer, at least one upper circuit layer in contact with the upper dielectric layer, and at least one bonding portion electrically connected to the upper circuit layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.

Abstract: Leadframes for semiconductor packages. Implementations may include a plurality of leads extending inwardly into an opening surrounded by the plurality of leads where the plurality of leads except for at least one are configured to mechanically couple at a surface of a semiconductor chip. The at least one of the plurality of leads that is not configured to mechanically coupled at the surface of the semiconductor chip be configured to electrically couple with the semiconductor chip.

Abstract: An injection moulding apparatus and method for producing a moulded article is disclosed herein. In a described embodiment, the method comprises: (i) securing a layer of film to a part of a first mould half at step 504; (ii) adjusting relative position of the first mould component and a second mould component to an initial moulding position at step 506 to define a mould cavity; (iii) injecting molten moulding material into the mould cavity at step 508 to enable the molten moulding material to contact the layer of protective film; (iv) moving a movable core at step 510 to compress the molten moulding material in the mould cavity; and (v) cooling the compressed molten moulding material at step 514 to bond the layer of film to the cooled moulding material to form the moulded article.

Abstract: A semiconductor element includes an element body, a surface protective film and an electrode. The element body has a front surface and a side surface connected to the front surface. The surface protective film is supported on the front surface of the element body. The surface protective film has a cutout portion recessed inward from an outer edge of the surface protective film as viewed in a thickness direction of the element body. The electrode is disposed in the cutout portion and electrically connected to the element body. The element body has a ledge protruding with respect to the side surface in a direction perpendicular to the thickness direction. The ledge is adjacent to an opening of the cutout portion as viewed in the thickness direction.

Abstract: A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.

Abstract: A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad provided on the PCB base, a semiconductor die provided on the conductive die pad, and a conductive die bonding agent that electrically connects the conductive die pad and the semiconductor die. The semiconductor module further includes a wire bonding pad provided on the PCB base, a wire that electrically connects the wire bonding pad and the semiconductor die, and a sealing resin that seals the conductive die pad, the semiconductor die, the conductive die bonding agent, the wire bonding pad, and the wire. In a planar view, the area of the conductive die pad is 5.0 mm2 or less.

Abstract: A semiconductor device has inner leads (2a) of leads (2) which are covered with a first resin-encapsulating body (4), and has outer leads (2b) which are exposed from the first resin-encapsulating body (4), and which are given a shape bending downward and have distal ends having the bending shape extending in a lateral direction. The inner leads (2a) embedded in the first resin-encapsulating body (4) extend inward, and are then formed into a shape bending downward. Above end portions (3) having the bending shape, an element mounting portion (11) is formed of the first resin-encapsulating body (4), and a semiconductor element (6) placed on the element mounting portion (11) is covered with a second resin-encapsulating body (8).

Abstract: A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

Abstract: A semiconductor module includes block-shaped first and second lower base members provided by bonding of flat lower surfaces on an insulated circuit board and having bottomed first and second hole portions open in upper surfaces in upper portions of the first and second lower base members, tubular first and second upper slide support members inserted in the first and second hole portions in a state where at least a part of outside surfaces is in contact with inside walls of the first and second hole portions, first and second pins inserted in contact with the insides of the first and second upper slide support members, and a sealing resin sealing the first and second pins except for the upper portions of the first and second pins.

Abstract: A distributed fiber optic communication network for controlling a gas turbine engine includes a computation module and an input/output (I/O) module. The computation module and the I/O module are connected via the communication network. The communication network comprises multi-mode fiber optic cables, wherein data is transferred thereon on multiple frequency bands. The frequency bands range from about 300 nm to about 1550 nm. A method of frequency hopping is provided in which communication band instructions are stored locally on nodes of the communication network and may include communication band instructions transmitted to nodes of the communication network on a dedicated band.

Abstract: Solid state light emitting devices including light-emitting diodes (LEDs), and more particularly packaged LEDs are disclosed. In some embodiments, an LED package includes electrical connections that are configured to reduce corrosion of metals within the LED package; or decrease the overall forward voltage of the LED package; or provide an electrical path for serially-connected electrostatic discharge (ESD) chips. In some embodiments, an LED package includes at least two LED chips and a material between the two LED chips that promotes homogeneity of composite emissions from the two LED chips. In this manner, LED packages according to the present disclosure may be beneficial for various applications, including those where a high luminous intensity is desired in a variety of environmental conditions. Such applications include automotive lighting, aerospace lighting, and general illumination.

Abstract: A lead frame strip with corrugated saw street metal where the corrugated saw street metal is comprised of a partial thickness of the lead frame strip metal. A lead frame strip with corrugated saw street metal where the corrugated saw street metal is comprised of a half thickness of the lead frame strip metal.

Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.

Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.

Abstract: An electronic device includes: an electronic component; and a mounting member on which the electronic component is mounted. A center of gravity of the electronic component is at a position separated from the mounting member. The electronic device further includes: a rigid member having a frame shape, which is fixed to the mounting member and surrounds the electronic component in a direction perpendicular to a direction from the center of gravity of the electronic component to the mounting member; and a connecting member which connects the electronic component to the rigid member on a side opposite to the mounting member with respect to the electronic component.

Abstract: A method of fabricating a semiconductor device is provided in which an adhesive layer is disposed on a first surface of a first semiconductor substrate. A carrier substrate is provided on the first surface of the first semiconductor substrate, and the carrier substrate is separated from a surface of the adhesive layer while the adhesive layer is still attached to the first surface of the first semiconductor substrate.

Abstract: Solid state light emitting devices including light-emitting diodes (LEDs), and more particularly packaged LEDs are disclosed. In some embodiments, an LED package includes electrical connections that are configured to reduce corrosion of metals within the LED package; or decrease the overall forward voltage of the LED package; or provide an electrical path for serially-connected electrostatic discharge (ESD) chips. In some embodiments, an LED package includes at least two LED chips and a material between the two LED chips that promotes homogeneity of composite emissions from the two LED chips. In this manner, LED packages according to the present disclosure may be beneficial for various applications, including those where a high luminous intensity is desired in a variety of environmental conditions. Such applications include automotive lighting, aerospace lighting, and general illumination.

Abstract: A method for manufacturing a semiconductor device includes preparing a lead frame, mounting a semiconductor element on an obverse face of the lead frame, forming a sealing resin covering the semiconductor element, forming a groove on a reverse face of the lead frame, and removing a portion of the lead frame and a portion of the sealing resin along a disposal region that is narrower than the groove and entirely overlaps with the groove. The preparing of the lead frame includes forming at least one recess located in the disposal region and having an end that is open in the thickness direction. The forming of the groove includes exposing the recess on a side of the reverse face of the lead frame. The removing is performed with reference to the recess.

Abstract: A semiconductor device includes: a first semiconductor element including a first signal electrode; a second semiconductor element, laminated on the first semiconductor element, including a second signal electrode; a sealing body; a first signal terminal connected to the first signal electrode; and a second signal terminal connected to the second signal electrode, wherein: the first signal terminal and the second signal terminal project from the sealing body and extend in a first direction; the first signal terminal and the second signal terminal are distanced from each other in a second direction; the first signal electrode and the second signal electrode are placed at different positions in the second direction; the first signal electrode is provided closer to the first signal terminal than to the second signal terminal; and the second signal electrode is provided closer to the second signal terminal than to the first signal terminal.

Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

Abstract: A semiconductor device may include a first conductor plate on which a first semiconductor element, a second semiconductor element and a first circuit board are disposed, and a plurality of first signal terminals. A size of the second semiconductor is smaller than a size of the first semiconductor element. In a plan view along a direction perpendicular to the first conductor plate, the plurality of first signal terminals is located in a first direction with respect to the first semiconductor element. The second semiconductor element and the first circuit board are located between the plurality of first signal terminals and the first semiconductor element and are arranged along a second direction that is perpendicular to the first direction. A signal pad of the first semiconductor element is connected to a corresponding one of the plurality of first signal terminals via a signal transmission path of the first circuit board.

Abstract: A terminal 20 includes a terminal connection portion 21 connected to a counterpart terminal and a board connection portion 24 connected to a conductive path 13 of a board 11. The board connection portion 24 has a plate shape portion 25 that is a plate shape. The plate shape portion is disposed behind the terminal connection portion 21 and is soldered to the conductive path 13 of the board 11. The board connection portion has a plate-shape first projection walls 28A to 28D that are bent from edge portions of a lateral direction side of the plate shape portion 25 and that project to an opposite side to the board 11 side. The plate shape portion 25 and the first projection walls 28A to 28D have a plating layer 37 that is formed on a plate surface of the plate shape portion and the first projection walls.

Abstract: A leadframe comprising a plurality of leads, each of the plurality of leads having a proximal end and a distal end opposite the proximal end, the distal ends positioned along a linear axis. The leadframe further comprises a die pad closer to the proximal ends than the distal ends of the plurality of leads and including an edge positioned along a plane that intersects the linear axis at an angle less than 90 degrees.

Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.

Abstract: An object is to provide a technique for reducing process steps, and a stress generated at the peripheral portion of the joint portion between an electrode of a semiconductor element and a lead frame. A semiconductor device includes the following: a semiconductor element disposed on a heat spreader; a lead frame joined to an emitter electrode of the semiconductor element via solder, which is a joining material; a metal film disposed on a surface of the emitter electrode; and an anti-oxidation film disposed on a surface of the metal film. The metal film has a peripheral portion that is entirely exposed from the anti-oxidation film.

Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip thicker than the first semiconductor chip, a plurality of bumps provided between the first and second semiconductor chips and electrically connecting the first and second semiconductor chips, an adhesive resin provided between the first and second semiconductor chips and bonding the first and second semiconductor chips, and a sealing resin encapsulating the first and second semiconductor chips. At least one of the first and second semiconductor chips has an organic protective film disposed thereon.

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

Abstract: A light detection device includes: a package including an opening configured to allow light to enter therefrom; a light transmitting unit arranged on an inner surface of the package so as to close the opening; a Fabry-Perot interference filter arranged in the package and configured to transmit light transmitted by the light transmitting unit; and a light detector arranged in the package and configured to detect the light transmitted by the Fabry-Perot interference filter. The light transmitting unit is integrally configured by including: a band pass filter arranged in the package and configured to transmit the light to be incident on the Fabry-Perot interference filter; and at least one lens unit configured to condense the light to be incident on the Fabry-Perot interference filter.

Abstract: Embodiments of the present disclosure are directed to flat no-lead packages with wettable sidewalls or flanks. In particular, wettable conductive layers are formed on the package over lateral portions of the leads and on portions of the package body, which may be encapsulation material. The wettable conductive layers may also be formed on bottom surfaces of the package body and the leads. The wettable conductive layers provide a wettable flank for solder to wick up when the package is mounted to a substrate, such as a PCB, using SMT. In particular, solder that is used to join the PCB and the package wicks up the side of the wettable conductive layers along a side surface of the package. In that regard, the solder is exposed and coupled to the side surface of the package at the wettable conductive layers, thereby allowing for a visual inspection of the solder joints. The wettable conductive layers are formed on the package after the package body has been formed.

Abstract: A circuit board is provided. The circuit board includes a first pin row, a second pin row and a plurality of signal vias. The first pin row includes a first side and a second side, wherein the first side of the first pin row and the second side of the first pin row are opposite to each other. The second pin row includes a first side and a second side, wherein the first side of the second pin row and the second side of the second pin row are opposite to each other. A plurality of traces of the circuit board are electrically connected to a plurality of pins of the first pin row and a plurality of pins of the second pin row respectively through the signal vias. Three consecutive signal vias of the signal vias are sequentially disposed at the first side of the first pin row, the first side of the second pin row, and the second side of the first pin row.

Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.

Abstract: A package encloses a power semiconductor die and has a package body with a top side, footprint side and sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; and a top layer arranged at the package top side and electrically connected with the second load terminal. A heat spreader is mounted onto the top layer with a bottom surface facing the top layer. The area of the top surface of the heat spreader is greater than the area of the bottom surface.

Abstract: A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering top faces and faces that form concavities or a through hole between the top faces and bottom faces of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

Abstract: A semiconductor device including a base, a buffer member, a frame, a lid, and a semiconductor element, is disclosed. The ceramic frame is mounted on the copper base with the molybdenum buffer member interposed therebetween. The semiconductor element is sealed in a space within the frame defined by the lid. The frame includes a top portion, a lower stage portion that is disposed below the top portion and is provided with an input electrode and an output electrode, and an upper stage portion. The upper stage portion is formed in an arrangement direction of the input electrode and the output electrode, and is formed below the top portion and above the lower stage portion. The upper stage portion includes an upper stage connection portion formed on the periphery of the lower stage portion in a direction intersecting the arrangement direction of the input electrode and the output electrode.

Abstract: Disclosed is technology in that a clip structure formed of an inexpensive and light metallic material to easily performing soldering on a corresponding metal and to reduce costs of a semiconductor package and to reduce the weight of the semiconductor package. The composite clip structure bent at a predetermined angle and being in charge of electrical connection between components in a semiconductor package includes a main metal layer formed of a conductive material with a predetermined thickness, and a lower functional layer formed below the main metal layer and formed of a different type of metal from a metallic component of the main metal layer, wherein the lower functional layer is attached to the main metal layer to be integrated thereinto, and wherein the main metal layer is formed of a single metal containing a largest amount of aluminum (Al) or a metal mixture containing a largest amount of Al.

Abstract: Photonic circuits are disclosed having an efficient optical power distribution network. Laser chips (InP) having different wavelengths are flip-chip assembled near the center of a silicon photonic chip. Each InP die has multiple optical lanes, but a given die has only one wavelength. Waveguides formed in the photonic chip are optically connected to the lanes, and fan out to form multiple waveguide sets, where each waveguide set has one of the waveguides from each of the different wavelengths, i.e., one waveguide from each InP die. The waveguide network is optimized to minimize the number of crossings that any given waveguide may have, and no waveguide having a particular wavelength crosses another waveguide of the same wavelength. The unique arrangements of light sources and waveguides allows the use of a smaller number of more intense laser sources, particularly in applications such as performance-optimized datacenters where liquid cooling systems may be leveraged.