Abstract: An LED package structure includes a multilayer circuit board, an LED chip, and a cover. The multilayer circuit board has a conductive layer, a first resin layer disposed on the conductive layer, and a first circuit layer disposed on the first resin layer. The first resin layer has a first opening, and a portion of the conductive layer is partially exposed from the first resin layer via the first opening such that a mounting region is exposed. The first circuit layer has a second opening, and the second opening exposes the mounting region. The LED chip is fixed on the mounting region by passing it through the first and second openings, and the LED chip is connected to the first circuit layer by wires. The cover is disposed on the first resin layer and covers the LED chip and the first circuit layer.

Abstract: A brazing method for assembling two elements includes selecting two brazing materials that can generate, when they are heated and melted, an intermetallic compound having a melting temperature which is higher than the melting temperature of each of the selected brazing materials taken individually, positioning the two selected brazing materials between the two elements, heating and melting the two selected brazing materials in order to substantially reach the melting temperature of each of the selected brazing materials so as to achieve the precipitation of an intermetallic compound having a melting temperature which is higher than the melting temperature of each of the selected brazing materials taken individually.

Abstract: A power transistor, a driver and an output stage. The power transistor includes an active region and a metallization level located above the active region for power distribution and for detecting an imminent metallization error induced by stress (RPP stress) caused by repeated power pulses. The power transistor also includes a further metallization level, which is located above the metallization level and in which galvanically isolated metal elements extend mutually parallel in a direction of extent, of which one pair is used for energizing the power transistor. It is a characteristic of the power transistor that at least one cut-out is formed above the active region in the further metallization level. The cut-out has the effect of decreasing heat dissipation. The power transistor is thereby heated more intensely in the localized region, so that large temperature gradients occur in the transition region defined by the edges of the metal elements.

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.

Abstract: A lead frame has a concavity formed on the upper-surface side of a metal plate and columnar portions defined by the concavity. A horizontally deepest portion regarding a side face shape of the concavity is positioned lower than the vertical center position of the concavity. Thereby, overhangs projecting from the top faces of the columnar portions rarely cause shape defects or burr defects and thus the lead frame has an enhanced capability, by the columnar portions, of preventing a sealing resin from coming off without sacrificing the freedom of wiring design.

Abstract: A semiconductor device having a housing is provided, where the housing includes the first surface, concave portions provided to the first surface, the second surface to face toward the first surface, and convex portions provided in contact with the second surface. In a thickness direction of the housing directed from the first surface to the second surface, the concave portions and the convex portions are provided at positions corresponding to each other.

Abstract: A package includes a resin molded body having a side wall provided between a first side and a second side to surround a recess portion which has a bottom portion on the second side. The bottom portion of the recess portion includes an element mount region provided in a vicinity of the side wall and a wire connection region separated from the element mount region. The element mount region has a polygonal outer peripheral shape having corners and diagonals connecting two of the corners when viewed in the height direction. An area of the wire connection region is smaller than an area of the element mount region when viewed in the height direction. The wire connection region is provided on an extension of one of the diagonals passing through one of the corners of the element mount region to face toward the adjacent to one of the corners.

Abstract: An integrated circuit package includes a lead frame having a first surface, a second opposing surface, at least one die attach portion configured to support at least one die, and a plurality of leads, wherein at least one of the leads has a raised feature extending along a portion of a length of the lead.

Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

Abstract: A semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame. The drain frame includes drain frame fingers. The source frame includes source frame fingers. The drain frame fingers and the source frame fingers are alternately arranged in a first direction and include overlapping portions as viewed from a first direction. In a region where each drain frame finger overlaps the source frame fingers as viewed in the first direction, at least either one of the drain frame fingers and the source frame fingers are not exposed from the back surface of the encapsulation resin.

Abstract: A leadframe includes a first die attach pad (“DAP”) having a first longitudinally extending edge surface and a second DAP having a first longitudinally extending edge surface. The second DAP is positioned with the first longitudinally extending edge surface thereof in adjacent, laterally and vertically spaced relationship with the first longitudinally extending edge surface of the first DAP.

Abstract: A testing system for semiconductor package components includes a testing circuit board, a test socket, at least one probe pin and a thermal barrier layer element. The testing circuit board has at least one electrical contact. The test socket is used to receive a DUT. The probe pin is located on the test socket for contacting with the DUT. The thermal barrier layer element is located between the testing circuit board and the test socket, electrically connected to the probe pin and the electrical contact, and thermally isolated the electrical contact from the probe pin.

Abstract: A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps.

Abstract: A semiconductor device includes a first lead with a first block, a second lead with a second block, and a sealing resin partially covering the first and second leads. The first block is exposed from the sealing resin and has a first covered surface covered with an electroconductive layer, and a pair of first exposed surfaces spaced apart from each other via a part of the first covered surface. The second block is exposed from the sealing resin and has a second covered surface covered with an electroconductive layer, and a pair of second exposed surfaces spaced apart from each other via a part of the first covered surface.

Abstract: A resin package includes: a resin portion, a first lead having an upper surface and an end surface, a second lead having an upper surface and disposed opposite the first lead, and a recess having lateral surfaces and a bottom surface that includes a portion of the upper surface of the first lead and a portion of the upper surface of the second lead that are exposed from the resin portion. In a top view, the upper surface of the first lead includes a first groove overlapping a first side of the bottom surface, a second groove overlapping a second side of the bottom surface, a third groove overlapping a third side of the bottom surface, and one or more fourth grooves extending from a portion of the third groove to an end surface of the first lead facing the second lead.

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

Abstract: In a described example, a method for making a packaged semiconductor device includes laser ablating a first groove with a first width and a first depth into a mounting surface of a substrate between landing pads. A first pillar bump on an active surface of a semiconductor device is bonded to a first landing pad; and a second pillar bump on the semiconductor device is bonded to a second landing pad. A channel forms with the active surface of the semiconductor device forming a first wall of the channel, the first pillar bump forms a second wall of the channel, the second pillar bump forming a third wall of the channel, and a surface of the first groove forms a fourth wall of the channel. The channel is filled with mold compound and at least a portion of the substrate and the semiconductor device are covered with mold compound.

Abstract: A leadframe has a peripheral frame. A die attach pad (DAP) is positioned inwardly and downwardly of the peripheral frame. Two spaced apart parallel arms engage one side of the DAP. In one embodiment the arms are portions of a U-shaped strap.

Abstract: Printhead pin configurations are disclosed. An example printhead assembly includes an interface to place the printhead assembly in communication with a logic circuit; and a logic circuit configured according to a pin configuration, the pin configuration comprising pin groups, wherein each of the pin groups includes a signal line and a reference voltage.

Abstract: An integrated circuit (IC) package, e.g., a power MOSFET package, may include a lead frame including (a) a main lead frame structure including a plurality of leads and defining or lying in a main lead frame plane, and (b) an offset lead frame die-attach pad (DAP) defining or lying in an offset plane that is offset from the main lead frame plane. The power IC package may further include a semiconductor die having a first side attached to the offset lead frame DAP, and a conductive element attached to both (a) a second side of the semiconductor die and (b) the main lead frame structure. The lead frame including the offset DAP may emulate the functionality of a copper clip, thus eliminating the need for the copper clip. The power IC package may also exhibit enhanced heat dissipation capabilities.

Abstract: In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

Abstract: An electronic device includes a lead frame, a first clip, a second clip, and a plurality of semiconductor devices. The first clip is stacked with the lead frame. The second clip stacked with the first clip and the lead frame. The second clip includes a first protrusion that engages the first clip and secures the second clip to the first clip. The semiconductor devices are conductively coupled to the lead frame via the first clip and the second clip.

Abstract: A first lead terminal, a second lead terminal provided parallel to the first lead terminal, and a tie bar connecting the first lead terminal and the second lead terminal are provided. The tie bar includes a first narrow-width section touching the first lead terminal, a second narrow-width section touching the second lead terminal, and a wide-width section having a larger width than the first narrow-width section and the second narrow-width section and connecting the first narrow-width section and the second narrow-width section. The wide-width section has a through-hole formed between the first narrow-width section and the second narrow-width section.

Abstract: A power semiconductor device and package includes multiple electrically parallel semiconductor device legs designed to share source regions and share a drain region between two devices in each leg laterally staggered from each other to distribute thermal conductivity across the shared source regions. A multitude of jigsaw patterned lateral isolation trenches are formed in a substrate of the device. The trenches are configured to isolate the laterally staggered line-in and line-out source regions from a common drain region of the plurality of semiconductor device legs. The staggered devices are also designed for staggered time and staggered heat conductivity delays and current spreading from the package input to an output of a respective pair of devices to improve current and heat conductivity from the package input to an output of a subsequent pair of devices.

Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.

Abstract: A light emitting device includes a package having a recess which includes a bottom surface having corners. The package includes a first electrode, a second electrode, and a resin portion. The first electrode is provided at a first part of the bottom surface. The second electrode is provided at a second part of the bottom surface. The resin portion is provided between the first electrode and the second electrode at a third part of the bottom surface. A protection element is provided on the bottom surface. A light reflective material covers the bottom surface except for an uncovered region to cover the protection element and the corners of the bottom surface and uncovers an uncovering region of the bottom surface. The uncovered region is defined by linear lines and curved lines connecting the linear lines. A light emitting element is provided in the uncovered region on the bottom surface.

Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.

Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.

Abstract: To improve a performance of a semiconductor device, a semiconductor device includes a lead electrically coupled to a semiconductor chip via a wire. An inner portion of the lead, the semiconductor chip, and the wire are sealed by a sealing body (a resin sealing body). The wire is bonded to an upper surface of a wire bonding portion of the inner portion of the lead. A metal film is formed on a lower surface of the inner portion of the lead, which is on an opposite side to the upper surface. No metal film is formed on the upper surface of the wire bonding portion.

Abstract: A method of manufacturing a semiconductor device includes forming a substrate structure. The substrate structure includes a carrier, an adhesive layer, and a signal distribution structure (SDS). The carrier includes a top carrier side and a bottom carrier side. The adhesive layer includes a bottom adhesive layer side on the top carrier side and a top adhesive layer side. The SDS includes a bottom SDS side adhered to the top adhesive layer side and a top SDS side. The SDS also includes conductive layers and at least one dielectric layer. The method includes coupling a bottom side of a test carrier to the top SDS side. The test carrier includes an aperture that exposes at least a portion of the top SDS side. The method also includes testing the SDS, at least in part, through the aperture in the test carrier and attaching the carrier to the bottom SDS side.

Abstract: A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.

Abstract: A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.

Abstract: A method for forming a micro-electro mechanical system (MEMS) device is provided. The method includes forming a first dielectric layer over a semiconductor layer and forming a blocking layer over the first dielectric layer. The method also includes bonding a CMOS substrate with the blocking layer, and the CMOS substrate includes a second dielectric layer, and the blocking layer is configured to block gas coming from the second dielectric layer. The method further includes partially removing the first dielectric layer to form a cavity between the semiconductor layer and the blocking layer. A portion of the semiconductor layer above the cavity becomes a movable element. In addition, the method includes sealing the cavity such that a closed chamber is formed to surround the movable element.

Abstract: A test board for a semiconductor device and a test board including the same are provided. A test board includes a substrate, a mounting pad which is formed on the substrate and on which a semiconductor chip is mounted and a test terminal group arranged on the substrate to be spaced apart from the mounting pad and electrically connected to the semiconductor chip by a pattern arranged on the substrate, wherein the semiconductor chip includes a first terminal and a second terminal for inputting/outputting signals, the test terminal group includes a first test terminal electrically connected to the first terminal and a second test terminal electrically connected to the second terminal, a first voltage is applied to the first terminal and the second terminal, and a stress signal that is caused by a second voltage is applied to the first test terminal.

Abstract: A manufacturing method of a semiconductor device according to the present embodiment includes forming a modified layer with distortion in semiconductor crystals in a first and a second semiconductor wafers by radiating laser to a dicing region of the first and second semiconductor wafers, each of the first and second semiconductor wafers including a plurality of semiconductor chips. The method also includes stacking the second semiconductor wafer on the first semiconductor wafer to be shifted in a first direction. The first direction is a direction from a first side of a first semiconductor chip of the first semiconductor wafer towards an opposite side to the first side of the first semiconductor chip. The method further includes cleaving the first and second semiconductor wafers.

Abstract: The power module includes: a ceramics substrate; a source electrode pattern, a drain electrode pattern, a source signal electrode pattern, and a gate signal electrode pattern respectively disposed on the ceramics substrate; a semiconductor device disposed on the drain electrode pattern, the semiconductor device comprising a source pad electrode and a gate pad electrode at a front surface side; a divided leadframe for source bonded to the source electrode pattern and the source pad electrode; and a divided leadframe for gate pad electrode bonded to a gate pad electrode. There is provided a power module having a simplified structure, fabricated through a simplified process, and capable of conducting a large current; and a fabrication method for such a power module.

Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.

Abstract: A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

Abstract: Embodiments of the invention include a microelectronic device and methods for forming a microelectronic device. In an embodiment, the microelectronic device includes a semiconductor die that has one or more die contacts that are each electrically coupled to a contact pad by a conductive trace. The semiconductor die may have a first elastic modulus. The microelectronic device may also include an encapsulation layer over the semiconductor die and the conductive trace. The encapsulation layer may have a second elastic modulus that is less than the first elastic modulus. The microelectronic device may also include a first strain redistribution layer within the encapsulation layer. The first strain redistribution layer may have a footprint that covers the semiconductor die and a portion of the conductive traces. The strain redistribution layer may have a third elastic modulus that is less than the first elastic modulus and greater than the second elastic modulus.

Abstract: A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer.

Abstract: A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad. The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface.

Abstract: A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.

Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

Abstract: A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

Abstract: Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.

Abstract: A leadframe of a semiconductor device includes a die pad, first and second suspension leads, and a frame. The main surfaces of the die pad and the frame are located on different planes, and the die pad and the frame are connected to each other by the first and second suspension leads. A first boundary line between the first suspension lead and the die pad runs on a straight line different from a second boundary line between the second suspension lead and the die pad. A third boundary line between the first suspension lead and the frame runs on a straight line different from a fourth boundary line between the second suspension lead and the frame.

Abstract: A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.

Abstract: Semiconductor devices may include a substrate and a semiconductor die on the substrate. The semiconductor die may include an active surface and a lateral edge at a periphery of the active surface. An electrically insulating material may be located on the active surface proximate the lateral edge. The electrically insulating material may be distinct from any other material located on the active surface. A wire bond may extend from the active surface, over the electrically insulating material, to the substrate. Methods of making semiconductor devices may involve positioning an electrically insulating material on an active surface of a semiconductor die proximate a lateral edge at a periphery of an active surface. After positioning the electrically insulating material on the active surface, a wire bond extending from the active surface, over the electrically insulating material, to the substrate may be formed.