Abstract: A multiple access Proximity Communication system in which electrical elements on an integrated circuit chip provide the multiplexing of multiple signals to a single electrical receiving element on another chip. Multiple pads formed on one chip and receiving separate signals may be capacitively coupled to one large pad on the other chip. Multiple inductive coils on one chip may be magnetically coupled to one large coil on another chip or inductive coils on three or more chips may be used for either transmitting or receiving. The multiplexing may be based on time, frequency, or code.

Abstract: An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

Abstract: A semiconductor device includes: a first output unit configured to output a first phase; a second output unit configured to output a second phase different from the first phase, the second output unit being disposed to be stacked on the first output unit; and a controller configured to control the output units.

Abstract: The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a thermal attach cluster includes: forming a heat collector having a heat dissipation surface, forming a cluster bridge, having a thermal surface, connected to the heat collector, forming a cluster pad, having an attachment surface, connected to the end of the cluster bridge opposite the heat collector; connecting an integrated circuit to the thermal attach cluster; and forming an encapsulation over the thermal attach cluster with the heat dissipation surface, the thermal surface, and the attachment surface exposed from and coplanar with the encapsulation.

Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead.

Abstract: A first lead frame group is constituted by a plurality of lead frames that are connected to the first circuit, terminals of the plurality of lead frames being provided on a first side of the semiconductor device. A second lead frame group is constituted by a plurality of lead frames that are connected to the second circuit, terminals of the plurality of lead frames being provided on a second side of the semiconductor device. A suspension lead for suspending a die pad that supports the semiconductor chip, the suspension lead being arranged from a corner portion that is formed by the first side and the second side toward the semiconductor chip. Among a group of the terminals of the first lead frame group that are provided on the first side, a terminal on the corner portion side is a terminal for inputting or outputting a signal with a high frequency.

Abstract: An integrated circuit package system includes: forming an array of external interconnects with an intersecting region between the external interconnects; removing the intersecting region for forming an isolation hole between the external interconnects; mounting an integrated circuit die over the external interconnects; connecting an internal interconnect between the integrated circuit die and the external interconnects; and forming a package encapsulation over the integrated circuit die with the external interconnects partially exposed.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Abstract: In a method for manufacturing a semiconductor device according to the present invention, as shown in FIG. 2(A), a case (2) including a first terminal (1) is placed on a working table (3) with an opening (30) formed at the bottom of the case (2). Subsequently, as shown in FIG. 2(B), a plurality of packages (6,6,6) including second terminals (4) are placed on the working table (3) through the opening (30) of the case (2), forming a clearance (31) between the first terminal (1) and the second terminal (4). As shown in FIG. 2(C), a bonding material (7) is disposed in the clearance (31) so as to electrically connect the first terminal (1) and the second terminal (4). Thus, the exposed surfaces of the packages (6,6,6) in the opening (30) of the case (2) are aligned at the same height, thereby reducing variations in thermal resistance among the packages (6,6,6).

Abstract: A semiconductor system (100) has a first planar leadframe (101) with first leads (102) and pads (103) having attached electronic components (120), the first leadframe including a set of elongated leads (104) bent at an angle away from the plane of the first leadframe; a second planar leadframe (110) with second leads (112) and pads (113) having attached electronic components (114); the bent leads of the first leadframe conductively connected to the second leadframe, forming a conductively linked 3-dimensional network between components and leads in two planes; and packaging material (140) encapsulating the 3-dimensional network.

Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.

Abstract: A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

Abstract: A semiconductor device includes at least 4 conductive line groups arranged in parallel over one memory cell block and each configured to include conductive lines. First contact pads may be coupled to the respective ends of the conductive lines of two of the 4 conductive line groups in a first direction, and second contact pads may be coupled to the respective ends of the conductive lines of the remaining 2 of the 4 conductive line groups in a second direction opposite to the first direction.

Abstract: An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.

Abstract: An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.

Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.

Abstract: A lead frame includes: a chip-mounting region provided on a front surface; a lead region including a plurality of concave and convex sections arranged in an in-plane direction of the chip-mounting region; and a terminal arranged in the concave section. A thickness of the lead region from the front surface is smaller than a thickness of the terminal from the front surface.

Abstract: Chip carriers are provided. The chip carrier includes a carrier body having a cavity therein and at least one conductive through silicon via (TSV) penetrating the carrier body under the cavity. The cavity includes an uneven sidewall surface profile. The at least one conductive through silicon via (TSV) is exposed at a bottom surface of the carrier body opposite to the cavity. Related methods are also provided.

Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced package (9) with exposed heat spreader lid array (96) designed to be optimized for compression mold encapsulation of an integrated circuit die (94) by including a perimeter reservoir regions (97r) in each heat spreader lid (96) for movement of mold compound (98) displaced during the mold compression process.

Abstract: An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.

Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Abstract: In a connecting portion between an interconnection and a first bump which is a part of a through electrode penetrating a semiconductor chip and which penetrates a semiconductor substrate, a protruding portion protruding from the interconnection to the side of the first bump is provided. The protruding portion may be made of an insulating material and may be made of a conductive material.

Abstract: A semiconductor unit includes a base having a surface where a first insulation layer is disposed, a second insulation layer spaced apart from the first insulation layer to form a region therebetween and disposed parallel to the surface of the base where the first insulation layer is disposed, a single conductive layer disposed across the first insulation layer and the second insulation layer, and a semiconductor device bonded to the conductive layer.

Abstract: A semiconductor package has a substrate with a solder mask layer, and upper and lower surfaces. Conductive traces and electrical contacts are formed on the substrate, and vias are formed in the substrate to electrically connect the conductive traces and electrical contacts. A semiconductor die is attached on the upper surface of the substrate. A mold cap is formed on the upper surface of the substrate and covers the die and the conductive traces. The mold cap includes a mold body having clipped corners and extensions that extend from each of the clipped corners. The extensions and clipped corners help prevent package cracking.

Abstract: The present disclosure relates to a semiconductor package structure and semiconductor process. The semiconductor package includes a first substrate, a second substrate, a die, a plurality of interconnection elements and an encapsulation material. Each of the interconnection elements connects the first substrate and the second substrate. The encapsulation material encapsulates the interconnection elements. The encapsulation material defines a plurality of accommodation spaces to accommodate the interconnection elements, and the profile of each accommodation space is defined by the individual interconnection element, whereby the warpage behavior of the first substrate is in compliance with that of the second substrate during reflow.

Abstract: A bump-joining pad (61) is provided to the upper surface of a substrate (45), and a bump (70) of a circuit element (43) is connected to the bump-joining pad. The bump-joining pad (61) is connected to a substrate-side joining section (69) provided to a surface facing a cover by a pattern wiring (64). A microphone chip (42) is mounted on the lower surface of the cover (44). A first joining pad (a bonding pad (48), a cover-side joining section (49)) is provided to a surface of the cover (44) facing the substrate (45), and the microphone chip (42) is connected to the first joining pad by a bonding wire (50). The first joining pad of the cover (44) and the substrate-side joining section (69) of the substrate (45) are joined by a conductive material (65), and as a result, the microphone chip (42) and the circuit element (43) are electrically connected.

Abstract: A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate.

Abstract: A lead frame includes an inner lead area overlapping with a chip mounting area, an outer lead portion having outer leads disposed outside the inner lead area, and an inner lead portion having inner leads disposed in the inner lead area. A semiconductor chip is mounted on the chip mounting area of the lead frame. Electrode pads of the semiconductor chip are electrically connected to inner leads via metal wires. Portions of the inner leads located on an area in the inner lead area except the chip mounting area are depressed.

Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.

Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.

Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.

Abstract: A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes.

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Abstract: An electronic device includes a first chip and a second chip, where each chip has a first conduction terminal on a first surface and a second conduction terminal on a second surface. An insulating body surrounds the first and second chip, a first heat-sink coupled with the first conduction terminals of the first and second chip, and a second heat-sink coupled with the second conduction terminals of the first and second chip. A portion of the first heat-sink and/or the second heat-sink being exposed from the insulating body. The electronic device includes a first conductive lead and a second conductive lead exposed from the insulating body for through-hole mounting of the electronic device on an electronic board, the first conductive lead being coupled with the first heat-sink and the second conductive lead being coupled with the second heat-sink.

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract: A three-dimensional integrated circuit, including a first adhesive bonding layer, a first chip, a second chip, and an inter-stratum thermal pad, is provided. The first adhesive bonding layer has a first surface and a second surface opposite to each other. The first chip is disposed on the first surface of the first adhesive bonding layer. The first chip includes a hot zone. The second chip is disposed on the second surface of the first adhesive bonding layer. The inter-stratum thermal pad is embedded in the first adhesive bonding layer and faces to the hot zone.

Abstract: Provided are semiconductor packages and electronic systems including the same. A first memory chip may be stacked on a first portion of a substrate. A controller chip may be stacked on a second portion of the substrate, which is different from the first portion. At least one first bonding wire may directly connect the first memory chip with the controller chip. At least one second bonding wire may directly connect the first memory chip with the substrate, and may be electrically connected with the at least one first bonding wire.

Abstract: A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.

Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.

Abstract: A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material.

Abstract: A leadless package system includes: an integrated circuit die having contact pads; external contact terminals with a conductive layer and an external coating layer; connections between contact pads in the integrated circuit die and the external contact terminals; and an encapsulant encapsulates the integrated circuit die and the external contact terminals including the external coating layer.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Abstract: Methods and structures related to packaging a chip are disclosed. In one embodiment, a chip package structure includes: (i) a chip having a plurality of first and second contact pads thereon; (ii) a lead frame having a plurality of pins for external connection to the package structure, where the chip is disposed on the lead frame; (iii) a plurality of first bonding wires for connecting the first contact pads to the lead frame; and (iv) a plurality of second bonding wires for connecting the second contact pads to the plurality of pins on the lead frame.

Abstract: A semiconductor device includes: a lead frame; a semiconductor element held by the lead frame; a frame body which is formed on the lead frame to surround the semiconductor element, cover a side surface of the lead frame, and expose a bottom surface of the lead frame; and a protective resin filling a region surrounded by the frame body. The lead frame includes an uneven part formed in a section which is part of an upper surface of the lead frame, and is covered with the frame body.

Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.

Abstract: A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact with the first metal layer, and a conductive pillar disposed on the second metal layer, where a material of the first metal layer is different from a material of the second metal layer, the first metal layer has a first distribution-projected area larger than a second distribution projected-area of the conductive pillar, and the second metal layer has a third distribution-projected area that is the same as the second distribution-projected area of the conductive pillar.