Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.

Abstract: A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.

Abstract: A packaged semiconductor device includes at least first and second lead-fingers. A molded structure forms a cavity and is molded around portions of each of the first and second lead-fingers to thereby mechanically attach each of the first and second lead-fingers to the molded structure. A semiconductor structure (e.g., a IC, chip or die) is attached within the cavity. First and second bond wires respectively providing electrical connections between the semiconductor structure and the first and second lead-fingers. A further portion of each of the first and second lead-fingers is mechanically attached to a bottom surface of the semiconductor structure to inhibit relative mechanical motion between the semiconductor structure, the molded structure and the first and second lead-fingers.

Abstract: A semiconductor module is manufactured by bonding a resin case having a first opening through which surfaces of main circuit terminals and control terminals are exposed, onto a metal heat-dissipating substrate onto which is bonded, a conductive-patterned insulating substrate onto which are bonded, semiconductor chips, the main circuit terminals, and the control terminals; inserting into and attaching to a second opening formed on a side wall constituting a resin case, a resin body having a nut embedded therein to fix the main circuit terminals and the control terminals; and filling the resin case with a resin material. A side wall of the first opening is tapered toward the surface thereof; a tapered contact portion contacting the tapered side wall is disposed on the control terminal; and the resin body having the embedded nut fixes the control terminal having a one-footing structure that is an independent terminal.

Abstract: A semiconductor device has an insulation substrate formed with a conductive pattern; an independent terminal, which is an externally leading terminal, soldered to the conductive pattern of the insulation substrate; a case disposed over the insulation substrate such that a top surface of the independent terminal is exposed; an opening provided on a side surface of the case; a nut glove inserted from the opening so as to be below the independent terminal, and fix the independent terminal; and a first projection part formed on a side surface of the nut glove, and having tapers in a frontward direction and a rearward direction of insertion of the nut glove, respectively. The rearward taper of the first projection part is pressure contacting with a sidewall surface of the opening.

Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.

Abstract: A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter electrode and a collector electrode. The second functional device (3) includes at least one electrode. The module (1) further includes a conductive frame (4). One of the base electrode, the emitter electrode, and the collector electrode of the first functional device (2) is directly connected to the frame (4). The electrode of the second functional device (3) is also directly connected to the frame (4). The frame (4) includes a portion serving as a terminal for external connection.

Abstract: An integrated circuit (IC) package is disclosed comprising a substrate including a plurality of substrate contacts; a semiconductor die including a plurality of die contacts; and a plurality of conductors for providing direct connections between substrate contacts and die contacts, respectively. By having the conductors directly route the connections between the die contacts and substrate contacts, many improvements may be realized including, but not limited to, improved package routing capabilities, reduced die and/or package size, improved package reliability, improved current handling capacity, improved speed, improved thermal performance, and lower costs.

Abstract: Power electronics modules having solder layers with reduced thermal-stress are disclosed. In one embodiment, a power electronics module includes a power electronics device having a first surface, a second surface, a first edge, and a second edge opposite the first edge. The power electronics device has a device length measured from the first edge to the second edge. A first solder layer is adjacent to the first surface of the power electronics device, and a second solder layer is adjacent to the second surface. The first solder layer and the second solder layer have a maximum thickness T along a length that is less than the device length of the power electronics device. A first thermally conductive layer is adjacent to the first solder layer, and a second thermally conductive layer is adjacent to the second solder layer. In some embodiments, the first and second solder layers have tapered portions.

Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.

Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

Abstract: A semiconductor device that can suppress variation of GND potential of a control board and prevent malfunction of IC without restricting a mounting direction of the IC of the control board is provided. In a power module 10 as a semiconductor device in which an insulating board 31 having a power switching element 24 and a control board 22 having IC 50 for controlling the power switching element 24 are vertically provided in a case body 19, GND pins 61 are provided at both the sides of the IC 50, a GND pattern 51 to which the GND pins 61 of the IC 50 are connected is provided in the control board 22, and a GND loop breaking slit 70 as a breaking portion for breaking a GND loop formed by electrical connection of the IC 50, the GND pins 61 at both the sides of the IC 50 and the GND pattern 51 is provided to the GND pattern 51.

Abstract: A power semiconductor element, a high-voltage electrode electrically connected to the power semiconductor element, a heat radiating plate connected to the power semiconductor element and having heat radiation property, a cooling element connected to the heat radiating plate with an insulating film being interposed, and a seal covering the power semiconductor element, a part of the high-voltage electrode, the heat radiating plate, the insulating film, and a part of the cooling element are included. The cooling element includes a base portion of which part is embedded in the seal and a cooling member connected to the base portion. The base portion and the cooling member are separate from each other, and the cooling member is fixed to the base portion exposed through the seal.

Abstract: A semiconductor device is described advantageously making use of the interposer principle. The semiconductor device comprises at least one semiconductor die, a window substrate being an inorganic substrate comprising at least one window-shaped cavity for mounting the at least one semiconductor die, the window substrate having interconnect structures. Furthermore, the at least one semiconductor die is positioned inside the at least one cavity and is connected to the interconnect structures, providing connections to another level of assembly or packaging of the semiconductor device. The invention also relates to a method of manufacturing such a semiconductor device.

Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Abstract: An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit package and the second integrated circuit package. At least one support structure is disposed between the first integrated circuit package and the second integrated circuit package to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical signal connections.

Abstract: A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a terminal portion formed on a surface of the substrate.

Abstract: A welding system component includes a circuit board for the welding system component. An interface has a main riser portion with a fastener passageway formed therethrough. The interface has an extension portion with a terminal passageway formed therethrough. The extension portion is electrically connected to the circuit board with a terminal disposed in the terminal passageway. The extension portion is spaced away from a surface of the circuit board. A capacitor is electrically connected to the main riser portion with a fastener disposed in the fastener passageway.

Abstract: A packaged integrated device can include a die attach pad having a top surface and a bottom surface. A plurality of leads physically and electrically separated from the die attach pad can be positioned at least partially around the perimeter of the die attach pad. An integrated device die can be mounted on the top surface of the die attach pad. A package body can cover the integrated device die and at least part of the plurality of leads, and at least a portion of the bottom surface of each of the plurality of leads can be exposed through the package body. A plating layer can cover substantially the entire width of an etched lower portion of the outer end of each lead and at least the exposed portion of the bottom surface of each lead.

Abstract: A package structure is provided, including: a substrate having a ground pad and an MEMS element; a lid disposed on the substrate for covering the MEMS element; a wire segment electrically connected to the ground pad; an encapsulant encapsulating the lid and the wire segment; and a circuit layer formed on the encapsulant and electrically connected to the wire segment and the lid so as to commonly ground the substrate and the lid, thereby releasing accumulated electric charges on the lid so as to improve the reliability of the MEMS system and reduce the number of I/O connections.

Abstract: Disclosed is a light emitting device package. The light emitting device package includes a substrate including a recess, a light emitting chip on the substrate and a first conductive layer electrically connected to the light emitting chip. And the first conductive layer includes at least one metal layer electrically connected to the light emitting chip on an outer circumference of the substrate.

Abstract: The invention achieves a further downsizing of an actuator control unit. The actuator control unit has a control circuit controlling an actuator, and a bus bar electrically connected to the control circuit and arranged such as to be partially embedded in an inner portion of a resin case and be partially exposed to an outer portion of the resin case. It is preferable to have a projection portion extending in a wiring direction of the bus bar between two bus bars wired adjacently, having a greater height than an embedded plane of the bus bar in the resin case, and made of an insulating material.

Abstract: A microelectronic assembly may include microelectronic devices arranged in a stack and having device contacts exposed at respective front surfaces. Signal conductors having substantial portions extending above the front surface of the respective microelectronic devices connect the device contacts with signal contacts of an underlying interconnection element. A rear surface of a microelectronic device of the stack overlying an adjacent microelectronic device of the stack is spaced a predetermined distance above and extends at least generally parallel to the substantial portions of the signal conductors connected to the adjacent device, such that a desired impedance may be achieved for the signal conductors connected to the adjacent device.

Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.

Abstract: An apparatus provides good bonding between a package structure and a substrate and extended solder bonding life, even under heat stress. Of a lead frame to be used for a package structure having a configuration in which a semiconductor chip, an island of the lead frame, and external connection terminals are sealed with a resin from one surface, and the island and the external connection terminals are exposed on the other surface, the external connection terminals include a first external connection terminal disposed at a central part of each of sides of an outer rim of a semiconductor chip mounting region in which the semiconductor chip is to be mounted and a second external connection terminal outside the first external connection terminal at each of the sides of the outer rim of the semiconductor chip mounting region, wherein the first external connection terminal area exceeds the second external connection terminal's.

Abstract: A sensor module includes a support member having a first flat surface, a second flat surface orthogonally connected to the first flat surface, a third flat surface orthogonally connected to the first flat surface and the second flat surface, and a fourth flat surface opposed to the first flat surface as an attachment surface to an external member, the first flat surface having a support surface depressed from the first flat surface, IC chips having connection terminals on active surface sides with inactive surface sides along the active surfaces respectively attached to the respective surfaces of the support member, and vibration gyro elements having connection electrodes, and the vibration gyro elements are provided on the active surface sides of the IC chips and the connection electrodes are attached to the connection terminals of the IC chips so that principal surfaces are respectively along the respective surfaces of the support member.

Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.

Abstract: An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element.

Abstract: A flip-chip leadframe semiconductor package designed to improve mold flow around the leadframe and semiconductor die. An embodiment of the semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulant covering the leadframe and semiconductor die, wherein a portion of the leadframe that is attached to the semiconductor die is below a portion of the leadframe that enters the encapsulant.

Abstract: A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.

Abstract: A packaging substrate and a semiconductor package each include: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer.

Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.

Abstract: A preamplifier integrated circuit (IC) for a magnetic storage device comprises a plurality of channels, each including at least one preamplifier and a plurality of groups. Each of the groups includes at least one of the channels. A passivation layer is arranged adjacent to at least one interconnecting layer. A plurality of first external connections external to the IC are arranged in openings in the passivation layer, are in contact with at least one of the interconnecting layers, that distribute a first potential to the at least one preamplifier of the plurality of channels, and communicate with the plurality of groups. Each of the plurality of first external connections distributes the first potential to first respective ones of the plurality of groups independently of others of the plurality of groups.

Abstract: Forming a packaged semiconductor device includes placing a semiconductor die attached to a carrier into a mold cavity having an injection port, wherein the semiconductor die has an encapsulant exclusion region on a top surface of the semiconductor die within an outer perimeter of the top surface; and flowing an encapsulant over the semiconductor die and carrier from the injection port, wherein the encapsulant flows around the encapsulant exclusion region to surround the encapsulant exclusion region without covering the encapsulant exclusion region. The encapsulant exclusion region has a first length corresponding to a single longest distance across the encapsulant exclusion region, wherein the first length is aligned, within 30 degrees, to a line defined by a shortest distance between an entry point of the injection port into the mold cavity and an outer perimeter of the encapsulant exclusion region.

Abstract: A housing for a semiconductor chip has an injection molded body, in which an accommodating area for accommodating the semiconductor chip is provided. The injection-molded body has at least one metallization for making electrical contact with the semiconductor chip.

Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.

Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.

Abstract: Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is suppressed. When the semiconductor wafer is cut at the dicing step for the semiconductor wafer, a blade is advanced as follows: in dicing in a first direction (Y-direction in FIG. 12) along a first straight line, the blade is advanced from a first point to a second point. The first point is positioned in a first portion and the second point is opposed to the first point with a second straight line running through the center point of the semiconductor wafer in between.

Abstract: An apparatus that comprises a power ground/arrangement that comprises a first semiconductor die configured as a central processing unit (CPU). The power/ground arrangement further comprises a first metal layer that provides only one of (i) a power signal and (ii) a ground signal, and a second metal layer that provides the other one of (i) the power signal and (ii) the ground signal. The apparatus further comprises a second semiconductor die configured as a memory that is coupled to the power/ground arrangement. The second semiconductor die is configured to receive power signals and ground signals from the power/ground arrangement. The second semiconductor die is further configured to provide signals to the CPU via the power/ground arrangement and to receive signals from the CPU via the power/ground arrangement. The second semiconductor die is coupled to the power/ground arrangement only along a single side of the second semiconductor die.

Abstract: A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.

Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

Abstract: A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a rectangular plane shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a rectangular plane shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode.

Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.

Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.

Abstract: Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements.

Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity.

Abstract: In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.

Abstract: A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged.

Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

Abstract: A semiconductor package includes a first package and a second package, a connection terminal disposed between the first and second packages and including a first solder ball and a second solder ball that are vertically stacked, a solder passivation layer with which a surface of at least one of the first and second solder balls is coated, and a ring-shaped short prevention part surrounding a coupling portion between the first and second solder balls.