Abstract: A heat dissipation structure applied to a substrate with a heat generating element is provided. The heat dissipation structure includes a heat dissipation body and an elastomer. The heat dissipation body includes a connecting portion, where the connecting portion includes a central area and a peripheral area, and the central area is configured to contact with the heat generating element. The elastomer is disposed between the peripheral area and the heat generating element, to form a sealed space, and the sealed space is configured to accommodate a heat-conducting medium.

Abstract: The present disclosure relates to a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate including a first surface and a conductive trace extending over the substrate; a die disposed over the first surface of the substrate; a molding disposed over the first surface of the substrate and covering the die; and a metallic layer surrounding the molding and the substrate, wherein the metallic layer is electrically connected to at least a portion of the conductive trace exposed through the substrate.

Abstract: An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole.

Abstract: A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.

Abstract: A heat sink for an integrated circuit chip. The heat sink includes a base plate and a plurality of fins connected to the base plate. The base plate includes a first segment, a second segment, and a third segment that are sequentially connected; and the first segment and the third segment extend obliquely upward relative to the second segment.

Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.

Abstract: A thin heat pipe structure includes a main body having a chamber. The chamber has a wick structure and a working fluid provided therein, and internally defines an evaporating section and at least one condensing section. The condensing section is extended towards at least one or two ends of the evaporating section. The wick structure is provided with at least one groove. The groove is extended through the wick structure along a thickness direction of the main body to connect to two opposite wall surfaces of the chamber, and also extended along a length direction of the main body to communicate with the condensing section and the evaporating section. With these arrangements, the thin heat pipe structure has an extremely small overall thickness and is flexible.

Abstract: To obtain, in an on-board control device, a shield effect against noise radiated from an electronic component. The present invention includes: an electronic component 103; a metal housing 101 which covers at least a part of the electronic component 103; a metal portion 105 which is provided so that the electronic component 103 is disposed between the metal portion 105 and the metal housing 101; and a shield structure which shields radiation noise from the electronic component 103 by electrostatic capacitive coupling formed between the metal portion 105 and the metal housing 101.

Abstract: A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, a logic die, and a thermal management component. The non-volatile memory die, the volatile memory die, the logic die, and the thermal management component are stacked. The thermal management component can be stacked in between the non-volatile memory die and the logic die, stacked in between the volatile memory die and the logic die, or both.

Abstract: Disclosed is a semiconductor package comprising first and second semiconductor structures spaced apart on a first substrate, a heat sink covering the first and second semiconductor structure and the first substrate, and a thermal interface material layer between the heat sink and the first and second semiconductor structures. The first semiconductor structure includes a first sidewall adjacent to the second semiconductor structure and a second sidewall opposite the first sidewall. The thermal interface material layer includes a first segment between the first and second semiconductor structures and a second segment protruding beyond the second sidewall. A first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first segment is less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second segment.

Abstract: A power electronics module includes an electrically-conductive substrate including a base portion defining a plurality of orifices that extend through the base portion, the plurality of orifices defining a plurality of jet paths extending along and outward from the plurality of orifices, and a plurality of posts extending outward from the base portion, where individual posts of the plurality of posts are positioned between individual orifices of the plurality of orifices, and a power electronics device coupled to the plurality of posts opposite the base portion, the power electronics device defining a bottom surface that is oriented transverse to the plurality of jet paths.

Abstract: A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor includes a substrate, a block bonded on the substrate, a first die bonded on the block, a second die disposed over the first die, and a heat spreader covering the block and having a surface facing toward and proximal to the block. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the block.

Abstract: Some embodiments relate to a semiconductor package. The package includes a substrate having an upper surface and a lower surface. A first chip is disposed over a first portion of the upper surface of the substrate. A second chip is disposed over a second portion of the upper surface of the substrate. A first plurality of carbon nano material pillars are disposed over an uppermost surface of the first chip, and a second plurality of carbon nano material pillars are disposed over an uppermost surface of the second chip. A molding compound is disposed above the substrate, and encapsulates the first chip, the first plurality of carbon nano material pillars, the second chip, and the second plurality of carbon nano material pillars.

Abstract: A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.

Abstract: An electromagnetic wave absorption sheet is arranged to contact an upper surface and side surfaces of an electronic component mounted on a wiring board, a heat conduction plate is arranged to contact the electromagnetic wave absorption sheet, a heat transfer sheet is arranged to contact the heat conduction plate, and a heat dissipation member is arranged to contact the heat transfer sheet. Heat conductive particles contained in the heat transfer sheet contact a flat surface portion of the heat conduction plate. The electromagnetic wave absorption sheet, the heat conduction plate, and the heat transfer sheet are interposed between the heat dissipation member and the electronic component, as a heat conduction member for conducting heat generated in the electronic component and the like to the heat dissipation member.

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

Abstract: A conductive plate has a front surface at a front side and a rear surface at a rear side. The front surface includes a first front surface on which a first arrangement region is disposed and a second front surface on which a second arrangement region is disposed. The first front surface has a height measured from the rear surface that is different from a height of the second front surface measured from the rear surface. Next, first and second bonding materials are respectively applied to the first and second arrangement regions. A first part is bonded to the first arrangement region via the first bonding material, and a second part is bonded to the second arrangement region via the second bonding material. The heights of the first and second arrangement regions set on the front surface on the conductive plate are different from each other.

Abstract: A semiconductor package structure includes a first semiconductor die having an active surface and a passive surface opposite to the active surface, a conductive element leveled with the first semiconductor die, a first redistribution layer (RDL) being closer to the passive surface than to the active surface, a second RDL being closer to the active surface than to the passive surface, and a second semiconductor die over the second RDL and electrically coupled to the first semiconductor die through the second RDL. A first conductive path is established among the first RDL, the conductive element, the second RDL, and the active surface of the first semiconductor die.

Abstract: A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.

Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.

Abstract: The temperature of inverters and power semiconductor devices is detected at high speed and with high accuracy. The electronic control circuit includes a vector instruction circuit for calculating an efficiency value of an inverter corresponding to a torque instruction value, and a temperature estimation circuit for estimating a temperature of the power semiconductor element based on the efficiency value of the inverter and a duty cycle for driving the power semiconductor element constituting the inverter.

Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

Abstract: A structure and a formation method of a package structure are provided. The method includes disposing a semiconductor die structure over a substrate. The method also includes disposing a protective film over the substrate. The protective film has an opening exposing the semiconductor die structure, and sidewalls of the opening surround the semiconductor die structure. The method further includes dispensing an underfill material into the opening to surround the semiconductor die structure.

Abstract: A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip, having a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and one or more supports connected between the first segment and the second segment, and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from an upper surface of the encapsulant. A lower surface of the second segment is flush against the first bond pad.

Abstract: An emitter package can include: a body having a bottom member, side members extending from the bottom member, and a top surface, wherein the body defines a cavity formed into the top surface and located between the bottom member and side members; the cavity having top side walls extending from the top surface to optic shelves, middle side walls extending from the optic shelves to contact shelves, and bottom side walls extending from the contact shelves to a base surface; electrical conductive pads on the base surface in the cavity; emitter chips on the electrical conductive pads, each emitter chip having one or more light emitters; shelf contact pads on the contact shelves; and electrical connector wires connected to and extending between the emitter chips and the shelf contact pads.

Abstract: The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.

Abstract: An integrated circuit package comprising a first substrate having a cavity; a second substrate; and one or more semiconductor device(s) and/or passive component (s) are coupled to the second substrate. The cavity is formed using two opposite side walls of the first substrate where two opposite sides of the cavity are kept open, the one or more semiconductor device(s) and/or passive component(s) is/are electrically coupled using redistribution layers, and the second substrate is located inside the cavity of the first substrate.

Abstract: A package structure includes a substrate, a first die, a second die and a bonding die. The substrate comprises scribe regions and die regions. The die regions are spaced from each other by the scribe regions therebetween. The first die and the second die are within the die regions of the substrate. The bonding die is electrically bonded to the first die and the second die. The top surfaces of the first die and the second die are partially covered by the bonding die.

Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.

Abstract: A chip on film package is disclosed, including a flexible film, a patterned circuit layer, a chip, and a dummy metal layer. The flexible film includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the first surface and electrically connected to the patterned circuit layer. The dummy metal layer covers the second surface capable of dissipating heat of the chip. The dummy metal layer is electrically insulated from the patterned circuit layer.

Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The semiconductor substrate includes a carrier and a conductive post. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The carrier has a through hole extending between the first surface and the second surface. The carrier has a first opening on the lateral surface. The conductive post is disposed within the through hole.

Abstract: Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.

Abstract: A lamp capable of expanding illumination range includes a lighting and cooling module, a reflective cup, a lampshade, a diffuser plate and a wash wall cup. The reflective cup and lampshade are connected to the lighting and cooling module; the lampshade surrounds the reflective cup; the diffuser plate is divided into an oblique circular arc plate and a riser; the circular arc plate has rule gratings formed by convex and concave embossed marks. A front arc wall is built on a side of the wash wall cup, and a rear arc wall is built on the other side. An inlay seam is formed between the front and rear arc walls; the circular arc plate is mounted onto the front arc wall; edges of the riser are plugged into the inlay seam; and the wash wall cup is plugged from the bottom of the lampshade to form the lamp.

Abstract: A lubricating grease composition includes a base oil, a thickener, and a solid lubricant, wherein the base oil is a synthetic hydrocarbon oil with a kinematic viscosity of 600 to 2000 mm2/s at 40° C., the thickener is a barium complex soap, and the solid lubricant is an inorganic fine particle with Mohs hardness of 3 to 6 and an average particle size of 10 to 40 ?m.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: An optical power transfer device with an embedded active cooling chip is disclosed. The device includes a cooling chip made of a semiconductor material, and a first subassembly and a second subassembly mounted on the cooling chip. The cooling chip comprises at least one metallization layer on a portion of a first surface of the cooling chip, at least one inlet through a second surface of the cooling chip, wherein the second surface is opposite to the first surface, at least one outlet through the second surface and one or more micro-channels extending between and fluidly coupled to the at least one inlet and the at least one outlet. A cooling fluid flows through the one or more micro-channels. The first subassembly is mounted on the at least one metallization layer and comprises a laser. The second subassembly comprises a phototransducer configured to receive a laser beam from the laser.

Abstract: A semiconductor package includes a first semiconductor package including a core member having a through-hole, a first semiconductor chip disposed in the through-hole and having an active surface with a connection pad disposed thereon, a first encapsulant for encapsulating at least a portion of the first semiconductor chip, and a connection member disposed on the active surface of the first semiconductor chip and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, a second semiconductor package disposed on the first semiconductor package and including a wiring substrate electrically connected to the connection member, at least one second semiconductor chip disposed on the wiring substrate, and a second encapsulant for encapsulating at least a portion of the second semiconductor chip, and a heat dissipation member covering a lateral surface of the second semiconductor package and exposing an upper surface of the second encapsulant.

Abstract: A semiconductor device includes a semiconductor element, a first conductor bonded to an upper surface of the semiconductor element via a first solder layer, and a second conductor bonded to an upper surface of the first conductor via a second solder layer. The first conductor includes at least one groove formed in a stacking direction of the semiconductor element, the first conductor, and the second conductor on a side surface adjacent to the upper surface of the first conductor.

Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a bump and a dummy bump over a second surface of the first substrate. The dummy bump is close to a first corner of the first substrate, and the dummy bump is wider than the bump. The method includes bonding the first substrate to a second substrate through the bump. The dummy bump is electrically insulated from the chip and the second substrate. The method includes forming a protective layer between the first substrate and the second substrate. The protective layer surrounds the dummy bump and the bump, and the protective layer is between the dummy bump and the second substrate.

Abstract: Techniques that facilitate two-phase liquid cooling of an electronic device are provided. In one example, an apparatus, such as a cold plate device, comprises a first stackable layer and a second stackable layer. The first stackable layer comprises a first channel formed within the first stackable layer. The first channel comprises a first channel width and the first channel receives a coolant fluid via an inlet port of the apparatus. The second stackable layer comprises a second channel that provides a path for the coolant fluid to flow between the first channel and an outlet port of the apparatus. A width of the second channel increases along a flow direction of the coolant fluid that flows between the inlet port and the outlet port.

Abstract: Systems and methods are described herein to thermally regulate laser diodes. During operation, the structure of a laser diode may generate heat, which will affect the stability and accuracy of the output wavelength of the laser diode. During an OFF stage, the structure of the laser diode will then lose heat, creating a thermal gradient as the laser diode is switched between operation and an OFF state. The systems and methods provide constant average heat and a stable thermal gradient by integrating a laser diode power-coupled supply and a heater onto a heatspreader, such that the output wavelength of a coupled laser diode may be stabilized.

Abstract: In semiconductor device, a substrate unit includes an insulating substrate, a first conductor substrate and a second conductor substrate which are disposed on one main surface of the insulating substrate and spaced apart from each other, and a third conductor substrate which is disposed on the other main surface opposite to the one main surface of the insulating substrate. A terminal is connected to a surface of a semiconductor element opposite to the first conductor substrate. The terminal extends from a region above the semiconductor element to a region above the second conductor substrate while being connected to the second conductor substrate. At least a part of the terminal, the substrate unit and the semiconductor element is sealed by a resin. The third conductor substrate is exposed from the resin.

Abstract: The circuit comprises at least one electronic chip (MT, MD), a laminated substrate and heat sink means, the chip being implanted in the substrate and the heat sink means being secured to opposing faces of the substrate. According to the invention, the heat sink means comprise heat-sink-forming bus-bars (BBH, BBL) mounted on the opposing faces of the substrate, each of said bus-bars being formed by a plurality of metal segments (BB1H, BB2H, BB3H, BB4H; BB1L, BB2L, BB3L) secured at spaced-apart positions and interconnected with one another and with a contact face of the electronic chip (MT, MD) by means of a metal layer (MEH, MEL).

Abstract: A high efficiency satellite transmitter comprises an RF amplifier chip in thermal contact with a radiant cooling element via a heat conducting element. The RF amplifier chip comprises an active layer disposed on a high thermal conductivity substrate having a thermal conductivity greater than about 1000 W/mK, maximizing heat conduction out of the RF amplifier chip and ultimately into outer space when the chip is operating within a satellite under normal transmission conditions. In one embodiment, the active layer comprises materials selected from the group consisting of GaN, InGaN, AlGaN, and InGaAlN alloys. In one embodiment, the high thermal conductivity substrate comprises synthetic diamond.

Abstract: A MMIC support and cooling structure having a three-dimensional, thermally conductive support structure having a plurality of surfaces and a circuit having a plurality of heat generating electrical components disposed on a first portion of the surfaces and interconnected by microwave transmission lines disposed on a second portion of the plurality of surfaces of the thermally conductive support structure.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: In a power semiconductor module, a first conductive layer including first to fourth electrodes are formed on one of principal surfaces of an insulating layer, and a conductive substrate functioning as a second conductive layer is formed on the other one of principal surfaces. Current paths are switched by controlling switching of a first transistor and a second transistor disposed on a surface of the first conductive layer thereby performing a power conversion. A capacitor is connected, in a region, between the first electrode and the second electrode. When a current flows in the region through the second conductive layer, a charging/discharging current occurs in the capacitor, which results in magnetic field cancellation.

Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, a heat dissipation member attached to the inactive surface of the semiconductor chip and having a thickness greater than a thickness of the semiconductor chip, an encapsulant encapsulating at least a portion of each of the semiconductor chip and the heat dissipation member, and a connection member disposed on the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads, wherein the heat dissipation member is a complex of carbon and a metal.