With Provision For Cooling The Housing Or Its Contents Patents (Class 257/712)
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Patent number: 9905489Abstract: A semiconductor device is provided comprising a semiconductor element, a case portion housing the semiconductor element and having an opening end on at least some of wall portion, a lid portion covering the opening end of the case portion, and a sealing material sealing the semiconductor element inside the case portion, where a projection portion or a dent portion is provided on a surface of the wall portion close to the sealing material between the opening end and the sealing material. The Purpose is to prevent an oil leakage from a semiconductor device. Also, instead of the projection portion or the dent portion, a semiconductor device is provided with a liquid receiving portion that receives a liquid dripping from the opening end on a surface facing away from the sealing material.Type: GrantFiled: July 26, 2016Date of Patent: February 27, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takahiro Mitsumoto, Akira Iso
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Patent number: 9894804Abstract: An electronic control unit includes a board, a high-heat-generating device, a controller, a heat-dissipating member, and a heat-conducting member. The high-heat-generating device is mounted on a surface of the board. The heat-dissipating member has a surface located facing the surface of the board. The surface of the heat-dissipating member is recessed to form a recess capable of holding the high-heat-generating device. The heat-conducting member is located between the board and the heat-dissipating member and in contact with both the high-heat-generating device and the recess to transfer the heat of the high-heat-generating device to the heat-dissipating member. The recess is shaped to match a shape of the high-heat-generating device.Type: GrantFiled: December 24, 2014Date of Patent: February 13, 2018Assignee: DENSO CORPORATIONInventor: Shinji Shibata
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Patent number: 9879849Abstract: An LED light fixture including a heat-conductive overstructure having upper and lower surfaces and a plurality of upwardly-protruding elongate fins which extend along the upper surface adjacent to at least one opening through the fixture permitting air flow from beneath the lower surface to above the upper surface. An LED light source is secured with respect to the lower surface. The fins have heights which gradually increase toward fin-ends proximal to the at least one opening.Type: GrantFiled: April 2, 2015Date of Patent: January 30, 2018Assignee: Cree, Inc.Inventors: Brian Kinnune, David P. Goelz, Kurt S. Wilcox, Craig Raleigh
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Patent number: 9881877Abstract: Disclosed herein is an electronic circuit package includes a substrate, an electronic component mounted on a surface of the substrate, and a magnetic mold resin covering the surface of the substrate so as to embed therein the electronic component. The magnetic mold resin includes a resin material and a filler blended in the resin material in a blended ratio of 30 vol. % or more to 85 vol. % or less. The filler includes a magnetic filler containing Fe and 32 wt. % or more and 39 wt. % or less of a metal material contained mainly of Ni, thereby a thermal expansion coefficient of the magnetic mold resin is 15 ppm/° C. or less.Type: GrantFiled: November 16, 2016Date of Patent: January 30, 2018Assignee: TDK CORPORATIONInventor: Kenichi Kawabata
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Patent number: 9876152Abstract: This disclosure discloses a light-emitting device. The light-emitting device includes: a heat-dissipating structure having a first part and a second part separated from the first part; a light-emitting unit including a light-emitting element with a first pad formed on the first part; and a first transparent enclosing the light-emitting element and having a sidewall; and an adhesive material covering a portion of the sidewall.Type: GrantFiled: May 26, 2015Date of Patent: January 23, 2018Assignee: EPISTAR CORPORATIONInventors: Min-Hsun Hsieh, Biing-Jye Lee, Yih-Hua Renn, Jai-Tai Kuo
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Patent number: 9860987Abstract: An electronic assembly comprises a semiconductor device that has conductive pads on a semiconductor first side and a metallic region on a semiconductor second side opposite the first side. A lead frame provides respective separate terminals that are electrically and mechanically connected to corresponding conductive pads. A first heat sink comprises a first component having a mating side. A portion of the mating side is directly bonded with the metallic region of the semiconductor device. A circuit board has an opening for receiving the semiconductor device. The lead frame extends outward toward the circuit board or a board first side of the circuit board.Type: GrantFiled: April 17, 2015Date of Patent: January 2, 2018Assignee: DEERE & COMPANYInventors: Brij N. Singh, Thomas Roan, Andrew D. Wieland, Neal D. Clements
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Patent number: 9854678Abstract: An electronic device is provided which includes a printed circuit board (PCB) including a non-conductive layer that forms at least a portion of a first surface, and a conductive layer arranged between the first surface and a second surface, an electronic component arranged on a first area of the first surface of the PCB, a conductive shield structure arranged on the PCB to cover the first area and the electronic component on the PCB, a support structure connected to the PCB and including a first part that faces a portion of one side of the conductive shield structure, and a cable extending along the one side of the conductive shield structure, inserted between the support structure and the portion of the one side of the conductive shield structure, and including at least one conductive line and an insulation layer that covers the at least one conductive line.Type: GrantFiled: December 1, 2016Date of Patent: December 26, 2017Assignees: Samsung Electronics Co., Ltd, Pocons Co., LtdInventors: Byoung-ryoul Song, Eui-suck Sung
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Patent number: 9847274Abstract: According to an exemplary aspect an electronic module is provided, wherein the electronic module comprises an electronic chip comprising at least one electronic component, a spacing element comprising a main surface arranged on the electronic chip and being in thermally conductive connection with the at least one electronic component, and a mold compound at least partially enclosing the electronic chip and the spacing element, wherein the spacing element comprises a lateral surface which is in contact to the mould compound and comprises surface structures.Type: GrantFiled: December 12, 2016Date of Patent: December 19, 2017Assignee: Infineon Technologies AGInventors: Frank Winter, Ottmar Geitner, Ivan Nikitin, Jürgen Högerl
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Patent number: 9847275Abstract: A method of forming metallic pillars between a fluid inlet and outlet for two-phase fluid cooling. The method may include; forming an arrangement of metallic pillars between two structures, the metallic pillars are electrically connected to metallic connecting lines that run through each of the two structures, the arrangement of metallic pillars located between a fluid inlet and a fluid channel, the fluid channel having channel walls running between arrangements of the metallic pillars and a fluid outlet, whereby a fluid passes through the arrangement of metallic pillars to flow into the fluid channel.Type: GrantFiled: December 21, 2015Date of Patent: December 19, 2017Assignee: International Business Machines CorporationInventors: Timothy J. Chainer, Pritish R. Parida, Fanghao Yang
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Patent number: 9842776Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.Type: GrantFiled: January 13, 2016Date of Patent: December 12, 2017Assignee: NXP B.V.Inventors: John Suman Nakka, Tonny Kamphuis, Roelf Anco Jacob Groenhuis
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Patent number: 9842808Abstract: A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe.Type: GrantFiled: October 4, 2012Date of Patent: December 12, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: HanGil Shin, NamJu Cho, HeeJo Chi
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Patent number: 9842796Abstract: An electronic module including a semiconductor unit situated in a plastic housing, an electrically conductive plate system, via which the semiconductor unit may be supplied with electrical power, the electrically conductive plate system being connected in a planar fashion to a heat-generating integrated circuit of the semiconductor unit via a heat coupler; and the electrically conductive plate system being designed in such a way that it dissipates the heat generated by the heat-generating integrated circuit of the semiconductor unit to the plastic housing. A method for manufacturing a corresponding electronic module is also described.Type: GrantFiled: June 8, 2015Date of Patent: December 12, 2017Assignee: ROBERT BOSCH GMBHInventor: Thomas Schneider
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Patent number: 9842829Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip package stacked over the substrate. The chip package structure includes first conductive bumps arranged between and in direct contact with the chip package and the substrate providing a clearance. The chip package structure includes a chip structure having a first face and an opposing second face arranged in the clearance between the chip package and the substrate and adjacent to the first conductive bumps. The chip structure contains at least one chip. The chip package structure includes a solder cap connecting the first face of the chip structure and the chip package. The chip package structure includes a second conductive bump connecting the second face of the chip structure and the substrate.Type: GrantFiled: September 20, 2016Date of Patent: December 12, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Yun Chen, Hsien-Wei Chen, An-Jhih Su
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Patent number: 9828239Abstract: A method of making a system-in-package device, and a system-in-package device is disclosed. In the method, at least one first species die with predetermined dimensions, at least one second species die with predetermined dimensions, and at least one further component of the system-in-device is included in the system-in package device. At least one of the first and second species dies is selected for redimensioning, and material is added to at least one side of the selected die such that the added material and the selected die form a redimensioned die structure. A connecting layer is formed on the redimensioned die structure. The redimensioned die structure is dimensioned to allow mounting of the non-selected die and the at least one further component into contact with the redimensioned die structure via the connecting layer.Type: GrantFiled: September 4, 2015Date of Patent: November 28, 2017Assignee: MURATA ELECTRONICS OYInventors: Heikki Kuisma, Sami Nurmi
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Patent number: 9829660Abstract: There is provided an optical module. The optical module includes a light source, a wave guide to which beam output from the light source is input, a lens system configured to optically combining the light source and the wave guide, a first lens mount positioned between the light source and the lens system in an optical axis of the light source, a first adhesive configured to fix the lens system to the first lens mount, a second lens mount positioned between the wave guide and the lens system in the optical axis of the light source, and a second adhesive configured to fix the lens system to the second lens mount. Therefore, it is possible to precisely align light, to manufacture the optical module with small expenses, and to simplify processes and equipment.Type: GrantFiled: July 14, 2016Date of Patent: November 28, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong Jin Lee, Kwon-Seob Lim, Dae Seon Kim, Sun-Goo Lee
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Patent number: 9831540Abstract: Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assists in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assists in impedance matching.Type: GrantFiled: September 30, 2011Date of Patent: November 28, 2017Assignee: Aviat U.S., Inc.Inventors: Jayesh Nath, Ying Shen
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Patent number: 9832857Abstract: Provided are interconnect circuits for combined electrical and thermal energy transfer to devices connected to these circuits. Also provided are methods of fabricating such interconnect circuits. An interconnect circuit may include an electro-thermal conductor and at least one insulator providing support to different portions of the conductor with respect to each other. The insulator may include one or more openings for electrical connections and/or heat exchange with the electro-thermal conductor. The portions of the conductor may be electrically isolated from each other in the final circuit. Initially, these portions may be formed from the same conductive sheet, such as a metal foil having a thickness of at least about 50 micrometers. This thickness ensures sufficient thermal transfer in addition to providing excellent electrical conductance. In some embodiments, the conductor may include a surface coating to protect its base material from oxidation, enhancing electrical connections, and/or other purposes.Type: GrantFiled: September 8, 2016Date of Patent: November 28, 2017Assignee: CelLink CorporationInventors: Kevin Michael Coakley, Malcolm Brown
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Patent number: 9825427Abstract: An optical module providing a semiconductor optical amplifier (SOA), and a process to assembly the optical module are disclosed. The optical module provides front and rear coupling units each optically coupled with the SOA and fixed to the housing enclosing the SOA. The housing has a slim wall fixing a lens holder soldered to the slim wall. The front and/or rear coupling unit is fixed to the lens holder by YAG laser welding after the active alignment by using a spontaneous emission of the SOA, and amplified emission of externally provided test beam.Type: GrantFiled: March 17, 2017Date of Patent: November 21, 2017Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Yasuyuki Yamauchi
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Patent number: 9810407Abstract: A light emitting diode (LED) module is in thermal communication with front and back heat sinks for dissipation of heat therefrom. The LED module is physically held in place with at least the back heat sink. A mounting ring and locking ring can also be used to hold the LED module in place and in thermal communication with the back heat sink. Key pins and key holes are used to prevent using a high power LED module with a back heat sink having insufficient heat dissipation capabilities required for the high power LED module. The key pins and key holes allow lower heat generating (power) LED modules to be used with higher heat dissipating heat sinks, but higher heat generating (power) LED modules cannot be used with lower heat dissipating heat sinks.Type: GrantFiled: July 22, 2016Date of Patent: November 7, 2017Assignee: Cooper Technologies CompanyInventor: Grzegorz Wronski
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Patent number: 9806015Abstract: A semiconductor package includes first bump pads on a first surface of an interconnection structure layer, elevated pads thicker than the first bump pads on the first surface of the interconnection structure layer, a first semiconductor device connected on the first bump pads, through mold ball connectors connected on the elevated pads, respectively, a molding layer disposed covering the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors, outer connectors respectively attached to the through mold ball connectors, and a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.Type: GrantFiled: January 30, 2017Date of Patent: October 31, 2017Assignee: SK hynix Inc.Inventors: Ki Jun Sung, Jong Hoon Kim, Han Jun Bae
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Patent number: 9781851Abstract: An electronic device includes a framework defining a number of receiving grooves and a number of modules detachably retained in the receiving grooves. Each receiving groove has a respective notch at a bottom thereof. Each of the modules includes an insulative housing defining a receiving room, a cover having an opening, and an elastic member received in the receiving room. The elastic member has a tuber extending through the opening to engage the notch and a pair of ear portions welded on an inner surface of the cover.Type: GrantFiled: July 13, 2016Date of Patent: October 3, 2017Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITEDInventor: Shun-Jung Chuang
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Patent number: 9780020Abstract: A wiring substrate includes a wiring layer located on an insulation layer, and a protective insulation layer covering the wiring layer and the insulation layer. The protective insulation layer includes an opening that partially exposes the wiring layer. The wiring layer includes first and second metal layers. The first metal layer is located at a position corresponding to the opening and has a larger contour than the opening in a plan view. The second metal layer includes a pad portion, which covers upper and side surfaces of the first metal layer, and a wiring portion. The opening is extended in the protective insulation layer from an upper surface of the protective insulation layer to the upper surface of the pad portion by a distance that is shorter than that from the upper surface of the protective insulation layer to an upper surface of the wiring portion.Type: GrantFiled: December 1, 2016Date of Patent: October 3, 2017Assignee: Shinko Electric Industries Co., Ltd.Inventor: Hiroshi Shimizu
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Patent number: 9779866Abstract: Electromagnetic actuator components include a magnetic core, a conductor assembled with the core and defining a winding completing a number of turns, and a movable component that may be displaced by a magnetic field. The conductor is fabricated from a composite material including carbon nanotubes having an improved conductivity. The conductor has a cross section defined by an effective diameter. The conductor is fabricated to have performance parameters that are selected in view of a function of a ratio of conductivity and/or a function of a ratio of effective diameter of the composite conductor material relative to a reference conductor material as conventionally used in an electromagnetic actuator fabrication.Type: GrantFiled: October 10, 2014Date of Patent: October 3, 2017Assignee: COOPER TECHNOLOGIES COMPANYInventor: Frank Anthony Doljack
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Patent number: 9775248Abstract: A display device including a flexible circuit board including an insulation film, the insulation film including an input pad part and an output pad part on a first side thereof; a printed circuit board including a first pad part, the first pad part being connected to the input pad part; and a display panel including a second pad part, the second pad part being connected to the output pad part, wherein the input pad part includes a plurality of input pads that are arranged in at least two pad columns, and the flexible circuit board includes a plurality of dummy layers aligned with the plurality of input pads on a second side of the insulation film, the second side being an opposite side to the first side.Type: GrantFiled: September 23, 2015Date of Patent: September 26, 2017Assignee: SAMSUNG DISPLAY CO., LTD.Inventor: Dong-Ho Kim
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Patent number: 9768096Abstract: A mobile terminal is provided. The mobile terminal includes a circuit board, where a chip is disposed on a first surface of the circuit board. A groove is provided on a second surface of the circuit board. The mobile terminal further includes: a heat pipe that is disposed in the groove. One end of the heat pipe extends to a side wall of the circuit board or outside a side wall of the circuit board.Type: GrantFiled: March 20, 2014Date of Patent: September 19, 2017Assignee: Huawei Device Co., Ltd.Inventors: Longping Yan, Konggang Wei, Hualin Li
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Patent number: 9751753Abstract: Integration of active devices with passive components and MEMS devices is disclosed. An integrated semiconductor structure includes an active device having a device top electrode connected to a conductive jumper by a device-side via/interconnect metal stack. The integrated semiconductor structure also includes a passive component having a component bottom plate connected to the conductive jumper by a component side via/interconnect metal stack. The component bottom plate is situated at an intermediate metal level higher than the device top electrode, and the conductive jumper is situated at a connecting metal level higher than the component bottom plate. The conductive jumper reduces undesirable charge flow into the active device during fabrication of the passive component. The passive component can be, for example, a MEMS device.Type: GrantFiled: September 2, 2016Date of Patent: September 5, 2017Assignee: Newport Fab, LLCInventors: Michael J. DeBar, David J. Howard, Jeff Rose
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Patent number: 9748184Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.Type: GrantFiled: October 15, 2015Date of Patent: August 29, 2017Assignee: Micron Technology, Inc.Inventors: Shing-Yih Shih, Hsu Chiang
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Patent number: 9743555Abstract: Embodiments of a silicon-based heat dissipation device and a chip module assembly are described. An apparatus may include a silicon-based heat dissipation device, an extended device coupled to the silicon-based heat-dissipation device and heat-generating devices mounted on the silicon-based heat dissipation device. The silicon-based heat dissipation device may include a base portion having a first primary side and a second primary side opposite the first primary side. The silicon-based heat dissipation device may also include a protrusion portion on the first primary side of the base portion and protruding therefrom. The protrusion portion may include multiple fins. The base portion may include a slit opening with a first heat-generating device of the heat-generating devices on a first side of the slit opening and a second heat-generating device of the heat-generating devices on a second side of the slit opening opposite the first side of the slit opening.Type: GrantFiled: October 1, 2015Date of Patent: August 22, 2017Inventors: Gerald Ho Kim, Jay Eunjae Kim
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Patent number: 9723755Abstract: A drive unit for driving a motor has a component assembly including a main circuit board having a component side and a solder side, one or more main circuit conductors formed in at least one layer of the main circuit board, a power component module including one or more power components, the power component module having electrical connection terminals for connecting the power component(s) to the one or more main circuit conductors of the main circuit board and a cooling plate coupled to the power component(s) in a manner enabling transfer of heat from the power component(s) to the cooling plate. The power component module is mounted to the component side of the main circuit board. The component assembly further includes a heat sink mounted on the cooling plate and a fan mounted on the heat sink.Type: GrantFiled: September 25, 2015Date of Patent: August 1, 2017Assignee: KONE CORPORATIONInventor: Pasi Raassina
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Patent number: 9721866Abstract: A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.Type: GrantFiled: November 18, 2015Date of Patent: August 1, 2017Assignee: SOCIONEXT INC.Inventors: Takeshi Imamura, Nobutaka Shimizu, Yasunori Fujimoto
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Patent number: 9711429Abstract: In a semiconductor device, an insulating substrate housed in an housing opening portion of a resin case includes an insulating board, a first metal layer formed on the upper surface of the insulating board, a second metal layer which is formed on an outer peripheral edge portion of the upper surface of the insulating board and is in contact with a level difference portion, and a third metal layer formed on the under surface of the insulating board and leveled with or protruding from the under surface of the resin case. The first and second metal layers are formed by etching copper foil formed on the insulating board so that these metal layers have the same thickness. The thickness of the second metal layer may be changed relatively freely according to the housing depth of the resin case. Thus, the semiconductor device may be made thin.Type: GrantFiled: May 10, 2016Date of Patent: July 18, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tadanori Yamada
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Patent number: 9711426Abstract: A semiconductor device includes a first die including a first pad and a first passivation layer, a second die including a second pad and a second passivation layer, and an encapsulant surrounding the first die and the second die. Surfaces of the first die are not coplanar with corresponding surfaces of the second die. A dielectric layer covers at least portions of the first passivation layer and the second passivation layer, and further covers the encapsulant between the first die and the second die. The encapsulant has a first surface. The dielectric layer has a second surface adjacent to the first passivation layer, the second passivation layer and the encapsulant, and further has a third surface opposite the second surface. The semiconductor device further includes a redistribution layer electrically connected to the first pad and the second pad and disposed above the third surface of the dielectric layer.Type: GrantFiled: October 6, 2016Date of Patent: July 18, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chung-Hsuan Tsai, Chuehan Hsieh
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Patent number: 9704774Abstract: A thermal management structure for a device is provided. The thermal management structure includes electroplated metal, which connects multiple contact regions for a first contact of a first type located on a first side of the device. The electroplated metal can form a bridge structure over a contact region for a second contact of a second type without contacting the second contact. The thermal management structure also can include a layer of insulating material located on the contact region of the second type, below the bridge structure.Type: GrantFiled: December 11, 2013Date of Patent: July 11, 2017Assignee: SENSOR ELECTRONIC TECHNOLOGY, INC.Inventors: Yuri Bilenko, Michael Shur, Remigijus Gaska
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Patent number: 9685392Abstract: A radiofrequency high-output device includes: a base plate having a mount portion and a flange portion; a frame joined to an upper surface of the mount portion; and a semiconductor chip mounted on the upper surface of the mount portion in the frame, wherein a cut or an aperture in which a screw is inserted to fix the base plate is provided in the flange portion, and a groove is provided between the mount portion and the flange portion of the base plate.Type: GrantFiled: February 16, 2016Date of Patent: June 20, 2017Assignee: Mitsubishi Electric CorporationInventors: Katsumi Miyawaki, Tatsuto Nishihara
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Patent number: 9685554Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first ridge portion embedded in the first concave and the drain includes a second ridge portion embedded in the second concave, wherein the first and second ridge portions extend along a height direction of the semiconductor fin.Type: GrantFiled: March 7, 2016Date of Patent: June 20, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
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Patent number: 9653438Abstract: An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer.Type: GrantFiled: August 21, 2014Date of Patent: May 16, 2017Assignee: General Electric CompanyInventors: Paul Alan McConnelee, Arun Virupaksha Gowda
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Patent number: 9646914Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.Type: GrantFiled: December 3, 2015Date of Patent: May 9, 2017Assignee: STMicroelectronics SAInventors: Pierre Bar, Perceval Coudrain
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Patent number: 9645332Abstract: Configurations are described for creating and using separable optical feedthroughs. These are especially useful in their at least semi-hermetic form when integrated with implantable photomedical devices. One embodiment is directed to a system for operatively coupling an optical output from a light source positioned inside of a sealed housing to an external optical fiber, comprising: a first optical fiber disposed adjacent to the light source and configured to receive at least a portion of the optical output; a second optical fiber operatively coupled to the first optical fiber and configured to capture at least a portion of an output from the first optical fiber; a primary seal operatively coupled to the housing between the light source and the second optical fiber that is at least partially transparent; and a secondary seal positioned between the second optical fiber and the environment.Type: GrantFiled: July 29, 2015Date of Patent: May 9, 2017Assignee: Circuit Therapeutics, Inc.Inventors: Greg Stahler, David Angeley, Brian Andrew Ellin
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Patent number: 9640469Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).Type: GrantFiled: September 10, 2015Date of Patent: May 2, 2017Assignee: NXP USA, Inc.Inventors: George R. Leal, Tim V. Pham
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Patent number: 9632294Abstract: Micro-channel-cooled UV curing systems and components thereof are provided. According to one embodiment, a lamp head module includes a high aspect ratio, high fill factor array of light emitting devices and a submount. The array includes multiple groups of electrically seriesed light emitting devices that are connected in electrical parallel. The submount is of monolithic construction and includes multiple L-shaped patterned circuit material layers. Each of the L-shaped patterned circuit material layers includes an arm portion and a stem portion. The arm portion functions as a light emitting device bond pad and the stem portion functions as a wire bond pad and a circuit trace. Each light emitting device of a group is affixed to a corresponding arm portion of the submount. The stem portions are located external to the array, run parallel to the length of the array and perform a primary current carrying function for current flow between adjacent light emitting devices of the group.Type: GrantFiled: July 9, 2014Date of Patent: April 25, 2017Assignee: Heraeus Noblelight America LLCInventor: Jonathan S. Dahm
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Patent number: 9634215Abstract: Embodiments provide a light emitting device package including a package body having a through-hole; a radiator disposed in the through-hole and including an alloy layer having Cu; and a light emitting device disposed on the radiator, wherein the alloy layer includes at least one of W or Mo, and wherein the package body includes cavity including a sidewall and a bottom surface, and wherein the through-hole is formed in the bottom surface.Type: GrantFiled: October 16, 2015Date of Patent: April 25, 2017Assignee: LG Innotek Co., Ltd.Inventors: Su Jung Jung, Yon Tae Moon, Young Jun Cho, Son Kyo Hwang, Byung Mok Kim, Seo Yeon Kwon
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Patent number: 9633869Abstract: A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.Type: GrantFiled: August 16, 2013Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sao-Ling Chiu, Kuo-Ching Hsu, Wei-Cheng Wu, Ping-Kang Huang, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu
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Patent number: 9622351Abstract: It is aimed to reduce the electrical field intensity at a laminate substrate on which a semiconductor device is placed. A semiconductor module includes a laminate substrate including an insulative plate, a circuit board provided on a first surface of the insulative plate and a metal plate provided on a second surface that is opposite to the first surface, and an interconnecting substrate that is provided so as to oppose the laminate substrate and that includes a metal layer. Here, the insulative plate extends more outside than an outer edge portion of the circuit board, and the metal layer has a region overlapping the outer edge portion of the circuit board and extends more outside than the outer edge portion of the circuit board.Type: GrantFiled: March 3, 2016Date of Patent: April 11, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventor: Kyohei Fukuda
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Patent number: 9613885Abstract: A cooling apparatus includes a plurality of discrete modules and a plastic housing. Each module includes a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound and a first cooling plate at least partly uncovered by the mold compound. The plastic housing surrounds the periphery of each module to form a multi-die module. The plastic housing includes a first singular plastic part which receives the modules and a second singular plastic part attached to a periphery of the first plastic part. The second plastic part has cutouts which expose the first cooling plates and a sealing structure containing a sealing material which forms a water-tight seal around the periphery of each module at a side of the modules with the first cooling plates.Type: GrantFiled: March 3, 2015Date of Patent: April 4, 2017Assignee: Infineon Technologies AGInventors: Inpil Yoo, Andreas Grassmann
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Patent number: 9595992Abstract: An electronic apparatus includes a cover panel and a case, and at least a board disposed therebetween. A plurality of components are disposed on a board and have heights different from one another. A gap reduction member is disposed so as to face the plurality of components. Steps are formed on the gap reduction member in accordance with the heights of the plurality of components which faces the plurality of components to reduce breakage of a cover panel of the electronic apparatus.Type: GrantFiled: April 8, 2016Date of Patent: March 14, 2017Assignee: KYOCERA CorporationInventors: Katsumi Arao, Ryosuke Iwaya
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Patent number: 9596769Abstract: A multilayer circuit board includes a first substrate and a second substrate in stack. The first substrate is provided with a first pad, a second pad, and a first sub-circuit. The first pad and the second pad are electrically connected to the first sub-circuit. The second substrate has a top surface, a bottom surface, and an opening. The bottom surface of the second substrate is attached to the top surface of the first substrate. The opening extends from the top surface to the bottom surface of the second substrate. The first pad of the first substrate is in the opening of the second substrate; the second pad of the first substrate is not covered by the second substrate. The second substrate further provided with a pad on the top surface and a second sub-circuit electrically connected to the pad of the second substrate.Type: GrantFiled: February 11, 2015Date of Patent: March 14, 2017Assignee: MPI CORPORATIONInventors: Wei-Cheng Ku, Jun-Liang Lai, Chih-Hao Ho
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Patent number: 9564384Abstract: A cooling apparatus includes a plurality of discrete modules and a plastic housing. Each module includes a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound and a first cooling plate at least partly uncovered by the mold compound. The plastic housing surrounds the periphery of each module to form a multi-die module. The plastic housing includes a first singular plastic part which receives the modules and a second singular plastic part attached to a periphery of the first plastic part. The second plastic part has cutouts which expose the first cooling plates and a sealing structure containing a sealing material which forms a water-tight seal around the periphery of each module at a side of the modules with the first cooling plates.Type: GrantFiled: March 3, 2015Date of Patent: February 7, 2017Assignee: Infineon Technologies AGInventors: Inpil Yoo, Andreas Grassmann
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Patent number: 9553036Abstract: A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer covers the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.Type: GrantFiled: July 9, 2015Date of Patent: January 24, 2017Assignee: Powertech Technology Inc.Inventors: Shou-Chian Hsu, Hiroyuki Fujishima
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Patent number: 9551834Abstract: A method to assemble a transmitter optical module is disclosed, where the optical module installs two lenses, one of which concentrates an optical beam emitted from a laser diode, while, the other collimates the optical beam concentrated by the former lens. The method has a feature that the first lens is firstly positioned in a point to collimate the optical beam coming from the laser diode, then, moved to a point, which is apart from the former point with respect to the laser diode, to concentrate the optical beam. The process performs the steps to position the lens by a jig to extract the optical beam passing through the first lens outside of the housing.Type: GrantFiled: January 31, 2014Date of Patent: January 24, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Munetaka Kurokawa, Tomoya Saeki, Yasushi Fujimura
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Patent number: 9548264Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.Type: GrantFiled: January 11, 2016Date of Patent: January 17, 2017Assignee: Intel CorporationInventors: Mihir K. Roy, Stefanie M. Lotz, Wei-Lun Kane Jen