Abstract: A resistivity of an epitaxial layer in a trench is changed in a stepwise manner by reducing a quantity of an impurity diffused into the epitaxial layer in the trench from a semiconductor wafer in a stepwise manner, thereby suppressing an influence of auto-doping from the semiconductor wafer. An epitaxial layer 17 is grown in a trench 16 of a semiconductor wafer 10 having a trench structure by gradually reducing a temperature in a temperature in the range of 400 to 1150° C. by a vapor growth method while supplying a silane gas as a raw material gas, thereby filling the epitaxial layer 17 in the trench 16.

Abstract: Trenches are formed in a silicon substrate by etching exposed portions of the silicon substrate. After covering areas on which deposition of Si:C containing material is to be prevented, selective epitaxy is performed in a single wafer chamber at a temperature from about 550° C. to about 600° C. employing a limited carrier gas flow, i.e., at a flow rate less than 12 standard liters per minute to deposit Si:C containing regions at a pattern-independent uniform deposition rate. The inventive selective epitaxy process for Si:C deposition provides a relatively high net deposition rate a high quality Si:C crystal in which the carbon atoms are incorporated into substitutional sites as verified by X-ray diffraction.

Abstract: A nonvolatile semiconductor storage device is provided in which memory cells comprising PN junction diodes having satisfactory rectifying characteristics are arranged in three dimensions. The semiconductor storage device includes: a first wire which extends in one direction; a second wire which extends in a direction intersecting the first wire; and a memory cell which is positioned at a portion of intersection of the first wire with the second wire between the first wire and the second wire, the memory cell comprising a storage element and a PN junction diode connected thereto, positioned on a side of the second wire used in selecting the memory cell, and a P-type semiconductor forming the PN junction diode forms a portion of the second wire, wherein a plurality of structures, each structure comprising the first wire, the second wire, and the memory cell is provided three-dimensionally.

Abstract: A method of surface treatment for silicon material. The method includes providing a first silicon material having a surface region. The first silicon material has a first purity characteristics and a first surface roughness characteristics. A chemical polishing process is perform to the surface region to cause the surface region to have a second roughness characteristics. Thereafter, a chemical leaching process is performed to the surface region to cause the first silicon material in a depth within a vicinity of the surface region to have a second purity characteristics. A polysilicon material characterized by a grain size greater than about 0.1 mm is formed using a deposition process overlying the surface region.

Abstract: A multilayer structure, comprises a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon having the composition Si1-xGex and having a lattice constant which differs from the lattice constant of silicon, and a thin interfacial layer deposited on the SiGe layer and having the composition Si1-yGey, which thin interfacial layer binds threading dislocations, and at least one further layer deposited on the interfacial layer.

Abstract: The present invention relates to alternative methods for the production of crystalline silicon compounds and/or alloys such as silicon carbide layers and substrates.

Abstract: The invention provides a high temperature (about 1150° C. or greater) annealing process for converting thick polycrystalline Si layers on the order of 1 ?m to 40 ?m on a single crystal seed layer into thick single crystal Si layers having the orientation of the seed layer, thus allowing production of thick Si films having the quality of single crystal silicon at high rates and low cost of processing. Methods of integrating such high temperature processing into solar cell fabrication are described, with particular attention to process flows in which the seed layer is disposed on a porous silicon release layer. Another aspect pertains to the use of similar high temperature anneals for poly-Si grain growth and grain boundary passivation. A further aspect relates to structures in which these thick single crystal Si films and passivated poly-Si films are incorporated.

Abstract: A method of forming a multijunction solar cell includes providing a substrate, forming a first subcell by depositing a nucleation layer over the substrate and a buffer layer including gallium arsenide (GaAs) over the nucleation layer, forming a middle second subcell having a heterojunction base and emitter disposed over the first subcell and forming first and second tunnel junction layers between the first and second subcells. The first tunnel junction layer includes GaAs over the first subcell and the second tunnel junction layer includes aluminum gallium arsenide (AlGaAs) over the first tunnel junction layer. The method further includes forming a third subcell having a homojunction base and emitter disposed over the middle subcell.

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.

Abstract: Methods for forming embedded epitaxial layers containing silicon and carbon are disclosed. Specific embodiments pertain to the formation embedded epitaxial layers containing silicon and carbon on silicon wafers. In specific embodiments an epitaxial layer of silicon and carbon is non-selectively formed on a substrate or silicon wafer, portions of this layer are removed to expose the underlying substrate or silicon wafer, and an epitaxial layer containing silicon is formed on the exposed substrate or silicon wafers. In specific embodiments, gates are formed on the resulting silicon-containing epitaxial layers.

Abstract: A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.

Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.

Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrificial growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

Abstract: A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 107 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface.

Abstract: Dual channel heterostructures comprising strained Si and strained Ge-containing layers are disclosed, along with methods for producing such structures. In preferred embodiments, a strain-relaxed buffer layer is deposited on a carrier substrate, a strained Si layer is deposited over the strain-relaxed buffer layer and a strained Ge-containing layer is deposited over the strained Si layer. The structure can be transferred to a host substrate to produce the strained Si layer over the strained Ge-containing layer. By depositing the Si layer first, the process avoids Ge agglomeration problems.

Abstract: A method for manufacturing a semiconductor including the steps of supplying a substrate having a support with one face supporting a strained silicon thin layer; forming a first mask on a portion of the strained silicon thin layer; epitaxy of Si1-xGex on the portion of the layer not masked by the first mask; condensating germanium to obtain a strained germanium layer, the strained germanium layer then covered by a silicon oxide layer; eliminating the first mask and of the silicon oxide layer thereby exposing a semi-conducting thin layer; forming a second mask on the semi-conducting thin layer exposed via the previous step, the second mask protecting a region of the exposing a remaining strained germanium portion; epitaxial growing germanium on the remaining strained germanium portion; and removing the second mask.

Abstract: There is provided a method for producing a multijunction solar cell having four-junctions, the method allowing the area of a device to be increased. On a nucleation site formed on a substrate 2, is grown a semiconductor 2a comprising the same material as the substrate 2 in the shape of a wire. On the semiconductor 2a, are successively grown semiconductors 3, 4, 5, and 6 with a narrower band gap in the shape of a wire. The semiconductor 3 may be directly grown in the shape of a wire on the nucleation site formed on the substrate 2. It is preferred to form the nucleation site by forming an amorphous SiO2 coating 8a on the substrate 2 and etching a part of the amorphous SiO2 coating 8a. Further, it is preferred to form an insulating film 8 in the region except the nucleation sites on the substrate 2 by allowing the amorphous SiO2 coating 8a to remain therein. The semiconductor 2a is GaP; the semiconductor 3 is Al0.3Ga0.7As; the semiconductor 4 is GaAs; the semiconductor 5 is In0.3Ga0.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) comprising silicon is provided with an n-type doped semiconductor region (2) comprising silicon by means of an epitaxial deposition process, wherein the epitaxial deposition process of the n-type region is performed by positioning the semiconductor body (1) in an epitaxial reactor and introducing in the reactor a first gas stream comprising a carrier gas and further gas streams comprising a gaseous compound comprising silicon and a gaseous compound comprising an element from the fifth column of the periodic system of elements, while heating the semiconductor body (1) to a growth temperature (Tg) and using an inert gas as the carrier gas. According to the invention for the gaseous compound comprising silicon a mixture is chosen of a first gaseous silicon compound which is free of chlorine and a second gaseous silicon compound comprising chlorine.

Abstract: In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate, patterning and etching the CNT seeding layer, and selectively fabricating CNT material on the CNT seeding layer. Numerous other aspects are provided.

Abstract: A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least 30° C./minute. The surface of the SiC substrate is inclined at an angle of from 1° to 3° with respect to a basal plane of the substrate material.

Abstract: A method for releasing from underlying substrate material micromachined structures or devices without application of chemically aggressive substances or excessive forces. The method starts with the step of providing a partially formed device, comprising a substrate layer, a sacrificial layer deposited on the substrate, and a function layer deposited on the sacrificial layer and possibly exposed portions of the substrate layer and then etched to define micromechanical structures or devices therein. The etching process exposes the sacrificial layer underlying the removed function layer material. Next there are the steps of cleaning residues from the surface of the device, and then directing high-temperature hydrogen gas over the exposed surfaces of the sacrificial layer to convert the silicon dioxide to a gas, which is carried away from the device by the hydrogen gas.

Abstract: A method of manufacturing a silicon substrate includes: growing a silicon single crystal having a carbon concentration in the range of 1.0×1016 atoms/cm3 to 1.6×1017 atoms/cm3 and an initial oxygen concentration in the range of 1.4×1018 atoms/cm3 to 1.6×1018 atoms/cm3 using a CZ method; slicing the silicon single crystal; forming an epitaxial layer on the sliced silicon single crystal; and performing a heat treatment thereon as a post-annealing process at a temperature in the range of 600° C. to 850° C.

Abstract: Method of manufacturing a thin film device substrate wherein no trench fabrication is required to be applied onto the substrate surface, and a material which is impervious to light can be used, and the substrate can be peeled off quickly. Firstly, a peeling-off film, a silicon oxide film and an amorphous silicon film are formed in succession on a glass substrate, and the amorphous silicon film is irradiated from above to obtain a polycrystalline silicon film. Subsequently, using the polycrystalline silicon film as an active layer, a TFT is formed, and then a plastic substrate is bonded thereon, and finally the glass substrate is peeled off with the peeling-off film, to complete transfer of the TFT. Because the peeling-off film has a gap space, its etching rate is high. Therefore, it is unnecessary to form a trench for supplying an etchant on the surface of the glass substrate.

Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow rate ratio greater than about 200:1 into the processing chamber, maintaining a first process pressure greater than about 6 Torr in the processing chamber to deposit a first microcrystalline silicon containing layer in presence of a plasma formed from the first gas mixture, supplying a second gas mixture into the processing chamber, and maintaining a second process pressure less than about 5 Torr in the processing chamber to deposit a second microcrystalline silicon containing layer in presence of a plasma formed from the second gas mixture.

Abstract: In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amorphous surface and/or a polycrystalline surface. The substrate is exposed to a deposition gas to deposit an epitaxial layer on the monocrystalline surface and a polycrystalline layer on the second surface. The deposition gas preferably contains a silicon source and at least a second elemental source, such as a germanium source, a carbon source and/or combinations thereof. Thereafter, the method further provides exposing the substrate to an etchant gas to etch the polycrystalline layer and the epitaxial layer in a manner such that the polycrystalline layer is etched at a faster rate than the epitaxial layer.

Abstract: A method for producing a Group IV semiconductor thin film in a chamber is disclosed. The method includes positioning a substrate in the chamber, wherein the chamber further has a chamber pressure. The method further includes depositing a nanoparticle ink on the substrate, the nanoparticle ink including set of Group IV semiconductor nanoparticles and a solvent, wherein each nanoparticle of the set of Group IV semiconductor nanoparticles includes a nanoparticle surface, wherein a layer of Group IV semiconductor nanoparticles is formed. The method also includes striking a hydrogen plasma; and heating the layer of Group IV semiconductor nanoparticles to a fabrication temperature of between about 300° C. and about 1350° C., and between about 1 nanosecond and about 10 minutes; wherein the Group IV semiconductor thin film is formed.

Abstract: A light-emitting LED device has one or more light-emitting LED elements, including first and second spaced-apart electrodes with one or more light-emitting layers formed there-between, wherein at least one of the electrodes is a transparent electrode. Also included are a first transparent encapsulating layer having a first optical index formed over the transparent electrode opposite the light-emitting layer; a light-scattering layer formed over the first transparent encapsulating layer opposite the transparent electrode; and a second transparent encapsulating layer, having a second optical index lower than the first optical index, formed over the light-scattering layer.

Abstract: The present invention is a method for producing a semiconductor wafer, comprising at least steps of, epitaxially growing a Si1-XGeX layer (0<X<1) on an SOI wafer, forming a Si1-YGeY layer (0?Y<X) on the epitaxially grown Si1-XGeX layer, and then enriching Ge in the epitaxially grown Si1-XGeX layer by an oxidation heat treatment so that the Si1-XGeX layer becomes an enriched SiGe layer, wherein, at least, the oxidation heat treatment is initiated from 950° C. or less under an oxidizing atmosphere, and the oxidation is performed so that the formed Si1-YGeY layer remains during a temperature rise to 950° C. Thereby, there can be provided a method for producing a semiconductor wafer by which the lattice relaxation of the SiGe layer in an SGOI wafer can be sufficiently performed by a heat treatment for a short time and its production cost can be reduced.

Abstract: A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.

Abstract: A method of fabricating a semiconductor device according to one embodiment of the invention includes: forming a gate electrode on a semiconductor substrate through a gate insulating film; forming offset spacers on side surfaces of the gate electrode, respectively; etching the semiconductor substrate with a channel region below the offset spacers and the gate electrode being left by using the offset spacers as a mask; forming a first epitaxial layer made of a crystal having a lattice constant different from that of a crystal constituting the semiconductor substrate on the semiconductor substrate thus etched; etching at least a portion of the first epitaxial layer adjacent to the channel region to a predetermined depth from a surface of the first epitaxial layer toward the semiconductor substrate side; and forming a second epitaxial layer containing therein a conductivity type impurity on the first epitaxial layer thus etched.

Abstract: The present invention provides methods of making and using semiconductive single crystal diamond bodies, including semiconductive diamond bodies made by such methods. In one aspect, a method of making a semiconductive single crystal diamond layer may include placing a plurality of diamond segments in close proximity under high pressure in association with a molten catalyst and a carbon source, where the diamond segments are arranged in a single crystal orientation. The plurality of diamond segments are then maintained under high pressure in the molten catalyst until the plurality of diamond segments have joined together with diamond to diamond bonds to form a substantially single crystal diamond body. Following creation of the single crystal diamond body, a homoepitaxial single crystal diamond layer may be deposited on the single crystal diamond body. A dopant may be introduced into the homoepitaxial single crystal diamond layer to form a semiconductive single crystal diamond layer.

Abstract: A method for depositing a single crystalline silicon film comprises: providing a substrate disposed within a chamber; introducing to the chamber under chemical vapor deposition conditions a silicon precursor, a chlorine-containing etchant and an inhibitor source for decelerating reactions between the silicon precursor and the chlorine-containing etchant; and selectively depositing a doped crystalline Si-containing film onto the substrate.

Abstract: A vertical CVD apparatus is arranged to process a plurality of target substrates all together to form a silicon germanium film. The apparatus includes a reaction container having a process field configured to accommodate the target substrates, and a common supply system configured to supply a mixture gas into the process field. The mixture gas includes a first process gas of a silane family and a second process gas of a germane family. The common supply system includes a plurality of supply ports disposed at different heights.

Abstract: A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 107 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface.

Abstract: A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.

Abstract: The invention relates to a method for depositing at least one semiconductor layer on at least one substrate in a processing chamber (2). Said semiconductor layer is composed of several components which are evaporated by non-continuously injecting a liquid starting material (3) or a starting material (3) dissolved in a liquid into a tempered evaporation chamber (4) with the aid of one respective injector unit (5) while said vapor is fed to the processing chamber by means of a carrier gas (7). The inventive method is characterized in that the mass flow rate parameters, such as the preliminary injection pressure, the injection frequency, the pulse/pause ratio, and the phase relation between the pulses/pauses and the pulses/pauses of the other injector unit(s), which determine the progress of the mass flow rate of a first silicon-containing starting material and a germanium-containing second starting material (3) through the associated injector unit (5), are individually adjusted or varied.

Abstract: A method of forming a nanostructure at low temperatures. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of least one of nitrogen and oxygen is generated within a laser-sustained-discharge plasma source and a collimated beam of energetic neutral atoms and molecules is directed from the plasma source onto a surface of the substrate to form the nanostructure. The energetic neutral atoms and molecules in the plasma have an average kinetic energy in a range from about 1 eV to about 5 eV.

Abstract: Various embodiments of the present invention comprise systems and methods of fabricating porous silicon. One application of such porous silicon is in the fabrication of electro-osmotic pumps and electro-osmotic pump substrates. The method can comprise operations performed on a silicon wafer. A liner material can be deposited on the silicon wafer, and a photoresist layer can be deposited on the liner material. The photoresist layer can be adapted to define a predetermined pattern on the silicon wafer. Then, porous silicon can be formed on the silicon wafer according to the predefined pattern. As a result, solid silicon can support porous silicon regions of the silicon wafer, providing a support structure for the pumping medium. Other embodiments, aspects, and features are also claimed and described.

Abstract: The present invention relates to a method for manufacturing a display device including a p-channel thin film transistor and an n-channel thin film transistor having a microcrystalline semiconductor film each of which are an inverted-staggered type, and relates to a method for formation of an insulating film and a semiconductor film which are included in the thin film transistor. Two or more kinds of high-frequency powers having different frequencies are supplied to an electrode for generating glow discharge plasma in a reaction chamber. High-frequency powers having different frequencies are supplied to generate glow discharge plasma, so that a thin film of a semiconductor or an insulator is formed. High-frequency powers having different frequencies (different wavelength) are superimposed and applied to the electrode of a plasma CVD apparatus, so that densification and uniformity of plasma for preventing the effect of surface standing wave of plasma can be realized.

Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.

Abstract: Disclosed is a method for cleaning a semiconductor device to remove native oxides or by-products created in the process of forming silicon germanium layers. The use of the method enables removal of native oxides or by-products created in the process of forming silicon germanium layers using hydrogen bromide and prevents reoxidation which may occur in subsequent processes after forming silicon germanium layers.

Abstract: The present invention provides a porous semiconductive structure, characterized in that the structure has an electrical conductivity of 5·10?8 S·cm?1 to 10 S·cm?1, and an activation energy of the electrical conductivity of 0.1 to 700 meV, and a solid fraction of 30 to 60% by volume, and a pore size of 1 nm to 500 nm, the solid fraction having at least partly crystalline doped constituents which are bonded to one another via sinter necks and have sizes of 5 nm to 500 nm and a spherical and/or ellipsoidal shape, which comprise the elements silicon, germanium or an alloy of these elements, and also a process for producing a porous semiconductive structure, characterized in that A. doped semimetal particles are obtained, and then B. a dispersion is obtained from the semimetal particles obtained after step A, and then C. a substrate is coated with the dispersion obtained after step B, and then D. the layer obtained after step C is treated by means of a solution of hydrogen fluoride in water, and then E.

Abstract: An apparatus for making a set of Group IV nanoparticles is disclosed. The apparatus includes a top plate, the top plate further including an outlet port; a bottom plate; and a casing extending between the top plate and the bottom plate. The apparatus also includes a particle collector assembly configured to be in fluid communication with the outlet port; and a primary precursor tubing assembly passing through the bottom plate into the casing, the primary precursor tubing assembly including a primary precursor tubing assembly nozzle.

Abstract: A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is substantially in agreement with a predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate, and at least one of orthographic projection images of cross-sections taken along planes parallel with the semiconductor silicon substrate of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is larger than the predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate.

Abstract: A method of forming an epitaxial layer on a silicon substrate includes (a) providing a silicon substrate; (b) performing a wet-cleaning process onto the silicon substrate; (c) performing a first plasma cleaning process onto the wet-cleaned silicon substrate by providing a chlorine (Cl2) gas and an argon (Ar) gas; and (d) forming an epitaxial growth film on the silicon substrate after the (c) step.

Abstract: A silicon epitaxial wafer of the invention comprises a silicon single crystal wafer sliced from a CZ silicon ingot doped with carbon in a concentration range of not less than 5×1015 atoms/cm3 and not more than 5×1017 atoms/cm3 and an epitaxial layer consisting of a silicon single crystal epitaxially grown on a front surface of the silicon single crystal wafer. A polycrystalline silicon layer having a thickness of not less than 0.5 ?m and not more than 1.5 ?m is formed on a back surface of the silicon single crystal wafer.

Abstract: Methods of depositing thin film materials having crystalline content are provided. The methods use plasma enhanced chemical vapor deposition. According to one embodiment of the present invention, microcrystalline silicon films are obtained. According to a second embodiment of the present invention, crystalline films of zinc oxide are obtained. According to a third embodiment of the present invention, crystalline films of iron oxide are obtained.

Abstract: Low pressure chemical vapor deposition (LPCVD) of polysilicon on a wafer in a manner that reduces the generation of particles during the deposition process. In one example embodiment, a method of LPCVD of polysilicon on a wafer positioned in a process tube includes various steps. First, introducing a particle inhibitor is introduced into the process tube. Next, a silicon source gas is introduced into the process tube. Finally, a doping gas is introduced into the process tube, resulting in the formation of a polysilicon film of a uniform thickness on the wafer.

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.

Abstract: This invention provides a substrate structure capable of controlling the threshold voltage of a MOS transistor independently of the substrate concentration and easily suppressing a short channel effect caused by reducing the channel length. A first nanosilicon film formed from nanosilicon grains having the same grain size is formed on a silicon oxide film on the surface of a silicon substrate. A silicon nitride film is formed on the first nanosilicon film. Then, a second nanosilicon film having an average grain size different from that of the first nanosilicon film is formed. A semiconductor circuit device is formed on a thus manufactured nanosilicon semiconductor substrate.