Using Diffusion Into Or Out Of A S Olid From Or Into A Solid Phase, E.g., A Doped Oxide Layer (epo) Patents (Class 257/E21.144)
  • Publication number: 20090108293
    Abstract: A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Inventors: Victor Moroz, Dipankar Pramanik
  • Patent number: 7449361
    Abstract: Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: November 11, 2008
    Assignee: Intel Corporation
    Inventors: Rajashree Baskaran, Kramadhati V. Ravi
  • Patent number: 7439609
    Abstract: An improved p-type gallium nitride-based semiconductor device is disclosed. The device includes a structure with at least one p-type Group III nitride layer that includes some gallium, a first silicon dioxide layer on the p-type layer, a layer of a Group II metal source composition on the first SiO2layer, and a second SiO2 layer on the Group II metal source composition layer.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: October 21, 2008
    Assignee: Cree, Inc.
    Inventor: Gerald H. Negley
  • Patent number: 7326631
    Abstract: Consistent with an example embodiment, a method of manufacturing a semiconductor device comprises MOS transistors having gate electrodes formed in a number of metal layers deposited upon one another. Active silicon regions having a layer of a gate dielectric and field-isolation regions insulating these regions from each other are formed in a silicon body. Then, a layer of a first metal is deposited in which locally, in a part of the active regions, nitrogen is introduced. On the layer of the first metal, a layer of a second metal is then deposited, after which the gate electrodes are etched in the metal layers. Before nitrogen is introduced into the first metal layer, an auxiliary layer of a third metal permeable to nitrogen is deposited an the first metal layer. Thus, the first metal layer can be nitrided locally without the risk of damaging the underlying gate dielectric.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: February 5, 2008
    Assignee: NXP B.V.
    Inventors: Robert Lander, Jacob Christopher Hooker, Robertus Adrianus Maria Wolters
  • Patent number: 7303967
    Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: December 4, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hoon Sa
  • Patent number: 7282428
    Abstract: In order to form a p-region in an InP-based photodiode, zinc doping must be performed. Due to the current trend toward the implementation of larger-sized InP wafers, there is a need for a solid phase diffusion method in which a ZnO thin film is applied to an epitaxial wafer, the wafer is heated, such that zinc is diffused from the ZnO thin film into the InP epitaxial layers. A mask having an upper layer made of a-Si is used as a diffusion mask. Since a-Si does not dissolve in hydrofluoric acid, the a-Si remains without dissolving when the ZnO is removed with hydrofluoric acid. Since the a-Si film remains, the edge of the pn junction is not exposed. The pn junction does not become degraded because the edge of the pn junction is covered and protected by the diffusion mask at all times.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: October 16, 2007
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hiroshi Inada