By Chemical Means, E.g., Cvd, Lpcvd, Pecvd, Laser Cvd (epo) Patents (Class 257/E21.17)
  • Patent number: 10279959
    Abstract: Described herein are alkoxysilylamine precursors having the following Formulae A and B: wherein R1 and R4 are independently selected from a linear or branched C1 to C10 alkyl group, a C3 to C12 alkenyl group, a C3 to C12 alkynyl group, a C4 to C10 cyclic alkyl group, and a C6 to C10 aryl group and wherein R2, R3, R4, R5, and R6 are independently selected from the group consisting of hydrogen, a linear or branched C1 to C10 alkyl group, a C2 to C12 alkenyl group, a C2 to C12 alkynyl group, a C4 to C10 cyclic alkyl, a C6 to C10 aryl group, and a linear or branched C1 to C10 alkoxy group. Also described herein are deposition processes using at least one precursor have Formulae A and/or B described herein.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 7, 2019
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Manchao Xiao, Ronald Martin Pearlstein, Richard Ho, Daniel P. Spence, Xinjian Lei
  • Patent number: 10242878
    Abstract: A substrate processing method is for forming a metal film on a target substrate by using a plasma. The method includes loading a target substrate having a silicon-containing layer on a surface thereof into a processing chamber which is pre-coated by a film containing a metal, introducing hydrogen gas and a gaseous compound of the metal and halogen into the processing chamber, generating a plasma, and forming a metal film on the target substrate. The method further includes performing a first reduction process of forming an atmosphere of a plasma obtained by activating hydrogen gas in the processing chamber, unloading the target substrate from the processing chamber, performing a second reduction process of forming an atmosphere of a plasma obtained by activating hydrogen gas in the processing chamber, and loading a next target substrate into the processing chamber.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: March 26, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tomonari Urano, Kyohei Noguchi, Osamu Yokoyama, Takashi Kobayashi, Satoshi Wakabayashi, Takashi Sakuma
  • Patent number: 10229948
    Abstract: A semiconductor apparatus includes a conductive member penetrating through a first semiconductor layer, a first insulator layer, and a third insulator layer, and connecting a first conductor layer with a second conductor layer. The conductive member has a first region containing copper, and a second region containing a material different from the copper is located at least between a first region and the first semiconductor layer, between the first region and the first insulator layer, and between the first region and the third insulator layer. A diffusion coefficient of the copper to a material is lower than a diffusion coefficient of the copper to the first semiconductor layer and a diffusion coefficient of the copper to the first insulator layer.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: March 12, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Mineo Shimotsusa
  • Patent number: 10157785
    Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Ching-Hwanq Su, Liang-Yueh Ou Yang, Ming-Hsing Tsai, Yu-Ting Lin
  • Patent number: 10141187
    Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 27, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa, Hiroki Murakami
  • Patent number: 10112825
    Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Huang Chiu, Weng-Yi Chen, Kuan-Yu Wang
  • Patent number: 10079245
    Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: September 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hauk Han, Je-Hyeon Park, Kihyun Yoon, Changwon Lee, HyunSeok Lim, Jooyeon Ha
  • Patent number: 10049925
    Abstract: Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Patent number: 10017852
    Abstract: A method for transferring a graphene sheet from a copper substrate to a functional substrate includes forming the graphene sheet on the copper substrate using chemical vapor deposition, and irradiating the graphene sheet disposed on the copper substrate with a plurality of xenon ions using broad beam irradiation to form a prepared graphene sheet. The prepared graphene sheet is resistant to forming unintentional defects induced during transfer of the prepared graphene sheet to the functional substrate. The method further includes removing the copper substrate from the prepared graphene sheet using an etchant bath, floating the prepared graphene sheet in a floating bath, submerging the functional substrate in the floating bath, and decreasing a fluid level of the floating bath to lower the prepared graphene sheet onto the functional substrate.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: July 10, 2018
    Assignee: Lockheed Martin Corporation
    Inventors: Scott E. Heise, Peter V. Bedworth, Jacob L. Swett, Steven W. Sinton
  • Patent number: 9962085
    Abstract: An inductive wireless power transfer and communication system includes an electrostatic shield for one of the coils. The electrostatic shield is inductively coupled with the coil and is configured as an open circuit. A signal processing element or elements, especially a modulator or a demodulator, are connected across the electrical discontinuity in the electrostatic shield. Because the electrostatic shield is inductively coupled to the coil, the modulator or demodulator can operate on the signal on the coil.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: May 8, 2018
    Assignee: The Alfred E. Mann Foundation For Scientific Research
    Inventor: Glen A. Griffith
  • Patent number: 9966308
    Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, forming a liner layer on the second dielectric layer and in the first and second contact holes, and forming a copper contact in the first and second contact holes.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: May 8, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
  • Patent number: 9911650
    Abstract: A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. The first contact structure comprises a first portion and a second portion. The first portion is formed in the gate electrode, and the second portion is formed on the first portion.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Guo-Chiang Chi, Chia-Der Chang, Chih-Hung Lu, Wei-Chin Chen
  • Patent number: 9847296
    Abstract: A method for forming a multilayer barrier comprises forming a conductive line over a substrate, depositing a dielectric layer over the conductive line, forming a plug opening in the dielectric layer, forming a multilayer barrier through a plurality of deposition processes and corresponding plasma treatment processes.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chung Chang, Jung-Chih Tsao, Chun Che Lin, Yu-Ming Huang, Tain-Shang Chang, Jian-Shin Tsai
  • Patent number: 9837504
    Abstract: A method of fabricating the gate structure in a semiconductor device includes forming a gate dielectric layer over a semiconductor substrate. A capping layer is formed over the gate dielectric layer. The capping layer is treated with a first hydrogen plasma to form a first-treated capping layer. A gate electrode is formed over the first-treated capping layer. The method may further includes treating the first-treated capping layer with a nitrogen plasma.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: December 5, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Heng Chen, Wayne Liu, Liang-Yin Chen, Xiong-Fei Yu, Hui-Cheng Chang
  • Patent number: 9799527
    Abstract: Isolation is provided by forming a first trench, depositing a cover layer on the bottom and sidewalls of the first trench, selectively removing the cover layer from the bottom and forming a second trench extending from the bottom of the first trench. The second trench is then substantially filled by thermal oxide formed by oxidation and the first trench is subsequently filled with a deposited dielectric.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: October 24, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Katsuo Yamada, Yuji Takahashi, Takuya Futase, Noritaka Fukuo, Tomoyasu Kakegawa
  • Patent number: 9776202
    Abstract: A driving method of a vertical heat treatment apparatus having a vertical reaction container with a heating part installed includes: performing a process of loading wafers by a substrate holder support to the reaction container; performing a film forming process of storing a first gas at a storage unit and pressurizing the first gas, and alternatively performing a step of supplying the first gas to the vacuum atmosphere reaction container and a step of supplying the second gas to the reaction container; subsequently performing a purge process of unloading the substrate holder support and supplying a purge gas into the reaction container to forcibly peel off a thin film attached to the reaction container; and while the purge process is performed, performing a process of repeating storing the purge gas at the storage unit, pressurizing the gas and discharging the gas into the reaction container.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 3, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yutaka Motoyama, Keisuke Suzuki, Kohei Fukushima, Shingo Hishiya
  • Patent number: 9768060
    Abstract: In one embodiment of the present disclosure, a method for electrochemical deposition on a workpiece includes (a) obtaining a workpiece including a feature; (b) depositing a first conductive layer in the feature; (c) moving the workpiece to an integrated electrochemical deposition plating tool configured for hydrogen radical H* surface treatment and electrochemical deposition; (d) treating the first conductive layer using a hydrogen radical H* surface treatment in a treatment chamber of the plating tool to produce a treated first conductive layer; and (e) maintaining the workpiece in the same plating tool and depositing a second conductive layer in the feature on the treated first conductive layer in an electrochemical deposition chamber of the plating tool.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: September 19, 2017
    Assignee: APPLIED Materials, Inc.
    Inventors: Roey Shaviv, Ismail T. Emesh
  • Patent number: 9735295
    Abstract: An electronic device with an electrode having a superior light transmittance and including a substrate, an amine group-containing compound layer formed on the substrate, and a metal layer formed on the amine group-containing compound layer is provided. In accordance with the present invention, the electrode is easily manufactured when a solution process is used, has performances of a light transmittance, a sheet resistance, and flexibility higher than those of a typical ITO transparent electrode, and a manufacturing cost of the electrode may be reduced.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: August 15, 2017
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Kwang Hee Lee, Su Hyun Jung, Hong Kyu Kang
  • Patent number: 9711399
    Abstract: An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Jason A. Farmer, Jeffrey S. Leib, Daniel B. Bergstrom
  • Patent number: 9627647
    Abstract: An organic light-emitting diode display includes an organic light-emitting display device including a first electrode, an intermediate layer including an organic emission layer, and a second electrode; a first inorganic encapsulation layer on the second electrode; a second inorganic encapsulation layer on the first inorganic encapsulation layer; and an organic encapsulation layer on the second inorganic encapsulation layer. A refractive index of the first inorganic encapsulation layer is higher than a refractive index of the second inorganic encapsulation layer. The first inorganic encapsulation layer has an extinction coefficient of 0.02 to 0.07 and a refractive index of 2.1 to 2.3 at a blue wavelength.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaehyun Kim, Yongjun Park, Cheho Lee
  • Patent number: 9499399
    Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: November 22, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Che Chen, Te-Yuan Wu, Chia-Huei Lin, Hui-Min Wu, Kun-Che Hsieh, Kuan-Yu Wang, Chung-Yi Chiu
  • Patent number: 9478411
    Abstract: Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 25, 2016
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Reza Arghavani, Michal Danek
  • Patent number: 9466488
    Abstract: Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Patent number: 9425078
    Abstract: Systems and methods for depositing film in a substrate processing system includes performing a first atomic layer deposition (ALD) cycle in a processing chamber to deposit film on a substrate including a feature; after the first ALD cycle, exposing the substrate to an inhibitor plasma in the processing chamber for a predetermined period to create a varying passivated surface in the feature; and after the predetermined period, performing a second ALD cycle in the processing chamber to deposit film on the substrate.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 23, 2016
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Wei Tang, Bart Van Schravendijk, Jun Qian, Hu Kang, Adrien LaVoie, Deenesh Padhi, David C. Smith
  • Patent number: 9299619
    Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a substrate having a PMOS region and an NMOS; forming a first gate trench on the PMOS region; forming a first high-k dielectric layer and a first high-k cap layer that cover a bottom and sides of the first gate trench; forming a second gate trench on the NMOS region; forming a second high-k dielectric layer and a second high-k cap layer that cover a bottom and sides of the second gate trench; removing a portion of the first high-k dielectric layer and a portion of the first high-k cap layer that are positioned on a side of the first gate trench; and removing a portion of the second high-k dielectric layer and a portion of the second high-k cap layer that are positioned on a side of the second gate trench.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 29, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jie Zhao
  • Patent number: 9281303
    Abstract: Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Huiming Bu, Junjun Li, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 9236392
    Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: January 12, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Keisuke Izumi, Hiroaki Iuchi, Ryo Taura, Kentaro Sera, Akio Yanai
  • Patent number: 9041111
    Abstract: A flat panel detector includes a photoelectric conversion layer and a pixel detecting element disposed under the photoelectric conversion layer. The pixel detecting element includes: a pixel electrode for receiving charges, a storage capacitor for storing the received charges, and a thin film transistor for controlling outputting of the stored charges. The storage capacitor includes a first electrode and a second electrode. The first electrode includes an upper electrode and a bottom electrode that are disposed opposite to each other and electrically connected. A second electrode is sandwiched between the upper electrode and the bottom electrode. It is insulated between the upper electrode and the second electrode and between the second electrode and the bottom electrode.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: May 26, 2015
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Zhenyu Xie
  • Patent number: 9018050
    Abstract: A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: April 28, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Wen Huang
  • Patent number: 9013005
    Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Syotaro Ono, Wataru Saito, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita, Toshiyuki Naka
  • Patent number: 8999805
    Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.
    Type: Grant
    Filed: October 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 8999846
    Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Luke D. LaCroix, Mark C. H. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 8987753
    Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 24, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8980682
    Abstract: Methods of forming absorber layers in a TFPV device are provided. Methods are described to provide the formation of metal oxide films and heating the metal oxide films in the presence of a chalcogen to form a metal-oxygen-chalcogen alloy. Methods are described to provide the formation of metal oxide films, forming a layer of elemental chalcogen on the metal oxide film, and heating the stack to form a metal-oxygen-chalcogen alloy. In some embodiments, the metal oxide film includes zinc oxide and the chalcogen includes selenium.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Haifan Liang, Jeroen Van Duren
  • Patent number: 8969752
    Abstract: The present invention provides a laser processing method comprising the steps of attaching a protective tape 25 to a front face 3 of a wafer 1a, irradiating a substrate 15 with laser light L while employing a rear face of the wafer 1a as a laser light entrance surface and locating a light-converging point P within the substrate 15 so as to form a molten processed region 13 due to multiphoton absorption, causing the molten processed region 13 to form a cutting start region 8 inside by a predetermined distance from the laser light entrance surface along a line 5 along which the object is intended to be cut in the wafer 1a, attaching an expandable tape 23 to the rear face 21 of the wafer 1a, and expanding the expandable tape 23 so as to separate a plurality of chip parts 24 produced upon cutting the wafer 1a from the cutting start region 8 acting as a start point from each other.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: March 3, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Kenshi Fukumitsu, Fumitsugu Fukuyo, Naoki Uchiyama
  • Patent number: 8962461
    Abstract: Consistent with an example embodiment, a GaN heterojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectriclayer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 24, 2015
    Assignee: NXP B.V.
    Inventors: Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers, Stephan Heil, Jan Sonsky
  • Patent number: 8952512
    Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: February 10, 2015
    Assignee: China Wafer Level CSP Ltd.
    Inventors: Junjie Li, Wenbin Wang, Qiuhong Zou, Guoqing Yu, Wei Wang
  • Patent number: 8951878
    Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Hironobu Shoji, Hideto Ohnuma, Shunpei Yamazaki
  • Patent number: 8952452
    Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Seong Kang, Yoon-Hae Kim, Jong-Shik Yoon
  • Patent number: 8946784
    Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung, Pao-Tung Chen, Jen-Cheng Liu
  • Patent number: 8946894
    Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: February 3, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Tarak A. Railkar, Deep C. Dumka
  • Patent number: 8937020
    Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Keiji Sato
  • Patent number: 8937022
    Abstract: A method of manufacturing a semiconductor device includes: housing a substrate into a processing chamber; and forming a metal nitride film on the substrate by supplying a source gas containing a metal element, a nitrogen-containing gas and a hydrogen-containing gas into the processing chamber; wherein in forming the metal nitride film, the source gas and the nitrogen-containing gas are intermittently supplied into the processing chamber, or the source gas and the nitrogen-containing gas are intermittently and alternately supplied into the processing chamber, or the source gas is intermittently supplied into the processing chamber in a state that supply of the nitrogen-containing gas into the processing chamber is continued, and the hydrogen-containing gas is supplied into the processing chamber during at least supply of the nitrogen-containing gas into the processing chamber.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: January 20, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Arito Ogawa
  • Patent number: 8927348
    Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 6, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Susumu Sugano, Hisayuki Miki, Hironao Shinohara
  • Patent number: 8927433
    Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 6, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Jin-Yeong Kang
  • Patent number: 8912098
    Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
  • Patent number: 8906772
    Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 9, 2014
    Assignee: UChicago Argonne, LLC
    Inventor: Anirudha V. Sumant
  • Patent number: 8906790
    Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Albert Lee, Tony P. Chiang, Jason Wright
  • Patent number: 8906811
    Abstract: A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: December 9, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thorsten Kammler, Andy Wei, Ina Ostermay
  • Patent number: 8900999
    Abstract: A method of filling a feature in a substrate with tungsten without forming a seam is presented. The tungsten is deposited by a thermal chemical vapor deposition (CVD) process using hydrogen (H2) and tungsten hexafluoride (WF6) precursor gases. The H2 to WF6 flow rate ratio is greater than 40 to 1, such as from 40 to 1 to 100 to 1. The substrate temperature during deposition is less than 300 degrees Celsius (° C.) and the processing pressure during deposition is greater than 300 Torr.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: December 2, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kai Wu, Sang-Hyeob Lee, Joshua Collins, Kiejin Park