Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a dielectric structure on a semiconductor substrate, introducing a first gas on the dielectric structure to form first conductive structures on the dielectric structure, and introducing a second gas on the first conductive structures and the dielectric structure. The second gas is different from the first gas. The method also includes introducing a third gas on the first conductive structures and the dielectric structure to form second conductive structures on the dielectric structure. The first gas and the third gas include the same metal.

Abstract: Embodiments of the present disclosure are directed towards a protective multilayer coating for process chamber components exposed to temperatures from about 20° C. to about 300° C. during use of the process chamber. The protective multilayer coating comprises a bond layer and a top layer, the bond layer is formed on a chamber component to reduce the stress between the top layer and the chamber component. The reduced stress decreases or prevents particle shedding from the top layer of the multilayer coating during and after use of the process chamber. The bond layer comprises titanium, titanium nitride, aluminum, or combinations thereof, and the top layer comprises tungsten nitride.

Abstract: In order to provide an absorbance analysis apparatus for DCR gas that can measure a concentration of a DCR gas by separating absorbance of the DCR gas alone even in a mixed gas consisting of the DCR gas and CO gas whose absorption spectrum overlaps each other, the absorbance analysis apparatus for DCR gas comprises a DCR filter 31 that is configured to transmit a light in a first wavenumber domain including an absorbance peak of the DCR gas, a CO filter 32 that is configured to transmit a light in a second wavenumber domain that is different from the first wavenumber domain, and a DCR gas volume calculator 4 that is configured to calculate volume of the DCR gas based on a first absorbance measured by the light transmitted through the DCR filter 31 and a second absorbance measured by the light transmitted through the CO filter 32.

Abstract: In a capacitive coupled etch reactor, in which the smaller electrode is predominantly etched, the surface of the larger electrode is increased by a body e.g. a plate, which is on the same electric potential as the larger electrode and which is immersed in the plasma space. A pattern of openings in which plasma may burn is provided in the body so as to control the distribution of the etching effect on a substrate placed on the smaller electrode.

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction; a gate structure extending across the fin-type active region in a second direction, different from the first direction; a source/drain region in the fin-type active region on one side of the gate structure; and first and second contact structures connected to the source/drain region and the gate structure, respectively, wherein at least one of the first and second contact structures includes a seeding layer on at least one of the gate structure and the source/drain region and including a first crystalline metal, and a contact plug on the seeding layer and including a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug.

Abstract: The present invention provides a method for manufacturing a molybdenum-containing thin film and a molybdenum-containing thin film manufactured thereby. By using a molybdenum (0)-based hydrocarbon compound and a predetermined reaction gas, the method for manufacturing a molybdenum-containing thin film according to the present invention enables easy manufacturing of a highly pure thin film in a simple process.

Abstract: Methods for atomic layer deposition (ALD) of plasma enhanced atomic layer deposition (PEALD) of low-K films are described.

Abstract: A method of manufacturing a semiconductor device may include forming a stack structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate, forming channel structures extending through the stack structure, forming openings extending through the stack structure, forming lateral openings by removing the sacrificial layers exposed by the openings, and forming gate electrodes in the lateral openings. Forming the gate electrodes may include supplying a source gas containing tungsten (W) wherein the source gas is heated to a first temperature and is supplied in a deposition apparatus at the first temperature, supplying a reactant gas containing hydrogen (H) subsequently to supplying the source gas, wherein the reactant gas is heated to a second temperature and is supplied in the deposition apparatus at the second temperature, and supplying a purge gas subsequently to supplying the reactant gas.

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

Abstract: An apparatus for direct liquid injection (DLI) of chemical precursors into a processing chamber is provided. The apparatus includes a vaporizer assembly having an injection valve for receiving a liquid reactant, vaporizing the liquid reactant, and delivering the vaporized liquid reactant. The injection valve includes a valve body encompassing an interior region therein, a gas inlet port, a liquid inlet port, and a vapor outlet port all in fluid communication with the interior region. The vaporizer assembly further includes a first inlet line having a first end fluidly coupled with the liquid inlet port and a second end to be connected to a liquid source. The vaporizer assembly further includes a second inlet line with a first end fluidly coupled with the gas inlet port, a second end fluidly coupled with a carrier gas source, and a heater positioned between the first end and the second end.

Abstract: A method of processing a target substrate includes a process of serially executing multiple processes including a main process and first to M-th subprocesses (where M is a positive integer). An index value indicating one execution of the main process is accumulated for each execution of the main process. The main process is executed multiple times in the process of serially executing multiple processes. An i-th subprocess (where i is a positive integer that satisfies 1?i?M) is executed once or multiple times in the process of serially executing multiple processes, and is executed subsequent to one or multiple consecutive executions of the main process. The i-th application and execution conditions are changeable.

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Abstract: The present disclosure relates to a method for forming a p-metal work function nitride film having a desired p-work function on a substrate, including: adjusting one or more of a temperature of a substrate, a duration of one or more temporally separated vapor phase pulses, a ratio of a tungsten precursor to a titanium precursor, or a pressure of a reaction to tune a work function of a p-metal work function nitride film to a desired p-work function, and contacting the substrate with temporally separated vapor phase pulses of the tungsten precursor, the titanium precursor, and a reactive gas to form a p-metal work function nitride film thereon having the desired p-work function.

Abstract: Methods for depositing metal oxide layers on metal surfaces are described. The methods include exposing a substrate to separate doses of a metal precursor, which does not contain metal-oxygen bonds, and an alcohol. These methods do not oxidize the underlying metal layer.

Abstract: A method of forming a nitride film wherein (a) a silane-based gas is supplied to a processing chamber through a gas supply port; (b) a nitrogen radical gas from a radical generator is supplied to the processing chamber through a radical gas pass-through port; and (c) the silane-based gas supplied in (a) is reacted with the nitrogen radical gas supplied in (b), without causing a plasma phenomenon in the processing chamber, to form a nitride film on a wafer.

Abstract: Described herein is an FCVD process for depositing a silicon-containing film from at least one alkoxysilylamine precursor having the following Formulae A and B: wherein R1 and R4 are independently selected from a linear or branched C1 to C10 alkyl group, a C3 to C12 alkenyl group, a C3 to C12 alkynyl group, a C4 to C10 cyclic alkyl group, and a C6 to C10 aryl group and wherein R2, R3, R4, R5, and R6 are independently selected from the group consisting of hydrogen, a linear or branched C1 to C10 alkyl group, a C2 to C12 alkenyl group, a C2 to C12 alkynyl group, a C4 to C10 cyclic alkyl, a C6 to C10 aryl group, and a linear or branched C1 to C10 alkoxy group.

Abstract: A method of forming a tungsten film having low resistance is provided. The method includes forming a discontinuous film containing a metal on a substrate; and forming the tungsten film on the substrate on which the discontinuous film is formed. In the forming of the discontinuous film, a first source gas and a nitriding gas are supplied onto the substrate alternately along with, for example, a carrier gas. In the forming of the tungsten film, a second source gas and a reducing gas are supplied onto the substrate alternately along with, for example, a carrier gas.

Abstract: A method includes forming a first amorphous material, forming a second amorphous material over and in contact with the first material, removing a portion of the second material and the first material to form pillars, and exposing the materials to a temperature between a crystallization temperature of the first material and a crystallization temperature of the second material. The first material and the second material each comprise at least one element selected from the group consisting of silicon and germanium. The second material exhibits a crystallization temperature different than a crystallization temperature of the first material. Semiconductor structures, memory devices, and systems are also disclosed.

Abstract: A method for forming a backside illuminated image sensor with a three-dimensional transistor structure is provided, where forming a gate of the three-dimensional transistor structure includes: forming a source follower transistor and/or a reset transistor with a three-dimensional transistor structure, wherein the source follower transistor and/or the reset transistor correspond to a protruding structure; and forming an insulating sidewall around the protruding structure, forming a groove between the insulating sidewall and a channel region of a transistor corresponding to the protruding structure, and forming a gate of the transistor in the groove, wherein the gate of the transistor is isolated by the insulating sidewall.

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.

Abstract: Subfab components of the processing system may be controlled based on the flow of materials into the processing system. In some embodiments, the flow of an inert gas used to dilute the effluent gases may be controlled in accordance with the flow of one or more precursor gases. Thus, the cost of running the processing system is reduced while mitigating critical EHS concerns.

Abstract: A method for manufacturing a semiconductor device comprising two-dimensional (2D) materials may include: epitaxially forming a first two-dimensional (2D) material layer over a substrate; calculating a mean thickness of the first 2D material layer; comparing the mean thickness of the first 2D material layer with a reference parameter; determining that the mean thickness of the first 2D material layer is not substantially equal to the reference parameter; and after the determining, epitaxially forming a second 2D material layer over the first 2D material layer.

Abstract: An organometallic precursor includes tungsten as a central metal and a cyclopentadienyl ligand bonded to the central metal. A first structure including an alkylsilyl group or a second structure including an allyl ligand is bonded to the cyclopentadienyl ligand or bonded to the central metal.

Abstract: Described herein are alkoxysilylamine precursors having the following Formulae A and B: wherein R1 and R4 are independently selected from a linear or branched C1 to C10 alkyl group, a C3 to C12 alkenyl group, a C3 to C12 alkynyl group, a C4 to C10 cyclic alkyl group, and a C6 to C10 aryl group and wherein R2, R3, R4, R5, and R6 are independently selected from the group consisting of hydrogen, a linear or branched C1 to C10 alkyl group, a C2 to C12 alkenyl group, a C2 to C12 alkynyl group, a C4 to C10 cyclic alkyl, a C6 to C10 aryl group, and a linear or branched C1 to C10 alkoxy group. Also described herein are deposition processes using at least one precursor have Formulae A and/or B described herein.

Abstract: A substrate processing method is for forming a metal film on a target substrate by using a plasma. The method includes loading a target substrate having a silicon-containing layer on a surface thereof into a processing chamber which is pre-coated by a film containing a metal, introducing hydrogen gas and a gaseous compound of the metal and halogen into the processing chamber, generating a plasma, and forming a metal film on the target substrate. The method further includes performing a first reduction process of forming an atmosphere of a plasma obtained by activating hydrogen gas in the processing chamber, unloading the target substrate from the processing chamber, performing a second reduction process of forming an atmosphere of a plasma obtained by activating hydrogen gas in the processing chamber, and loading a next target substrate into the processing chamber.

Abstract: A semiconductor apparatus includes a conductive member penetrating through a first semiconductor layer, a first insulator layer, and a third insulator layer, and connecting a first conductor layer with a second conductor layer. The conductive member has a first region containing copper, and a second region containing a material different from the copper is located at least between a first region and the first semiconductor layer, between the first region and the first insulator layer, and between the first region and the third insulator layer. A diffusion coefficient of the copper to a material is lower than a diffusion coefficient of the copper to the first semiconductor layer and a diffusion coefficient of the copper to the first insulator layer.

Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.

Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.

Abstract: A semiconductor device includes a lower structure including a lower conductor, an upper structure having an opening exposing the lower conductor on the lower structure, and a connection structure filling the opening and connected to the lower conductor. The connection structure includes a first tungsten layer covering an inner surface of the opening and defining a recess region in the opening, and a second tungsten layer filling the recess region on the first tungsten layer. A grain size of the second tungsten layer in an upper portion of the connection structure is greater than a grain size of the second tungsten layer in a lower portion of the connection structure.

Abstract: Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.

Abstract: A method for transferring a graphene sheet from a copper substrate to a functional substrate includes forming the graphene sheet on the copper substrate using chemical vapor deposition, and irradiating the graphene sheet disposed on the copper substrate with a plurality of xenon ions using broad beam irradiation to form a prepared graphene sheet. The prepared graphene sheet is resistant to forming unintentional defects induced during transfer of the prepared graphene sheet to the functional substrate. The method further includes removing the copper substrate from the prepared graphene sheet using an etchant bath, floating the prepared graphene sheet in a floating bath, submerging the functional substrate in the floating bath, and decreasing a fluid level of the floating bath to lower the prepared graphene sheet onto the functional substrate.

Abstract: An inductive wireless power transfer and communication system includes an electrostatic shield for one of the coils. The electrostatic shield is inductively coupled with the coil and is configured as an open circuit. A signal processing element or elements, especially a modulator or a demodulator, are connected across the electrical discontinuity in the electrostatic shield. Because the electrostatic shield is inductively coupled to the coil, the modulator or demodulator can operate on the signal on the coil.

Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, forming a liner layer on the second dielectric layer and in the first and second contact holes, and forming a copper contact in the first and second contact holes.

Abstract: A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is formed in and on the gate electrode. The first contact structure comprises a first portion and a second portion. The first portion is formed in the gate electrode, and the second portion is formed on the first portion.

Abstract: A method for forming a multilayer barrier comprises forming a conductive line over a substrate, depositing a dielectric layer over the conductive line, forming a plug opening in the dielectric layer, forming a multilayer barrier through a plurality of deposition processes and corresponding plasma treatment processes.

Abstract: A method of fabricating the gate structure in a semiconductor device includes forming a gate dielectric layer over a semiconductor substrate. A capping layer is formed over the gate dielectric layer. The capping layer is treated with a first hydrogen plasma to form a first-treated capping layer. A gate electrode is formed over the first-treated capping layer. The method may further includes treating the first-treated capping layer with a nitrogen plasma.

Abstract: Isolation is provided by forming a first trench, depositing a cover layer on the bottom and sidewalls of the first trench, selectively removing the cover layer from the bottom and forming a second trench extending from the bottom of the first trench. The second trench is then substantially filled by thermal oxide formed by oxidation and the first trench is subsequently filled with a deposited dielectric.

Abstract: A driving method of a vertical heat treatment apparatus having a vertical reaction container with a heating part installed includes: performing a process of loading wafers by a substrate holder support to the reaction container; performing a film forming process of storing a first gas at a storage unit and pressurizing the first gas, and alternatively performing a step of supplying the first gas to the vacuum atmosphere reaction container and a step of supplying the second gas to the reaction container; subsequently performing a purge process of unloading the substrate holder support and supplying a purge gas into the reaction container to forcibly peel off a thin film attached to the reaction container; and while the purge process is performed, performing a process of repeating storing the purge gas at the storage unit, pressurizing the gas and discharging the gas into the reaction container.

Abstract: In one embodiment of the present disclosure, a method for electrochemical deposition on a workpiece includes (a) obtaining a workpiece including a feature; (b) depositing a first conductive layer in the feature; (c) moving the workpiece to an integrated electrochemical deposition plating tool configured for hydrogen radical H* surface treatment and electrochemical deposition; (d) treating the first conductive layer using a hydrogen radical H* surface treatment in a treatment chamber of the plating tool to produce a treated first conductive layer; and (e) maintaining the workpiece in the same plating tool and depositing a second conductive layer in the feature on the treated first conductive layer in an electrochemical deposition chamber of the plating tool.

Abstract: An electronic device with an electrode having a superior light transmittance and including a substrate, an amine group-containing compound layer formed on the substrate, and a metal layer formed on the amine group-containing compound layer is provided. In accordance with the present invention, the electrode is easily manufactured when a solution process is used, has performances of a light transmittance, a sheet resistance, and flexibility higher than those of a typical ITO transparent electrode, and a manufacturing cost of the electrode may be reduced.

Abstract: An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.

Abstract: An organic light-emitting diode display includes an organic light-emitting display device including a first electrode, an intermediate layer including an organic emission layer, and a second electrode; a first inorganic encapsulation layer on the second electrode; a second inorganic encapsulation layer on the first inorganic encapsulation layer; and an organic encapsulation layer on the second inorganic encapsulation layer. A refractive index of the first inorganic encapsulation layer is higher than a refractive index of the second inorganic encapsulation layer. The first inorganic encapsulation layer has an extinction coefficient of 0.02 to 0.07 and a refractive index of 2.1 to 2.3 at a blue wavelength.

Abstract: A method of forming a MEMS structure, in which an etch stop layer is formed to be buried within the inter-dielectric layer and, during an etch of the substrate and the inter-dielectric layer from backside to form a chamber, the etch stop layer protect the remaining inter-dielectric layer. The chamber thus formed has an opening at a backside of the substrate, a ceiling opposite to the opening, and a sidewall joining the ceiling. The sidewall may further include a portion of the etch stop layer.

Abstract: Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.

Abstract: Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.