Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.

Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.

Abstract: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment includes a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.

Abstract: A production method for producing a semiconductor device capable of improving surface flatness and suppressing a variation in electrical characteristics of the semiconductor chip, and improving production yield. The production method includes the steps of: forming a first insulating film on a semiconductor substrate and on a conductive pattern film formed on the semiconductor substrate and reducing a thickness of the first insulating film in a region where the conductive pattern film is arranged by patterning; forming a second insulating film and polishing the second insulating film, thereby forming a flattening film; implanting a substance for cleavage into the semiconductor substrate through the flattening film, thereby forming a cleavage layer; transferring the semiconductor chip onto a substrate with an insulating surface so that the chip surface on the side opposite to the semiconductor substrate is attached thereto; and separating the semiconductor substrate from the cleavage layer.

Abstract: In one example, a method for fabricating a solar cell comprising a first electrode, a first-type layer, an intrinsic layer, a second-type layer and a second electrode is disclosed. At least one of the second-type layer, the intrinsic layer and the first-type layer is formed as a crystallized Si layer by an inductively coupled plasma chemical vapor deposition (ICP-CVD) device using mixed gas including hydrogen (H2) gas and silane (SiH4) gas, the mixed gas having a silane gas (SiH4) in a ratio of 0.016 to 0.02.

Abstract: A tray for film formation by a CVD method includes a tray main body (2) and a supporting member (3) mounted on the tray main body (2) for supporting a silicon wafer (5). The supporting member (3) has a holding portion (3c), on which the silicon wafer (5) is directly placed. The holding portion (3c) has its lower surface (3d) apart from a surface (2a) of the tray main body that is opposed to and apart from the supported silicon wafer (5), whereby the thickness distribution of an oxide film formed on the silicon wafer can be made uniform. The tray has a structure for reducing a contact area between the supporting member (3) and the tray main body (2), with the holding portion (3c) having a tilted surface with its inner circumferential side closer to the tray main body surface (2a) that is opposed to the silicon wafer.

Abstract: In a film-forming process with a capacitively-coupled plasma (CCP) chemical vapor deposition (CVD) device, pulse control is performed on a low-frequency radio-frequency power source. During the pulse control, an ON time and an OFF time form one period. Furthermore, in the pulse control, a time interval between a time period from the moment that the electric power supply is stopped till the electron density decreases to a residual plasma threshold capable of causing an arc discharge and a time period from the moment that the electric power supply is stopped till the density of high-temperature electrons decreases to a specific plasma state serves as the OFF time; a saturation time during the rising process of the density of the high-temperature electrons in the plasma after the electric power supply is started serves as an upper limit of the ON time; and electric power is intermittently supplied under the above conditions.

Abstract: In one example, a method for fabricating a solar cell comprising a first electrode, a first-type layer, an intrinsic layer, a second-type layer and a second electrode is disclosed. The method comprising forming a second-type layer including an amorphous silicon (Si) carbide thin film by an inductively coupled plasma chemical vapor deposition (ICP-CVD) device using mixed gas including hydrogen (H2) gas, silane (SiH4) gas, diborane (B2H6) and ethylene (C2H4) gas, wherein the ethylene (C2H4) gas includes 60% hydrogen gas diluted ethylene gas, the diborane gas is 97% hydrogen gas diluted diborane gas, the mixed gas includes 1 to 1.2% ethylene gas and 6 to 6.5% diborane gas.

Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.

Abstract: The sheet structure includes a plurality of linear structure bundles including a plurality of linear structures of carbon atoms arranged at a first gap, and arranged at a second gap larger than the first gap, a graphite layer formed in a region between the plurality of linear structure bundles and connected to the plurality of linear structure bundles, and a filling layer filled in the first gap and the second gap and retaining the plurality of linear structure bundles and the graphite layer.

Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

Abstract: A substrate having, on a base material, a barrier film for preventing copper diffusion containing one or more metal elements selected from tungsten, molybdenum and niobium, a metal element having a catalytic function in electroless plating such as ruthenium, rhodium, and iridium, and nitrogen contained in the form of a nitride of the aforementioned one or more metal elements selected from tungsten, molybdenum and niobium. The barrier film for preventing copper diffusion is manufactured by sputtering in a nitrogen atmosphere using a target containing one or more metal elements selected from tungsten, molybdenum and niobium and the aforementioned metal element having a catalytic function in electroless plating.

Abstract: The present invention provides a semiconductor device formed over an insulating substrate, typically a semiconductor device having a structure in which mounting strength to a wiring board can be increased in an optical sensor, a solar battery, or a circuit using a TFT, and which can make it mount on a wiring board with high density, and further a method for manufacturing the same. According to the present invention, in a semiconductor device, a semiconductor element is formed on an insulating substrate, a concave portion is formed on a side face of the semiconductor device, and a conductive film electrically connected to the semiconductor element is formed in the concave portion.

Abstract: The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0?x?1, 0?y?1, and 0?x+y?1.

Abstract: A light emitting diode chip includes a device for protection against overvoltages, e.g., an ESD protection device. The ESD protection device is integrated into a carrier, on which the semiconductor layer sequence of the light emitting diode chip is situated, and is based on a specific doping of specific regions of said carrier. By way of example, the ESD protection device is embodied as a Zener diode that is connected to the semiconductor layer sequence by means of an electrical conductor structure.

Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.

Abstract: A light emitting device includes a first semiconductor layer of a first conductivity type, an active layer adjacent to the first semiconductor layer, a second semiconductor layer of a second conductivity type and provided adjacent to the active layer, and a passivation layer provided on a side surface of the active layer. The passivation layer may be a semiconductor layer of one of the first conductivity type, the second conductivity type or a first undoped semiconductor layer. A first electrode may be coupled to the first semiconductor layer and a second electrode may be coupled to the second semiconductor layer.

Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Abstract: Reliability and yield of MTJ devices is improved by reducing surface roughness in the MTJ layers of the MTJ devices. Surface roughness is reduced by reducing surface roughness of layers below the MTJ layers such as the bottom electrode layer. Planarizing the bottom electrode layer through chemical mechanical polishing or etch back of spin-on material before depositing the MTJ layers decreases surface roughness of the bottom electrode layer and the MTJ layers. Alternatively, a capping layer may be planarized before deposition of the bottom electrode layer and MTJ layers to reduce surface roughness in the capping layer, the bottom electrode layer, and the MTJ layers.

Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

Abstract: Disclosed herein is a solid-state image pickup device including: a trench formed in an insulating film above a light-receiving portion; a first waveguide core portion provided on an inner wall side of the trench; a second waveguide core portion filled in the trench via the first waveguide core portion; and a rectangular lens formed of the same material as that of the second waveguide core portion and provided integrally with the second waveguide core portion.

Abstract: A light emitting device may include a plurality of nano-structures having a strip shape, each including a first nano-structure and a second nano-structure, the first nano-structures being the same height on the buffer layer.

Abstract: A substrate processing method includes preparing a substrate, a first mask adjacent to a first surface of the substrate and including a first light transmitting portion allowing light to be transmitted therethrough, a condenser adjacent to the first surface, a second mask including a second light transmitting portion, and a photo detecting member including a photo detecting portion detecting light having passed through the second light transmitting portion, the condenser condensing light having passed through the first light transmitting portion toward the second light transmitting portion, the second light transmitting portion allowing the light condensed by the condenser to be transmitted therethrough, and forming a recess in the substrate by laser beam irradiation from a direction opposite to the first surface. When an intensity of the laser beam detected by the photo detecting portion is at or above a specific intensity, the irradiation of the laser beam is stopped.

Abstract: Provided is an IC package.

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

Abstract: Described herein is a method and liquid-based precursor composition for depositing a multicomponent film. In one embodiment, the method and compositions described herein are used to deposit Germanium Tellurium (GeTe), Antimony Tellurium (SbTe), Antimony Germanium (SbGe), Germanium Antimony Tellurium (GST), Indium Antimony Tellurium (IST), Silver Indium Antimony Tellurium (AIST), Cadmium Telluride (CdTe), Cadmium Selenide (CdSe), Zinc Telluride (ZnTe), Zinc Selenide (ZnSe), Copper indium gallium selenide (CIGS) films or other tellurium and selenium based metal compounds for phase change memory and photovoltaic devices.

Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.

Abstract: An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.

Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is has in its backbone, side chains, or both backbone and side chains, multiple secondary or tertiary amide groups that are represented by the following acetamide structure: >N—C(?O)—. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.

Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.

Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.

Abstract: It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive layer; processing the second conductive layer by dry etching with the use of the mask; and processing the first conductive layer by wet etching with the mask left, wherein the etching rate of the second conductive layer is higher than that of the first conductive layer in the dry etching, and wherein the etching rate of the second conductive layer is the same as or more than that of the first conductive layer in the wet etching.

Abstract: Methods of forming cobalt-doped indium-tin oxide structures are shown. Properties of structures include transparency, conductivity, and ferromagnetism. Monolayers that contain indium, monolayers that contain tin, and monolayers that contain cobalt are deposited onto a substrate and subsequently processed to form cobalt-doped indium-tin oxide. Devices that include oxide structures formed with these methods should have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.

Abstract: Systems and methods for single lithography step interconnection metallization using a stop-etch layer are described. A method that includes depositing a stop-etch layer over a semiconductor device, depositing an interconnect metallization material over the stop-etch layer, performing a single lithography step to pattern a mask over the interconnect metallization material, etching the interconnect metallization material in non-masked areas, and removing the stop-etch layer. A system comprises a stop-etch layer material for deposit into a stop-etch layer over a wafer, an interconnect metallization material for deposit over the chrome layer, a lithography operation for patterning a mask over the interconnect metallization material, a first etching compound for etching the interconnect metallization material, where the etching stops at the stop-etch layer, and a second etching compound for removing the stop-etch layer.

Abstract: A method for manufacturing an ion implantation mask is disclosed which includes the steps of: forming an oxide film as a protective film over the entire surface of a semiconductor substrate; forming a thin metal film over the oxide film; and forming an ion-inhibiting layer composed of an ion-inhibiting metal over the thin metal film. The obtained ion implantation mask is used to form a deeper selectively electroconductive region.

Abstract: Solutions for forming dielectric interconnect structures are provided. Specifically, the present invention provides methods of forming a dielectric interconnect structure having a noble metal layer that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma. Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may be provided along an interface between the via and an internal metal layer.

Abstract: To provide a method of manufacturing a semiconductor device, which prevents impurities from entering an SOI substrate. A source gas including one or plural kinds selected from a hydrogen gas, a helium gas, or halogen gas are excited to generate ions, and the ions are added to a bonding substrate to thereby form a fragile layer in the bonding substrate. Then, a region of the bonding substrate that is on and near the surface thereof, i.e., a region ranging from a shallower position than the fragile layer to the surface is removed by etching, polishing, or the like. Next, after attaching the bonding substrate to a base substrate, the bonding substrate is separated at the fragile layer to thereby form a semiconductor film over the base substrate. After forming the semiconductor film over the base substrate, a semiconductor element is formed using the semiconductor film.

Abstract: A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.

Abstract: One or more embodiments relate to a method of forming a semiconductor device, including: providing a substrate; forming a gate stack over the substrate, the gate stack including a control gate over a charge storage layer; forming a conductive layer over the gate stack; etching the conductive layer to remove a portion of the conductive layer; and forming a select gate, the forming the select gate comprising etching a remaining portion of the conductive layer.

Abstract: The present invention describes a method of fabrication of nanocomposite semiconductor materials comprising aligned arrays of metal or semiconductor nanowires incorporated into semiconductor material for application in various electronic, optoelectronic, photonic and plasmonic devices employing self-assembling of the nanowires under light illumination from charged interstitial defect atoms, which are either inherently present in the semiconductor material or artificially introduced in the matrix semiconductor material.

Abstract: A method for fabricating the MEMS device includes providing a substrate. Then, a structural dielectric layer is formed over the substrate at a first side, wherein a diaphragm is embedded in the structural dielectric layer. The substrate is patterned from a second side to form a cavity in corresponding to the diaphragm and a plurality of venting holes in the substrate. An isotropic etching process is performed from the first side and the second side of the substrate via vent holes to remove a dielectric portion of the structural dielectric layer for exposing a central portion of the diaphragm while an end portion is held by a residue portion of the structural dielectric layer.

Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus. The method comprise: a first process of forming a film containing a predetermined element on a substrate by supplying a source gas containing the predetermined element to a substrate processing chamber in which the substrate is accommodated; a second process of removing the source gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; a third process of modifying the predetermined element-containing film formed in the first process by supplying a modification gas that reacts with the predetermined element to the substrate processing chamber; a fourth process of removing the modification gas remaining in the substrate processing chamber by supplying an inert gas to the substrate processing chamber; and a filling process of filling an inert gas in a gas tank connected to the substrate processing chamber.

Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.

Abstract: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus includes a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.

Abstract: A process is disclosed for in-situ fabricating a semiconductor component imbedded in a substrate. A substrate is ablated with a first laser beam to form a void therein. A first conductive element is formed in the void of the substrate with a second laser beam. A semiconductor material is deposited upon the first conductive element with a third laser beam operating in the presence of a depositing atmosphere. A second conductive element is formed on the first semiconductor material with a fourth laser beam. The process may be used for fabricating a Schottky barrier diode or a junction field effect transistor and the like.

Abstract: An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface of the substrate; and a light source facing a top surface of the substrate, configured to irradiate a pulsed light at a pulse width of about 0.1 ms to about 100 ms on the entire top surface of the substrate.

Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a cobalt titanium oxide film on a substrate for use in a variety of electronic systems. The cobalt titanium oxide film may be structured as one or more monolayers. The cobalt titanium oxide film may be formed by atomic layer deposition.

Abstract: In one embodiment the present invention is a method of conducting multiple step multiple chamber chemical vapor deposition while avoiding reactant memory in the relevant reaction chambers. The method includes depositing a layer of semiconductor material on a substrate using vapor deposition in a first deposition chamber followed by evacuation of the growth chamber to reduce vapor deposition source gases remaining in the first deposition chamber after the deposition growth and prior to opening the chamber. The substrate is transferred to a second deposition chamber while isolating the first deposition chamber from the second deposition chamber to prevent reactants present in the first chamber from affecting deposition in the second chamber and while maintaining an ambient that minimizes or eliminates growth stop effects. After the transferring step, an additional layer of a different semiconductor material is deposited on the first deposited layer in the second chamber using vapor deposition.