Selective Deposition (epo) Patents (Class 257/E21.171)
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Patent number: 7674715Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.Type: GrantFiled: December 16, 2008Date of Patent: March 9, 2010Assignee: Applied Materials, Inc.Inventors: Moris Kori, Alfred W. Mak, Jeong Soo Byun, Lawrence Chung-Lai Lei, Hua Chung, Ashok Sinha, Ming Xi
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Patent number: 7670941Abstract: A method for production of semiconductor devices which includes the steps of forming, on an interlayer insulating film formed on a substrate, a copper-containing conductive layer in such a way that its surface is exposed, performing heat treatment with a reducing gas composed mainly of hydrogen on the surface of the conductive layer, performing plasma treatment with a reducing gas on the surface of the conductive layer, thereby permitting the surface of the conductive layer to be reduced and the hydrogen adsorbed by the heat treatment to be released, and forming an oxidation resistance film that covers the surface of the conductive layer such that the surface of the conductive layer is not exposed to an oxygen-containing atmospheric gas after the plasma treatment.Type: GrantFiled: August 18, 2006Date of Patent: March 2, 2010Assignee: Sony CorporationInventors: Koji Kawanami, Kiyotaka Tabuchi
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Patent number: 7659626Abstract: A semiconductor device includes an insulation film 6 formed on a silicon substrate 1, a buried metal interconnect 8 formed in the insulation film 6, and a barrier metal film 7 formed between the insulation film 6 and the metal interconnect 8. The barrier metal film 7 is a metal compound film. The metal compound film is characterized by including at least one of elements forming the insulation film.Type: GrantFiled: May 20, 2005Date of Patent: February 9, 2010Assignee: Panasonic CorporationInventors: Hideo Nakagawa, Atsushi Ikeda, Nobuo Aoi
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Patent number: 7655564Abstract: A method of forming a Ta—Ru metal liner layer for Cu wiring includes: (i) conducting atomic deposition of Ta X times, each atomic deposition of Ta being accomplished by a pulse of hydrogen plasma, wherein X is an integer such that a surface of an underlying layer is not covered with Ta particles; (ii) after step (i), conducting atomic deposition of Ru Y times, each atomic deposition of Ru being accomplished by a pulse of hydrogen plasma, wherein Y is an integer such that the Ta particles are not covered with Ru particles; and (iii) repeating steps (i) and (ii) Z times, thereby forming a Ta—Ru metal liner layer on a Cu wiring substrate.Type: GrantFiled: December 12, 2007Date of Patent: February 2, 2010Assignee: ASM Japan, K.K.Inventors: Hiroshi Shinriki, Daekyun Jeong
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Patent number: 7651934Abstract: Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide.Type: GrantFiled: March 20, 2006Date of Patent: January 26, 2010Assignee: Applied Materials, Inc.Inventors: Dmitry Lubomirsky, Timothy W. Weidman, Arulkumar Shanmugasundram, Nicolay Y. Kovarsky, Kapila Wijekoon
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Publication number: 20100013051Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.Type: ApplicationFiled: September 24, 2009Publication date: January 21, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jay P. John, James A. Kirchgessner, Matthew W. Menner
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Patent number: 7645696Abstract: Methods of depositing thin seed layers that improve continuity of the seed layer as well as adhesion to the barrier layer are provided. According to various embodiments, the methods involve performing an etchback operation in the seed deposition chamber prior to depositing the seed layer. The etch step removes barrier layer overhang and/or oxide that has formed on the barrier layer. It some embodiments, a small deposition flux of seed atoms accompanies the sputter etch flux of argon ions, embedding metal atoms into the barrier layer. The embedded metal atoms create nucleation sites for subsequent seed layer deposition, thereby promoting continuous seed layer film growth, film stability and improved seed layer-barrier layer adhesion.Type: GrantFiled: June 22, 2006Date of Patent: January 12, 2010Assignee: Novellus Systems, Inc.Inventors: Alexander Dulkin, Anil Vijayendran, Tom Yu, Daniel R. Juliano
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Patent number: 7638437Abstract: Provided is an in-situ thin-film deposition method in which a TiSix/Ti layer or TiSix/Ti/TiN layer can be continuously deposited. The method serves to deposit a thin layer as a resistive contact and barrier on a loaded wafer and is performed in a thin-film deposition apparatus including a transfer chamber having a robot arm therein and a plurality of chambers installed as a cluster type on the transfer chamber. The method includes depositing a TiSix layer on the wafer by supplying a first reactive gas containing Ti and a second reactive gas containing Si to a first chamber; and transferring the wafer to a second chamber using the transfer chamber and depositing a TiN layer on the TiSix layer.Type: GrantFiled: October 27, 2005Date of Patent: December 29, 2009Assignee: IPS Ltd.Inventors: Tae Wook Seo, Young Hoon Park
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Patent number: 7638431Abstract: A metal is deposited onto a surface electrochemically using a deposition solution including a metal salt. In making a composite nanostructure, the solution further includes an enhancer that promotes electrochemical deposition of the metal on the nanostructure. In a method of forming catalyzing nanoparticles, the metal preferentially deposits on a selected location of a surface that is exposed through a mask layer instead of on unexposed surfaces. A composite nanostructure apparatus includes an array of nanowires and the metal deposited on at least some nanowire surfaces. Some of the nanowires are heterogeneous, branched and include different adjacent axial segments with controlled axial lengths. In some deposition solutions, the enhancer one or both of controls oxide formation on the surface and causes metal nanocrystal formation. The deposition solution further includes a solvent that carries the metal salt and the enhancer.Type: GrantFiled: September 29, 2006Date of Patent: December 29, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Amir A. Yasseri, Theodore I. Kamins, Shashank Sharma
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Patent number: 7618887Abstract: A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer pattern on the first etch stop layer; forming a first opening by etching the first etch stop layer; forming a second insulation layer and a second etch stop layer on the first insulation layer and the first etch stop layer, and forming a second photosensitive layer pattern on the second etch stop layer; forming a second opening by etching the second etch stop layer; simultaneously forming an inter-connection groove and a via hole by etching the first insulation layer and the second insulation layer using the second etch stop layer and the first etch stop layer as a mask; and forming a metal line by filling the inter-connection groove and the via hole with conductive materials.Type: GrantFiled: December 16, 2005Date of Patent: November 17, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Se-Yeul Bae
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Patent number: 7595263Abstract: Methods for processing substrate to deposit barrier layers of one or more material layers by atomic layer deposition are provided. In one aspect, a method is provided for processing a substrate including depositing a metal nitride barrier layer on at least a portion of a substrate surface by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a nitrogen containing compound and depositing a metal barrier layer on at least a portion of the metal nitride barrier layer by alternately introducing one or more pulses of a metal containing compound and one or more pulses of a reductant. A soak process may be performed on the substrate surface before deposition of the metal nitride barrier layer and/or metal barrier layer.Type: GrantFiled: March 27, 2007Date of Patent: September 29, 2009Assignee: Applied Materials, Inc.Inventors: Hua Chung, Rongjun Wang, Nirmalya Maity
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Patent number: 7576012Abstract: A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma conditions within the chamber effective to react with the first monolayer and form a second monolayer on the substrate which is different in composition from the first monolayer. The second monolayer includes components of the first monolayer and the second precursor. In one implementation, the first and second precursor flowings are successively repeated effective to form a mass of material on the substrate of the second monolayer composition. Additional and other implementations are contemplated.Type: GrantFiled: February 21, 2006Date of Patent: August 18, 2009Assignee: Micron Technology, Inc.Inventors: Trung Tri Doan, Guy T. Blalock, Gurtej S. Sandhu
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Patent number: 7566653Abstract: In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed.Type: GrantFiled: July 31, 2007Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Daniel C. Edelstein
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Patent number: 7563717Abstract: The method includes chemical-mechanical polishing to planarize an insulating interlayer deposited on a lower pattern. The insulating interlayer is polished using a surfactant. The chemical-mechanical polishing includes at least two separate polishing steps of different fluxes of the surfactant. The first polishing step is performed for touching up an upper side of the insulating layer. The second polishing step is performed, after completing the first polishing step, for planarizing the insulating interlayer.Type: GrantFiled: December 28, 2005Date of Patent: July 21, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Ji Hyung Yune
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Patent number: 7563718Abstract: A semiconductor substrate is loaded into a reaction chamber to form a tungsten layer. A source gas including tungsten (W) is introduced into the reaction chamber to grow a crystal nucleus of the tungsten on the semiconductor substrate. A reduction gas containing boron (B) is introduced into the reaction chamber to form a tungsten layer on the semiconductor substrate by actions of the source gas and the reduction gas. A hydrogen (H2) gas is introduced into the reaction chamber to remove the boron (B) remaining in the tungsten layer.Type: GrantFiled: December 29, 2006Date of Patent: July 21, 2009Assignee: Hynix Semiconductor Inc.Inventor: Choon Hwan Kim
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Patent number: 7563730Abstract: Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film.Type: GrantFiled: August 31, 2006Date of Patent: July 21, 2009Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
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Patent number: 7560393Abstract: A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an optional silicon precursor compound.Type: GrantFiled: February 28, 2007Date of Patent: July 14, 2009Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Patent number: 7553757Abstract: An interlayer insulator includes a first interlayer insulator and a second interlayer insulator formed on the first interlayer insulator and having a property of preventing diffusion of copper. A barrier metal film is formed on an inner wall in the wiring trench except an upper end and operative to prevent copper contained in the Cu wiring from diffusing into the interlayer insulator. The Cu wiring is brought into contact with the second interlayer insulator at the upper end and covered with the barrier metal film at a lower portion below the upper end.Type: GrantFiled: February 5, 2007Date of Patent: June 30, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Hisakazu Matsumori
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Publication number: 20090156003Abstract: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes forming a tungsten-containing layer by sequentially exposing a substrate to a processing gas and a tungsten-containing gas during an atomic layer deposition process, wherein the processing gas comprises a boron-containing gas and a nitrogen-containing gas, and forming a tungsten bulk layer over the tungsten-containing layer by exposing the substrate to a deposition gas comprising the tungsten-containing gas and a reactive precursor gas during a chemical vapor deposition process. In one example, the tungsten-containing layer and the tungsten bulk layer are deposited within the same processing chamber.Type: ApplicationFiled: December 16, 2008Publication date: June 18, 2009Inventors: MING XI, Ashok Sinha, Moris Kori, Alfred W. Mak, Xinliang Lu, Ken Kaung Lai, Karl A. Littau
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Patent number: 7544604Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.Type: GrantFiled: August 31, 2006Date of Patent: June 9, 2009Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
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Patent number: 7524765Abstract: A method comprising introducing an organometallic precursor according to a first set of conditions in the presence of a substrate; introducing the organometallic precursor according to a different second set of conditions in the presence of the substrate; and forming a layer comprising a moiety of the organometallic precursor on the substrate according to an atomic layer deposition process. A system comprising a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor comprising a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures formed in a plurality of dielectric layers formed on the substrate and each of the plurality of interconnect structures separated from the plurality of dielectric layers by a barrier layer formed according to an atomic layer deposition process.Type: GrantFiled: November 2, 2005Date of Patent: April 28, 2009Assignee: Intel CorporationInventors: Juan E. Dominquez, Adrien R. Lavoie, Harsono S. Simka, John Plombon, David M. Thompson, John D. Peck
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Patent number: 7507666Abstract: An insulating film having a concave portion is formed on a semiconductor substrate. The inner surface of the concave portion and the upper surface of the insulating film are covered with an auxiliary film made of Cu alloy containing a first metal element other than Cu. A conductive member containing Cu as a main composition is deposited on the auxiliary film, the conductive member being embedded in the concave portion. Heat treatment is performed in an atmosphere containing P compound, Si compound or B compound. With this method, a content of element other than Cu in the conductive member can be reduced and a resistivity can be lowered.Type: GrantFiled: December 6, 2005Date of Patent: March 24, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Yoshiyuki Nakao, Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu
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Patent number: 7504333Abstract: A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.Type: GrantFiled: December 21, 2006Date of Patent: March 17, 2009Assignee: Hynix Semiconductor Inc.Inventors: Cheol Mo Jeong, Whee Won Cho, Eun Soo Kim, Seung Hee Hong
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Publication number: 20090068832Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.Type: ApplicationFiled: August 29, 2008Publication date: March 12, 2009Applicant: ASM INTERNATIONAL N.V.Inventors: Suvi P. Haukka, Ivo Raaijmakers, Wei Min Li, Juhana Kostamo, Hessel Sprey, Christrian J. Werkhoven
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Patent number: 7491646Abstract: A process for fabricating an electrically conductive feature comprising: (a) liquid depositing a low viscosity composition comprising starting ingredients including an organic anine, a silver compound, and optionally an organic acid, to result in a deposited composition; and (b) heating the deposited composition, resulting in the electrically conductive feature comprising silver.Type: GrantFiled: July 20, 2006Date of Patent: February 17, 2009Assignee: Xerox CorporationInventors: Yiliang Wu, Beng S. Ong
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Patent number: 7485560Abstract: An amorphous silicon (Si) film is taken to form a metal silicide of Si—Al(aluminum) under a high temperature. Al atoms is diffused into the amorphous Si film for forming the metal silicide of Si—Al as nucleus site. Then through heating and annealing, a microcrystalline or nano-crystalline silicon thin film is obtained. The whole process is only one process and is done in only one reacting chamber.Type: GrantFiled: November 22, 2006Date of Patent: February 3, 2009Assignee: Atomic Energy Council - Institute of Nuclear Energy ResearchInventors: Tsun-Neng Yang, Shan-Ming Lan
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Patent number: 7473930Abstract: Method and system for providing a dynamically reconfigurable display having nanometer-scale resolution, using a patterned array of multi-wall carbon nanotube (MWCNT) clusters. A diode, phosphor or other light source on each MWCNT cluster is independently activated, and different color light sources (e.g., red, green, blue, grey scale, infrared) can be mixed if desired. Resolution is estimated to be 40-100 nm, and reconfiguration time for each MWCNT cluster is no greater than one microsecond.Type: GrantFiled: July 1, 2005Date of Patent: January 6, 2009Assignee: The United States of America as represented by the United States National Aeronautics and Space AdministrationInventors: Lance D. Delzeit, John F. Schipper
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Publication number: 20080318416Abstract: A method for enhancing an aluminum-copper interconnection in a semiconductor metal line process. In order to solve a reduction in wafer yield due to copper segregation resulting from a time delay during a metal deposition process, copper precipitates are re-solidified into the aluminum film through a quench process of performing annealing on the wafer at a predetermined temperature for a predetermined time correlating to the time delay.Type: ApplicationFiled: June 12, 2008Publication date: December 25, 2008Inventor: Geon-Hi Kim
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Patent number: 7465665Abstract: In one embodiment, a method for forming a tungsten-containing material on a substrate is provided which includes forming a tungsten-containing layer by sequentially exposing a substrate to a processing gas and a tungsten-containing gas during an atomic layer deposition process, wherein the processing gas comprises a boron-containing gas and a nitrogen-containing gas, and forming a tungsten bulk layer over the tungsten-containing layer by exposing the substrate to a deposition gas comprising the tungsten-containing gas and a reactive precursor gas during a chemical vapor deposition process. In one example, the tungsten-containing layer and the tungsten bulk layer are deposited within the same processing chamber.Type: GrantFiled: May 15, 2007Date of Patent: December 16, 2008Assignee: Applied Materials, Inc.Inventors: Ming Xi, Ashok Sinha, Moris Kori, Alfred W. Mak, Xinliang Lu, Ken Kaung Lai, Karl A. Littau
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Patent number: 7465666Abstract: In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers.Type: GrantFiled: June 21, 2007Date of Patent: December 16, 2008Assignee: Applied Materials, Inc.Inventors: Moris Kori, Alfred W. Mak, Jeong Soo Byun, Lawrence Chung-Lai Lei, Hua Chung, Ashok Sinha, Ming Xi
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Publication number: 20080280438Abstract: In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer.Type: ApplicationFiled: July 24, 2008Publication date: November 13, 2008Inventors: Ken Kaung Lai, Ravi Rajagopalan, Amit Khandelwal, Madhu Moorthy, Srinivas Gandikota, Joseph Castro, Aygerinos V. Gelatos, Cheryl Knepfler, Ping Jian, Hongbin Fang, Chao-Ming Huang, Ming Xi, Michael X. Yang, Hua Chung, Jeong Soo Byun
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Patent number: 7407876Abstract: A method for processing a substrate for forming TaC and TaCN films having good adhesion to Cu. The method includes disposing the substrate in a process chamber of a plasma enhanced atomic layer deposition (PEALD) system configured to perform a PEALD process, and depositing a TaC or TaCN film on the substrate using the PEALD process. The PEALD process includes (a) exposing the substrate to a first process material containing tantalum, (b) exposing the substrate to a second process material containing a plasma excited reducing agent, (c) repeating steps (a) (b) a predetermined number of times, (d) exposing the substrate to plasma excited Argon, and (e) repeating steps (c) and (d) until the TaC or TaCN film has a desired thickness. Preferably, purging of the process chamber is performed after one or more of the exposing steps.Type: GrantFiled: March 20, 2006Date of Patent: August 5, 2008Assignee: Tokyo Electron LimitedInventor: Tadahiro Ishizaka
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Patent number: 7405158Abstract: In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer.Type: GrantFiled: January 19, 2005Date of Patent: July 29, 2008Assignee: Applied Materials, Inc.Inventors: Ken Kaung Lai, Ravi Rajagopalan, Amit Khandelwal, Madhu Moorthy, Srinivas Gandikota, Joseph Castro, Averginos V. Gelatos, Cheryl Knepfler, Ping Jian, Hongbin Fang, Chao-Ming Huang, Ming Xi, Michael X. Yang, Hua Chung, Jeong Soo Byun
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Patent number: 7399705Abstract: A method for producing at least one local coating on a substrate is provided, as well as a combinatory substrate having such a local coating, a mask that is removable in a non-destructive manner being arranged on the substrate in a first step; the mask having at least one perforation, the perforation being at least partially filled with a reactive solution in a second step; and a coating reaction of the reactive solution with the substrate surface being induced in a third step to form the local coating.Type: GrantFiled: July 15, 2005Date of Patent: July 15, 2008Assignee: Robert Bosch GmbHInventors: Jörg Jockel, Andreas Müller
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Patent number: 7393783Abstract: The invention includes methods of forming metal-containing layers. The layers can, in particular aspects, consist essentially of metal, or consist of metal. The desired layers can be formed by initially depositing a metal-containing layer which comprises metal and halogen atoms. Subsequently, trialkylaluminum is utilized to remove the halogen atoms from the layer. The layer remaining after removal of the halogen atoms can comprise, consist essentially, or consist of any suitable metal, and in particular aspects can consist essentially of, or consist of, titanium or titanium/aluminum.Type: GrantFiled: July 14, 2005Date of Patent: July 1, 2008Assignee: Micron Technology, Inc.Inventor: Garo J. Derderian
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Patent number: 7393782Abstract: Structures for signal distribution are produced by applying a metallic seed layer over a semiconductor body. An insulating layer is applied over the metallic seed layer and openings in the insulating layer are produced by photolithographic patterning of the insulating layer. Each opening in the insulating layer is trapezoidal in cross section such that an upper portion of the insulating layer is wider than a lower portion of the insulating layer. A conductor is selectively formed over exposed portions of the metallic seed layer. After selectively forming the conductor, the insulating layer is anisotropically etched such that portions of the insulating layer abutting sidewalls of the conductor remain. Alternatively, a second insulating layer can be formed and anisotropically etched.Type: GrantFiled: February 4, 2005Date of Patent: July 1, 2008Assignee: Infineon Technologies AGInventors: Axel Brintzinger, Octavio Trovarelli, Wolfgang Leiberg
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Patent number: 7390756Abstract: A dielectric layer containing an atomic layer deposited zirconium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. Embodiments include forming zirconium silicates as dielectric layers in devices in an integrated circuit. In an embodiment, a zirconium silicon oxide film is formed by atomic layer deposition using a zirconium precursor containing silicon and a silicon precursor. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited zirconium silicon oxide film, and methods for forming such structures.Type: GrantFiled: April 28, 2005Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 7358187Abstract: The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenches (106) that are to be filled to a predetermined filling height (205), a catalyst layer (201) is introduced into the trenches (106) that are to be filled, a reaction layer (202) is deposited catalytically in the trenches (106) that are to be filled, the catalytically deposited reaction layer (202) is densified in the trenches (106) that are to be filled, and the introduction of the catalyst layer (201) and the catalytic deposition of the reaction layer (202) are repeated until the trenches (106) that are to be filled have been filled to the predetermined filling height (205).Type: GrantFiled: June 8, 2005Date of Patent: April 15, 2008Assignee: Infineon Technologies AGInventors: Thomas Hecht, Stefan Jakschik, Uwe Schröder
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Patent number: 7344982Abstract: A chemical vapor deposition reaction system converts a reactant precursor, which includes the metal Ruthenium, to a vapor during a chemical reaction in order to deposit the metal on a semiconductor wafer. The reactant precursor is Bis(2,2,6,6-tetramethyl-3,5-heptanedionato)(1,5-cyclooctadiene)Ru. An energy source provides energy to the reaction chamber to induce the chemical reaction. A controllable metering system alternatively supplies the precursor and oxygen to the reaction chamber. The precursor is supplied into the reaction chamber during a first phase and the oxygen is supplied into the reaction chamber during a second phase, which is non-overlapping with the first phase. A first pump/valve provides the precursor to the reaction chamber, and a second pump/valve provides the oxygen to the reaction chamber, each in response to a controller. The Ruthenium is selectively deposited on oxide sites patterned on a surface of the semiconductor wafer.Type: GrantFiled: November 23, 2004Date of Patent: March 18, 2008Assignee: Arizona Board of Regents, acting for and on behalf of Arizona State UniversityInventors: Jaydeb Goswami, Sandwip Kumar Dey
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Publication number: 20080050927Abstract: A variable temperature and/or reactant dose atomic layer deposition (VTD-ALD) process modulates ALD reactor conditions (e.g., temperature, flow rates, etc.) during growth of a film (e.g., metallic) on a wafer to produce different film properties a different film depths.Type: ApplicationFiled: September 20, 2007Publication date: February 28, 2008Applicant: INTEL CORPORATIONInventor: Ronald Kuse
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Patent number: 7335594Abstract: A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. An absorption layer is formed on the first layer of dielectric material. The absorption layer includes a plurality of titanium atoms bonded to the first layer of dielectric material, a nitrogen atom bonded to each titanium atom, and at least one ligand bonded to the nitrogen atom. The at least one ligand is removed from the nitrogen atoms to form nucleation centers. A metal such as tungsten is bonded to the nucleation centers to form metallic islands. A dielectric material is formed on the nucleation centers and annealed to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.Type: GrantFiled: April 27, 2005Date of Patent: February 26, 2008Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Connie Pin-Chin Wang, Zoran Krivokapic, Suzette Keefe Pangrle, Jinsong Yin
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Publication number: 20080020571Abstract: Methods of forming dense seed layers and structures thereof are provided. Seed layers including a monolayer of molecules having a density of about 0.5 or greater may be manufactured over a metal layer, resulting in a well-defined interface region between the metal layer and a subsequently formed material layer. A seed layer including a monolayer of atoms is formed over the metal layer, the temperature of the workpiece is lowered, and a physisorbed layer is formed over the seed layer, the physisorbed layer including a weakly bound layer of first molecules. A portion of the first molecules in the physisorbed layer are dissociated by irradiating the physisorbed layer with energy, the dissociated atoms of the first molecules being proximate the seed layer. The workpiece is then heated, causing integration of the dissociated atoms of the first molecules of the physisorbed layer into the seed layer and removing the physisorbed layer.Type: ApplicationFiled: October 2, 2007Publication date: January 24, 2008Inventor: Stefan Wurm
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Publication number: 20070298608Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.Type: ApplicationFiled: August 31, 2007Publication date: December 27, 2007Inventors: Steven Johnston, Valery Dubin, Michael McSwiney, Peter Moon
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Patent number: 7312163Abstract: The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.Type: GrantFiled: September 24, 2003Date of Patent: December 25, 2007Assignee: Micron Technology, Inc.Inventors: Garo J. Derderian, Gurtej S. Sandhu
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Publication number: 20070293013Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.Type: ApplicationFiled: June 15, 2006Publication date: December 20, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Jay P. John, James A. Kirchgessner, Matthew W. Menner
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Patent number: 7309650Abstract: A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.Type: GrantFiled: February 24, 2005Date of Patent: December 18, 2007Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Connie Pin-Chin Wang, Lu You, Zoran Krivokapic, Paul Raymond Besser, Suzette Keefe Pangrle
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Patent number: 7306956Abstract: A variable temperature and/or reactant dose atomic layer deposition (VTD-ALD) process modulates ALD reactor conditions (e.g., temperature, flow rates, etc.) during growth of a film (e.g., metallic) on a wafer to produce different film properties a different film depths.Type: GrantFiled: September 30, 2003Date of Patent: December 11, 2007Assignee: Intel CorporationInventor: Ronald John Kuse
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Patent number: 7303991Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.Type: GrantFiled: June 7, 2004Date of Patent: December 4, 2007Assignee: Micron Technology, Inc.Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
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Patent number: 7259057Abstract: Disclosed is a method for forming a capacitor of a semiconductor device capable of improving the film quality of a dielectric film. The method includes the steps of providing a semiconductor substrate having a storage node contact; forming a metal storage electrode on the substrate; forming a dielectric film using any one chosen from a group including a single film made of HfO2, a single film made of Al2O3, and a lamination film made of HfO2 and Al2O3 on the metal storage electrode; performing CF4 plasma treatment on the dielectric film; and forming a metal plate electrode on the dielectric film.Type: GrantFiled: May 6, 2005Date of Patent: August 21, 2007Assignee: Hynix Semiconductor Inc.Inventor: Hyung Bok Choi
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Patent number: 7202166Abstract: Methods are provided for treating germanium surfaces in preparation for subsequent deposition, particularly gate dielectric deposition by atomic layer deposition (ALD). Prior to depositing, the germanium surface is treated with plasma products or thermally reacted with vapor reactants. Examples of surface treatments leave oxygen bridges, nitrogen bridges, —OH, —NH and/or —NH2 terminations that more readily adsorb ALD reactants. The surface treatments avoid deep penetration of the reactants into the germanium bulk but improve nucleation.Type: GrantFiled: August 3, 2004Date of Patent: April 10, 2007Assignee: ASM America, Inc.Inventor: Glen Wilk